drivers: adc: use dts properties for stm32 adc sampling time
Use the new dts properties for sampling time in the STM32 ADC driver: - Get the sampling time from dts - Remove all sampling time macro concatenation. - Simplify/refactor setting of sampling time - Check that sampling time is the same for all series using common channel This also fixes a few cases where wrong sampling times were used for an ADC instance (like ADC4 on U5, or ADC3 on STM32H723). Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit is contained in:
Guillaume Gautier
Fabio Baltieri
parent
aa2933b42f
commit
a7b8a5d61f
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@ -51,6 +51,14 @@ LOG_MODULE_REGISTER(adc_stm32);
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#endif
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#endif
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#define ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(value) \
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(DT_INST_FOREACH_STATUS_OKAY_VARGS(IS_EQ_PROP_OR, \
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num_sampling_time_common_channels,\
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0, value) 0)
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#define IS_EQ_PROP_OR(inst, prop, default_value, compare_value) \
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IS_EQ(DT_INST_PROP_OR(inst, prop, default_value), compare_value) ||
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/* reference voltage for the ADC */
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#define STM32_ADC_VREF_MV DT_INST_PROP(0, vref_mv)
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@ -101,137 +109,12 @@ static const uint32_t table_seq_len[] = {
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};
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#endif
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#define SMP_TIME(x, y) LL_ADC_SAMPLINGTIME_##x##CYCLE##y
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/*
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* Conversion time in ADC cycles. Many values should have been 0.5 less,
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* but the adc api system currently does not support describing 'half cycles'.
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* So all half cycles are counted as one.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F1X)
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static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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SMP_TIME(7, S_5),
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SMP_TIME(13, S_5),
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SMP_TIME(28, S_5),
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SMP_TIME(41, S_5),
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SMP_TIME(55, S_5),
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SMP_TIME(71, S_5),
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SMP_TIME(239, S_5),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X)
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static const uint16_t acq_time_tbl[8] = {3, 15, 28, 56, 84, 112, 144, 480};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(3, S),
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SMP_TIME(15, S),
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SMP_TIME(28, S),
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SMP_TIME(56, S),
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SMP_TIME(84, S),
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SMP_TIME(112, S),
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SMP_TIME(144, S),
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SMP_TIME(480, S),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32F3X)
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#ifdef ADC5_V1_1
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static const uint16_t acq_time_tbl[8] = {2, 3, 5, 8, 20, 62, 182, 602};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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SMP_TIME(2, S_5),
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SMP_TIME(4, S_5),
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SMP_TIME(7, S_5),
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SMP_TIME(19, S_5),
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SMP_TIME(61, S_5),
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SMP_TIME(181, S_5),
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SMP_TIME(601, S_5),
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};
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#else
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static const uint16_t acq_time_tbl[8] = {2, 8, 14, 29, 42, 56, 72, 240};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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SMP_TIME(7, S_5),
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SMP_TIME(13, S_5),
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SMP_TIME(28, S_5),
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SMP_TIME(41, S_5),
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SMP_TIME(55, S_5),
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SMP_TIME(71, S_5),
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SMP_TIME(239, S_5),
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};
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#endif /* ADC5_V1_1 */
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#elif defined(CONFIG_SOC_SERIES_STM32C0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32WLX)
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static const uint16_t acq_time_tbl[8] = {2, 4, 8, 13, 20, 40, 80, 161};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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SMP_TIME(3, S_5),
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SMP_TIME(7, S_5),
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SMP_TIME(12, S_5),
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SMP_TIME(19, S_5),
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SMP_TIME(39, S_5),
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SMP_TIME(79, S_5),
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SMP_TIME(160, S_5),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32L5X) || \
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defined(CONFIG_SOC_SERIES_STM32H5X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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static const uint16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(2, S_5),
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SMP_TIME(6, S_5),
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SMP_TIME(12, S_5),
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SMP_TIME(24, S_5),
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SMP_TIME(47, S_5),
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SMP_TIME(92, S_5),
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SMP_TIME(247, S_5),
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SMP_TIME(640, S_5),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32L1X)
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static const uint16_t acq_time_tbl[8] = {5, 10, 17, 25, 49, 97, 193, 385};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(4, S),
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SMP_TIME(9, S),
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SMP_TIME(16, S),
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SMP_TIME(24, S),
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SMP_TIME(48, S),
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SMP_TIME(96, S),
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SMP_TIME(192, S),
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SMP_TIME(384, S),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32H7X)
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static const uint16_t acq_time_tbl[8] = {2, 3, 9, 17, 33, 65, 388, 811};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(1, _5),
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SMP_TIME(2, S_5),
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SMP_TIME(8, S_5),
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SMP_TIME(16, S_5),
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SMP_TIME(32, S_5),
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SMP_TIME(64, S_5),
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SMP_TIME(387, S_5),
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SMP_TIME(810, S_5),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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static const uint16_t acq_time_tbl[8] = {5, 6, 12, 20, 36, 68, 391, 814};
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static const uint32_t table_samp_time[] = {
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SMP_TIME(5,),
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SMP_TIME(6, S),
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SMP_TIME(12, S),
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SMP_TIME(20, S),
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SMP_TIME(36, S),
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SMP_TIME(68, S),
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SMP_TIME(391, S_5),
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SMP_TIME(814, S),
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};
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#endif
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/* External channels (maximum). */
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#define STM32_CHANNEL_COUNT 20
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/* Number of different sampling time values */
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#define STM32_NB_SAMPLING_TIME 8
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#ifdef CONFIG_ADC_STM32_DMA
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struct stream {
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const struct device *dma_dev;
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@ -254,12 +137,7 @@ struct adc_stm32_data {
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uint32_t channels;
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uint8_t channel_count;
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uint8_t samples_count;
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#if defined(CONFIG_SOC_SERIES_STM32C0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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int8_t acq_time_index;
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#endif
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#ifdef CONFIG_ADC_STM32_DMA
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volatile int dma_error;
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@ -272,6 +150,8 @@ struct adc_stm32_cfg {
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void (*irq_cfg_func)(void);
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struct stm32_pclken pclken;
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const struct pinctrl_dev_config *pcfg;
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const uint16_t sampling_time_table[STM32_NB_SAMPLING_TIME];
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int8_t num_sampling_time_common_channels;
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int8_t temp_channel;
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int8_t vref_channel;
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int8_t vbat_channel;
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@ -1212,80 +1092,81 @@ static int adc_stm32_read_async(const struct device *dev,
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}
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#endif
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static int adc_stm32_check_acq_time(uint16_t acq_time)
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static int adc_stm32_check_acq_time(const struct device *dev, uint16_t acq_time)
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{
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if (acq_time == ADC_ACQ_TIME_MAX) {
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return ARRAY_SIZE(acq_time_tbl) - 1;
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}
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for (int i = 0; i < 8; i++) {
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if (acq_time == ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS,
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acq_time_tbl[i])) {
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return i;
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}
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}
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const struct adc_stm32_cfg *config =
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(const struct adc_stm32_cfg *)dev->config;
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if (acq_time == ADC_ACQ_TIME_DEFAULT) {
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return 0;
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}
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if (acq_time == ADC_ACQ_TIME_MAX) {
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return STM32_NB_SAMPLING_TIME - 1;
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}
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for (int i = 0; i < STM32_NB_SAMPLING_TIME; i++) {
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if (acq_time == ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS,
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config->sampling_time_table[i])) {
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return i;
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}
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}
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LOG_ERR("Conversion time not supported.");
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return -EINVAL;
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}
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static void adc_stm32_setup_speed(const struct device *dev, uint8_t id,
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static int adc_stm32_setup_speed(const struct device *dev, uint8_t id,
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uint8_t acq_time_index)
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{
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const struct adc_stm32_cfg *config =
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(const struct adc_stm32_cfg *)dev->config;
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ADC_TypeDef *adc = config->base;
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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table_samp_time[acq_time_index]);
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#elif defined(CONFIG_SOC_SERIES_STM32C0X)
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LL_ADC_SetSamplingTimeCommonChannels(adc, LL_ADC_SAMPLINGTIME_COMMON_1,
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table_samp_time[acq_time_index]);
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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/* Errata ES0418 and more: ADC sampling time might be one cycle longer */
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if (acq_time_index < 2) {
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acq_time_index = 2;
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}
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LL_ADC_SetSamplingTimeCommonChannels(adc, LL_ADC_SAMPLINGTIME_COMMON_1,
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table_samp_time[acq_time_index]);
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#elif defined(CONFIG_SOC_SERIES_STM32WLX)
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LL_ADC_SetChannelSamplingTime(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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LL_ADC_SAMPLINGTIME_COMMON_1);
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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table_samp_time[acq_time_index]);
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#elif defined(CONFIG_SOC_SERIES_STM32U5X)
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if (adc != ADC4) {
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/*
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* For all series we use the fact that the macros LL_ADC_SAMPLINGTIME_*
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* that should be passed to the set functions are all coded on 3 bits
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* with 0 shift (ie 0 to 7). So acq_time_index is equivalent to the
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* macro we would use for the desired sampling time.
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*/
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switch (config->num_sampling_time_common_channels) {
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case 0:
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#if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(0)
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LL_ADC_SetChannelSamplingTime(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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table_samp_time[acq_time_index]);
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} else {
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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LL_ADC_SAMPLINGTIME_COMMON_1,
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table_samp_time[acq_time_index]);
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}
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#else
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LL_ADC_SetChannelSamplingTime(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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table_samp_time[acq_time_index]);
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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acq_time_index);
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#endif
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break;
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case 1:
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#if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(1)
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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acq_time_index);
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#endif
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break;
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case 2:
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#if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(2)
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LL_ADC_SetChannelSamplingTime(adc,
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__LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
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LL_ADC_SAMPLINGTIME_COMMON_1);
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LL_ADC_SetSamplingTimeCommonChannels(adc,
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LL_ADC_SAMPLINGTIME_COMMON_1,
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acq_time_index);
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#endif
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break;
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default:
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LOG_ERR("Number of common sampling time channels not supported");
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return -EINVAL;
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}
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return 0;
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}
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static int adc_stm32_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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#if defined(CONFIG_SOC_SERIES_STM32C0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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const struct adc_stm32_cfg *config =
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(const struct adc_stm32_cfg *)dev->config;
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struct adc_stm32_data *data = dev->data;
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#endif
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int acq_time_index;
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if (channel_cfg->channel_id >= STM32_CHANNEL_COUNT) {
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@ -1293,24 +1174,24 @@ static int adc_stm32_channel_setup(const struct device *dev,
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return -EINVAL;
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}
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acq_time_index = adc_stm32_check_acq_time(
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acq_time_index = adc_stm32_check_acq_time(dev,
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channel_cfg->acquisition_time);
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if (acq_time_index < 0) {
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return acq_time_index;
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}
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#if defined(CONFIG_SOC_SERIES_STM32C0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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if (data->acq_time_index == -1) {
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data->acq_time_index = acq_time_index;
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} else {
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/* All channels of F0/L0 must have identical acquisition time.*/
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if (acq_time_index != data->acq_time_index) {
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return -EINVAL;
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if (config->num_sampling_time_common_channels) {
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if (data->acq_time_index == -1) {
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data->acq_time_index = acq_time_index;
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} else {
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/*
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* All families that use common channel must have
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* identical acquisition time.
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*/
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if (acq_time_index != data->acq_time_index) {
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return -EINVAL;
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}
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}
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}
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#endif
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if (channel_cfg->differential) {
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LOG_ERR("Differential channels are not supported");
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@ -1327,8 +1208,11 @@ static int adc_stm32_channel_setup(const struct device *dev,
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return -EINVAL;
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}
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adc_stm32_setup_speed(dev, channel_cfg->channel_id,
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acq_time_index);
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if (adc_stm32_setup_speed(dev, channel_cfg->channel_id,
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acq_time_index) != 0) {
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LOG_ERR("Invalid sampling time");
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return -EINVAL;
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}
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LOG_DBG("Channel setup succeeded!");
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@ -1351,19 +1235,17 @@ static int adc_stm32_init(const struct device *dev)
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}
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data->dev = dev;
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#if defined(CONFIG_SOC_SERIES_STM32C0X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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/*
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* All conversion time for all channels on one ADC instance for F0 and
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* L0 series chips has to be the same. For C0 and G0 currently only one
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* For series that use common channels for sampling time, all
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* conversion time for all channels on one ADC instance has to
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* be the same.
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* For series that use two common channels, currently only one
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* of the two available common channel conversion times is used.
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* This additional variable is for checking if the conversion time
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* selection of all channels on one ADC instance is the same.
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*/
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data->acq_time_index = -1;
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#endif
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if (clock_control_on(clk,
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(clock_control_subsys_t) &config->pclken) != 0) {
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@ -1692,6 +1574,9 @@ static const struct adc_stm32_cfg adc_stm32_cfg_##index = { \
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.temp_channel = DT_INST_PROP_OR(index, temp_channel, 0xFF), \
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.vref_channel = DT_INST_PROP_OR(index, vref_channel, 0xFF), \
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.vbat_channel = DT_INST_PROP_OR(index, vbat_channel, 0xFF), \
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.sampling_time_table = DT_INST_PROP(index, sampling_times), \
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.num_sampling_time_common_channels = \
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DT_INST_PROP_OR(index, num_sampling_time_common_channels, 0),\
|
||||
.res_table_size = DT_INST_PROP_LEN(index, resolutions), \
|
||||
.res_table = DT_INST_PROP(index, resolutions), \
|
||||
}; \
|
||||
|
|
|
|||
Loading…
Reference in a new issue