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soc: apollo_lake: fix build errors for GPIO due to DTS changes

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The DTS changes introduced in 7ae220c845
changes the naming of GPIO related macros. This updates the usage
of previous macros via DTS fixup.

Fixes #10993

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung 2018-11-01 10:34:10 -07:00 committed by Kumar Gala
parent 7ad0dd0eec
commit a87a6d82ac
4 changed files with 33 additions and 18 deletions
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16
drivers/gpio/gpio_intel_apl.c
View file

@ -430,22 +430,22 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
.islands = {
{
/* North island */
.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_0,
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_0,
.num_pins = 78,
},
{
/* Northwest island */
.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_1,
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_1,
.num_pins = 77,
},
{
/* West island */
.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_2,
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_2,
.num_pins = 47,
},
{
/* Southwest island */
.reg_base = INTEL_APL_GPIO_0_BASE_ADDRESS_3,
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_3,
.num_pins = 43,
},
},
@ -453,7 +453,7 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
static struct gpio_intel_apl_data gpio_intel_apl_data;
DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL,
DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL,
gpio_intel_apl_init,
&gpio_intel_apl_data, &gpio_intel_apl_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -461,9 +461,9 @@ DEVICE_AND_API_INIT(gpio_intel_apl, INTEL_APL_GPIO_0_LABEL,
static void gpio_intel_apl_irq_config(struct device *dev)
{
IRQ_CONNECT(INTEL_APL_GPIO_0_IRQ_0, INTEL_APL_GPIO_0_IRQ_0_PRIORITY,
IRQ_CONNECT(CONFIG_APL_GPIO_IRQ, CONFIG_APL_GPIO_IRQ_PRIORITY,
gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
INTEL_APL_GPIO_0_IRQ_0_SENSE);
CONFIG_APL_GPIO_IRQ_SENSE);
irq_enable(INTEL_APL_GPIO_0_IRQ_0);
irq_enable(CONFIG_APL_GPIO_IRQ);
}

6
samples/boards/up_squared/gpio_counter/src/main.c
View file

@ -63,6 +63,8 @@ K_SEM_DEFINE(counter_sem, 0, 1);
#define NUM_PINS ARRAY_SIZE(counter_pins)
#define MASK (BIT(NUM_PINS) - 1)
#define GPIO_DEV CONFIG_APL_GPIO_LABEL
void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin)
{
counter++;
@ -71,13 +73,13 @@ void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin)
void main(void)
{
struct device *gpiodev = device_get_binding(INTEL_APL_GPIO_0_LABEL);
struct device *gpiodev = device_get_binding(GPIO_DEV);
u32_t val;
int i, ret;
if (!gpiodev) {
printk("ERROR: cannot get device binding for %s\n",
INTEL_APL_GPIO_0_LABEL);
GPIO_DEV);
return;
}

13
soc/x86/apollo_lake/dts_fixup.h
View file

@ -16,4 +16,17 @@
#define CONFIG_IOAPIC_BASE_ADDRESS INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define CONFIG_APL_GPIO_BASE_ADDRESS_0 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0
#define CONFIG_APL_GPIO_BASE_ADDRESS_1 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1
#define CONFIG_APL_GPIO_BASE_ADDRESS_2 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2
#define CONFIG_APL_GPIO_BASE_ADDRESS_3 INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3
#define CONFIG_APL_GPIO_IRQ INTEL_APL_GPIO_D0C50000_IRQ_0
#define CONFIG_APL_GPIO_IRQ_PRIORITY INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY
#define CONFIG_APL_GPIO_IRQ_SENSE INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE
#define CONFIG_APL_GPIO_LABEL INTEL_APL_GPIO_D0C50000_LABEL
#define CONFIG_APL_GPIO_MEM_SIZE_0 INTEL_APL_GPIO_D0C50000_SIZE_0
#define CONFIG_APL_GPIO_MEM_SIZE_1 INTEL_APL_GPIO_D0C50000_SIZE_1
#define CONFIG_APL_GPIO_MEM_SIZE_2 INTEL_APL_GPIO_D0C50000_SIZE_2
#define CONFIG_APL_GPIO_MEM_SIZE_3 oINTEL_APL_GPIO_D0C50000_SIZE_3
/* End of SoC Level DTS fixup file */

16
soc/x86/apollo_lake/soc.c
View file

@ -102,17 +102,17 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000,
/* for GPIO controller */
#ifdef CONFIG_GPIO_INTEL_APL
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_0,
INTEL_APL_GPIO_0_SIZE_0,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0,
CONFIG_APL_GPIO_MEM_SIZE_0,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_1,
INTEL_APL_GPIO_0_SIZE_1,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1,
CONFIG_APL_GPIO_MEM_SIZE_1,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_2,
INTEL_APL_GPIO_0_SIZE_2,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2,
CONFIG_APL_GPIO_MEM_SIZE_2,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
MMU_BOOT_REGION(INTEL_APL_GPIO_0_BASE_ADDRESS_3,
INTEL_APL_GPIO_0_SIZE_3,
MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3,
CONFIG_APL_GPIO_MEM_SIZE_3,
(MMU_ENTRY_READ | MMU_ENTRY_WRITE));
#endif