drivers: Add counter driver (RTCC) for SiLabs Gecko SoCs
This commit adds counter driver based on RTCC module for SiLabs Gecko SoCs. Tested with SLWSTK6061A / BRD4250B wireless starter kit. Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
parent
240c516316
commit
abbd952d2b
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@ -38,4 +38,11 @@ config GPIO_GECKO_PORTF
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endif # GPIO_GECKO
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if COUNTER
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config COUNTER_GECKO_RTCC
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default y
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endif # COUNTER
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endif # BOARD_EFM32PG_STK3402A
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@ -48,6 +48,8 @@ The efm32pg_stk3402a board configuration supports the following hardware feature
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| COUNTER | on-chip | rtcc |
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+-----------+------------+-------------------------------------+
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| FLASH | on-chip | flash memory |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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@ -73,6 +73,11 @@
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status = "ok";
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};
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&rtcc0 {
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prescaler = <1>;
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status = "ok";
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};
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&gpio {
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location-swo = <0>;
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status = "ok";
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@ -38,4 +38,11 @@ config GPIO_GECKO_PORTF
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endif # GPIO_GECKO
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if COUNTER
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config COUNTER_GECKO_RTCC
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default y
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endif # COUNTER
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endif # BOARD_EFR32_SLWSTK6061A
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@ -60,6 +60,8 @@ The efr32_slwstk6061a board configuration supports the following hardware featur
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| COUNTER | on-chip | rtcc |
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+-----------+------------+-------------------------------------+
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| FLASH | on-chip | flash memory |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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@ -62,6 +62,11 @@
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status = "ok";
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};
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&rtcc0 {
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prescaler = <1>;
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status = "ok";
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};
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&gpio {
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location-swo = <0>;
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status = "ok";
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@ -29,4 +29,11 @@ config GPIO_GECKO_PORTF
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endif # GPIO_GECKO
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if COUNTER
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config COUNTER_GECKO_RTCC
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default y
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endif # COUNTER
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endif # BOARD_EFR32MG_SLTB004A
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@ -63,6 +63,8 @@ The efr32mg_sltb004a board configuration supports the following hardware feature
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| COUNTER | on-chip | rtcc |
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+-----------+------------+-------------------------------------+
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| FLASH | on-chip | flash memory |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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@ -78,6 +78,11 @@
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status = "ok";
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};
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&rtcc0 {
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prescaler = <1>;
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status = "ok";
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};
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&gpio {
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location-swo = <0>;
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status = "ok";
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@ -6,6 +6,7 @@ zephyr_library_sources_ifdef(CONFIG_AON_COUNTER_QMSI counter_qmsi_aon.c)
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zephyr_library_sources_ifdef(CONFIG_AON_TIMER_QMSI counter_qmsi_aonpt.c)
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zephyr_library_sources_ifdef(CONFIG_TIMER_TMR_CMSDK_APB timer_tmr_cmsdk_apb.c)
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zephyr_library_sources_ifdef(CONFIG_TIMER_DTMR_CMSDK_APB timer_dtmr_cmsdk_apb.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_RTCC counter_gecko_rtcc.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT counter_imx_epit.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_RTC counter_mcux_rtc.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_NRF_TIMER counter_nrfx_timer.c)
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@ -20,6 +20,8 @@ config COUNTER_LOG_LEVEL
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help
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Counter logging level.
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source "drivers/counter/Kconfig.gecko"
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source "drivers/counter/Kconfig.qmsi"
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source "drivers/counter/Kconfig.tmr_cmsdk_apb"
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14
drivers/counter/Kconfig.gecko
Normal file
14
drivers/counter/Kconfig.gecko
Normal file
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@ -0,0 +1,14 @@
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# Kconfig - Silicon Labs Gecko Counter driver config
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#
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# Copyright (c) 2019, Piotr Mienkowski
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#
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# SPDX-License-Identifier: Apache-2.0
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config COUNTER_GECKO_RTCC
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bool "Silicon Labs Gecko Counter (RTCC) driver"
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depends on SOC_FAMILY_EXX32
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select SOC_GECKO_CMU
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select SOC_GECKO_RTCC
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help
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Enable counter driver based on RTCC module for Silicon Labs Gecko
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chips.
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drivers/counter/counter_gecko_rtcc.c
Normal file
371
drivers/counter/counter_gecko_rtcc.c
Normal file
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@ -0,0 +1,371 @@
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/*
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* Copyright (c) 2019, Piotr Mienkowski
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include <string.h>
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#include <errno.h>
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#include <kernel.h>
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#include <device.h>
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#include <soc.h>
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#include <em_cmu.h>
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#include <em_rtcc.h>
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#include <counter.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(counter_gecko, CONFIG_COUNTER_LOG_LEVEL);
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#define RTCC_MAX_VALUE (_RTCC_CNT_MASK)
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#define RTCC_ALARM_NUM 2
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struct counter_gecko_config {
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struct counter_config_info info;
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void (*irq_config)(void);
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u32_t prescaler;
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};
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struct counter_gecko_alarm_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct counter_gecko_data {
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struct counter_gecko_alarm_data alarm[RTCC_ALARM_NUM];
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counter_top_callback_t top_callback;
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void *top_user_data;
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};
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#define DEV_NAME(dev) ((dev)->config->name)
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#define DEV_CFG(dev) \
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((struct counter_gecko_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct counter_gecko_data *const)(dev)->driver_data)
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#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
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#define ERRATA_RTCC_E201_MESSAGE \
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"Errata RTCC_E201: In case RTCC prescaler != 1 the module does not " \
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"reset the counter value on CCV1 compare."
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#endif
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/* Map channel id to CC channel provided by the RTCC module */
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static u8_t chan_id2cc_idx(u8_t chan_id)
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{
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u8_t cc_idx;
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switch (chan_id) {
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case 0:
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cc_idx = 2;
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break;
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default:
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cc_idx = 0;
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break;
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}
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return cc_idx;
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}
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static int counter_gecko_start(struct device *dev)
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{
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ARG_UNUSED(dev);
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RTCC_Enable(true);
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return 0;
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}
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static int counter_gecko_stop(struct device *dev)
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{
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ARG_UNUSED(dev);
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RTCC_Enable(false);
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return 0;
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}
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static u32_t counter_gecko_read(struct device *dev)
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{
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ARG_UNUSED(dev);
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return RTCC_CounterGet();
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}
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static int counter_gecko_set_top_value(struct device *dev, u32_t ticks,
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counter_top_callback_t callback,
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void *user_data)
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{
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struct counter_gecko_data *const dev_data = DEV_DATA(dev);
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#ifdef CONFIG_SOC_GECKO_HAS_ERRATA_RTCC_E201
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const struct counter_gecko_config *const dev_cfg = DEV_CFG(dev);
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if (dev_cfg->prescaler != 1) {
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LOG_ERR(ERRATA_RTCC_E201_MESSAGE);
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return -EINVAL;
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}
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#endif
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/* Counter top value can only be changed when all alarms are disabled */
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for (int i = 0; i < RTCC_ALARM_NUM; i++) {
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if (dev_data->alarm[i].callback) {
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return -EBUSY;
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}
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}
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RTCC_IntClear(RTCC_IF_CC1);
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dev_data->top_callback = callback;
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dev_data->top_user_data = user_data;
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RTCC_CounterSet(0);
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RTCC_ChannelCCVSet(1, ticks);
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LOG_DBG("set top value: %u", ticks);
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/* Enable the compare interrupt */
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RTCC_IntEnable(RTCC_IF_CC1);
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return 0;
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}
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static u32_t counter_gecko_get_top_value(struct device *dev)
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{
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ARG_UNUSED(dev);
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return RTCC_ChannelCCVGet(1);
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}
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static u32_t counter_gecko_get_max_relative_alarm(struct device *dev)
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{
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ARG_UNUSED(dev);
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return RTCC_ChannelCCVGet(1);
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}
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static int counter_gecko_set_alarm(struct device *dev, u8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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u32_t count = counter_gecko_read(dev);
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struct counter_gecko_data *const dev_data = DEV_DATA(dev);
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u32_t top_value = counter_gecko_get_top_value(dev);
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u32_t ccv;
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if ((top_value != 0) && (alarm_cfg->ticks > top_value)) {
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return -EINVAL;
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}
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if (dev_data->alarm[chan_id].callback != NULL) {
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return -EBUSY;
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}
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if (alarm_cfg->absolute) {
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ccv = alarm_cfg->ticks;
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} else {
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if (top_value == 0) {
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ccv = count + alarm_cfg->ticks;
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} else {
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u64_t ccv64 = count + alarm_cfg->ticks;
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ccv = (u32_t)(ccv64 % top_value);
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}
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}
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u8_t cc_idx = chan_id2cc_idx(chan_id);
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RTCC_IntClear(RTCC_IF_CC0 << cc_idx);
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dev_data->alarm[chan_id].callback = alarm_cfg->callback;
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dev_data->alarm[chan_id].user_data = alarm_cfg->user_data;
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RTCC_ChannelCCVSet(cc_idx, ccv);
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LOG_DBG("set alarm: channel %u, count %u", chan_id, ccv);
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/* Enable the compare interrupt */
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RTCC_IntEnable(RTCC_IF_CC0 << cc_idx);
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return 0;
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}
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static int counter_gecko_cancel_alarm(struct device *dev, u8_t chan_id)
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{
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struct counter_gecko_data *const dev_data = DEV_DATA(dev);
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u8_t cc_idx = chan_id2cc_idx(chan_id);
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/* Disable the compare interrupt */
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RTCC_IntDisable(RTCC_IF_CC0 << cc_idx);
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RTCC_IntClear(RTCC_IF_CC0 << cc_idx);
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dev_data->alarm[chan_id].callback = NULL;
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dev_data->alarm[chan_id].user_data = NULL;
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RTCC_ChannelCCVSet(cc_idx, 0);
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LOG_DBG("cancel alarm: channel %u", chan_id);
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return 0;
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}
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static u32_t counter_gecko_get_pending_int(struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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static int counter_gecko_init(struct device *dev)
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{
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const struct counter_gecko_config *const dev_cfg = DEV_CFG(dev);
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RTCC_Init_TypeDef rtcc_config = {
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false, /* Don't start counting */
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false, /* Disable RTC during debug halt. */
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false, /* Don't wrap prescaler on CCV0 */
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true, /* Counter wrap on CCV1 */
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(RTCC_CntPresc_TypeDef)CMU_DivToLog2(dev_cfg->prescaler),
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rtccCntTickPresc, /* Count according to prescaler value */
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#if defined(_RTCC_CTRL_BUMODETSEN_MASK)
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false, /* Don't store RTCC counter value in
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* RTCC_CCV2 upon backup mode entry.
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*/
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#endif
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#if defined(_RTCC_CTRL_OSCFDETEN_MASK)
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false, /* Don't enable LFXO fail detection */
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#endif
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#if defined (_RTCC_CTRL_CNTMODE_MASK)
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rtccCntModeNormal, /* Use RTCC in normal mode */
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#endif
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#if defined (_RTCC_CTRL_LYEARCORRDIS_MASK)
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false /* No leap year correction. */
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#endif
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};
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RTCC_CCChConf_TypeDef rtcc_channel_config = {
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rtccCapComChModeCompare, /* Use compare mode */
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rtccCompMatchOutActionPulse,/* Don't care */
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rtccPRSCh0, /* PRS is not used */
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rtccInEdgeNone, /* Capture input is not used */
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rtccCompBaseCnt, /* Compare with base CNT register */
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#if defined (_RTCC_CC_CTRL_COMPMASK_MASK)
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0, /* Compare mask */
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#endif
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#if defined (_RTCC_CC_CTRL_DAYCC_MASK)
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rtccDayCompareModeMonth, /* Don't care */
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#endif
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};
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/* Ensure LE modules are clocked */
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CMU_ClockEnable(cmuClock_CORELE, true);
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#if defined(CMU_LFECLKEN0_RTCC)
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/* Enable LFECLK in CMU (will also enable oscillator if not enabled) */
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CMU_ClockSelectSet(cmuClock_LFE, cmuSelect_LFXO);
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#else
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/* Enable LFACLK in CMU (will also enable oscillator if not enabled) */
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CMU_ClockSelectSet(cmuClock_LFA, cmuSelect_LFXO);
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#endif
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/* Enable RTCC module clock */
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CMU_ClockEnable(cmuClock_RTCC, true);
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/* Initialize RTCC */
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RTCC_Init(&rtcc_config);
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/* Set up compare channels */
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RTCC_ChannelInit(0, &rtcc_channel_config);
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RTCC_ChannelInit(1, &rtcc_channel_config);
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RTCC_ChannelInit(2, &rtcc_channel_config);
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/* Disable module's internal interrupt sources */
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RTCC_IntDisable(_RTCC_IF_MASK);
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RTCC_IntClear(_RTCC_IF_MASK);
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/* Clear the counter */
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RTCC->CNT = 0;
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/* Configure & enable module interrupts */
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dev_cfg->irq_config();
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LOG_INF("Device %s initialized", DEV_NAME(dev));
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return 0;
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}
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static const struct counter_driver_api counter_gecko_driver_api = {
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.start = counter_gecko_start,
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.stop = counter_gecko_stop,
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.read = counter_gecko_read,
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.set_alarm = counter_gecko_set_alarm,
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.cancel_alarm = counter_gecko_cancel_alarm,
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.set_top_value = counter_gecko_set_top_value,
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.get_pending_int = counter_gecko_get_pending_int,
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.get_top_value = counter_gecko_get_top_value,
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.get_max_relative_alarm = counter_gecko_get_max_relative_alarm,
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};
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/* RTCC0 */
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static struct device DEVICE_NAME_GET(counter_gecko_0);
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ISR_DIRECT_DECLARE(counter_gecko_isr_0)
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{
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struct device *const dev = DEVICE_GET(counter_gecko_0);
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struct counter_gecko_data *const dev_data = DEV_DATA(dev);
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counter_alarm_callback_t alarm_callback;
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u32_t count = RTCC_CounterGet();
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u32_t flags = RTCC_IntGetEnabled();
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RTCC_IntClear(flags);
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if (flags & RTCC_IF_CC1) {
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if (dev_data->top_callback) {
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dev_data->top_callback(dev, dev_data->top_user_data);
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}
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}
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for (int i = 0; i < RTCC_ALARM_NUM; i++) {
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u8_t cc_idx = chan_id2cc_idx(i);
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if (flags & (RTCC_IF_CC0 << cc_idx)) {
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if (dev_data->alarm[i].callback) {
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alarm_callback = dev_data->alarm[i].callback;
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dev_data->alarm[i].callback = NULL;
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alarm_callback(dev, i, count,
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dev_data->alarm[i].user_data);
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}
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}
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}
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ISR_DIRECT_PM();
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return 1;
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}
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BUILD_ASSERT((DT_SILABS_GECKO_RTCC_0_PRESCALER > 0U) &&
|
||||
(DT_SILABS_GECKO_RTCC_0_PRESCALER <= 32768U));
|
||||
|
||||
static void counter_gecko_0_irq_config(void)
|
||||
{
|
||||
IRQ_DIRECT_CONNECT(DT_SILABS_GECKO_RTCC_0_IRQ_0,
|
||||
DT_SILABS_GECKO_RTCC_0_IRQ_0_PRIORITY,
|
||||
counter_gecko_isr_0, 0);
|
||||
irq_enable(DT_SILABS_GECKO_RTCC_0_IRQ_0);
|
||||
}
|
||||
|
||||
static const struct counter_gecko_config counter_gecko_0_config = {
|
||||
.info = {
|
||||
.max_top_value = RTCC_MAX_VALUE,
|
||||
.freq = DT_SILABS_GECKO_RTCC_0_CLOCK_FREQUENCY /
|
||||
DT_SILABS_GECKO_RTCC_0_PRESCALER,
|
||||
.flags = COUNTER_CONFIG_INFO_COUNT_UP,
|
||||
.channels = RTCC_ALARM_NUM,
|
||||
},
|
||||
.irq_config = counter_gecko_0_irq_config,
|
||||
.prescaler = DT_SILABS_GECKO_RTCC_0_PRESCALER,
|
||||
};
|
||||
|
||||
static struct counter_gecko_data counter_gecko_0_data;
|
||||
|
||||
DEVICE_AND_API_INIT(counter_gecko_0, DT_SILABS_GECKO_RTCC_0_LABEL,
|
||||
counter_gecko_init, &counter_gecko_0_data, &counter_gecko_0_config,
|
||||
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&counter_gecko_driver_api);
|
|
@ -109,6 +109,16 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtcc0: rtcc@40042000 {
|
||||
compatible = "silabs,gecko-rtcc";
|
||||
reg = <0x40042000 0x184>;
|
||||
interrupts = <30 0>;
|
||||
clock-frequency = <32768>;
|
||||
prescaler = <1>;
|
||||
status = "disabled";
|
||||
label = "RTCC_0";
|
||||
};
|
||||
|
||||
gpio: gpio@4000a400 {
|
||||
compatible = "silabs,efm32-gpio";
|
||||
reg = <0x4000a400 0xf00>;
|
||||
|
|
|
@ -76,6 +76,16 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtcc0: rtcc@40042000 {
|
||||
compatible = "silabs,gecko-rtcc";
|
||||
reg = <0x40042000 0x184>;
|
||||
interrupts = <29 0>;
|
||||
clock-frequency = <32768>;
|
||||
prescaler = <1>;
|
||||
status = "disabled";
|
||||
label = "RTCC_0";
|
||||
};
|
||||
|
||||
gpio: gpio@4000a400 {
|
||||
compatible = "silabs,efr32xg1-gpio";
|
||||
reg = <0x4000a400 0xc00>;
|
||||
|
|
|
@ -105,6 +105,16 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
rtcc0: rtcc@40042000 {
|
||||
compatible = "silabs,gecko-rtcc";
|
||||
reg = <0x40042000 0x184>;
|
||||
interrupts = <30 0>;
|
||||
clock-frequency = <32768>;
|
||||
prescaler = <1>;
|
||||
status = "disabled";
|
||||
label = "RTCC_0";
|
||||
};
|
||||
|
||||
gpio: gpio@4000a400 {
|
||||
compatible = "silabs,efr32mg-gpio";
|
||||
reg = <0x4000a400 0xc00>;
|
||||
|
|
25
dts/bindings/rtc/silabs,gecko-rtcc.yaml
Normal file
25
dts/bindings/rtc/silabs,gecko-rtcc.yaml
Normal file
|
@ -0,0 +1,25 @@
|
|||
#
|
||||
# Copyright (c) 2019, Piotr Mienkowski
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
---
|
||||
title: Silabs Gecko Real Time Counter
|
||||
version: 0.1
|
||||
|
||||
description: >
|
||||
This is a representation of the Silabs Gecko RTCC node
|
||||
|
||||
inherits:
|
||||
!include rtc.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
constraint: "silabs,gecko-rtcc"
|
||||
|
||||
reg:
|
||||
type: array
|
||||
description: mmio register space
|
||||
generation: define
|
||||
category: required
|
||||
...
|
|
@ -179,4 +179,12 @@ config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
|||
If disabled, indicates that pin locations are configured in groups.
|
||||
This is supported by e.g. efm32hg, efm32wg series.
|
||||
|
||||
config SOC_GECKO_HAS_ERRATA_RTCC_E201
|
||||
bool
|
||||
help
|
||||
Set if the SoC is affected by errata RTCC_E201:
|
||||
"When the RTCC is configured with a prescaler, the CCV1 top value enable
|
||||
feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter
|
||||
when RTCC_CNT is equal to RTCC_CC1_CCV, as intended."
|
||||
|
||||
endif # SOC_FAMILY_EXX32
|
||||
|
|
|
@ -18,5 +18,6 @@ config SOC_SERIES_EFR32FG1P
|
|||
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
|
||||
select SOC_GECKO_CMU
|
||||
select SOC_GECKO_GPIO
|
||||
select SOC_GECKO_HAS_ERRATA_RTCC_E201
|
||||
help
|
||||
Enable support for EFR32 FlexGecko MCU series
|
||||
|
|
Loading…
Reference in a new issue