soc: arc: fix ARC_HAS_ACCL_REGS settings

ARC_HAS_ACCL_REGS should set to y to protect ACCL and ACCH registers
during irq. These registers could be used as GPRs by compilers and
therefore need store/restore during irq.

Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
This commit is contained in:
Yuguo Zou 2021-11-22 15:20:43 +08:00 committed by Maureen Helm
parent f18df298f4
commit abeaf94855
7 changed files with 18 additions and 1 deletions

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@ -263,7 +263,6 @@ config CODE_DENSITY
config ARC_HAS_ACCL_REGS
bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
default y if CPU_HS3X
default y if FPU
help
Depending on the configuration, CPU can contain accumulator reg-pair
(also referred to as r58:r59). These can also be used by gcc as GPR so

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@ -47,4 +47,7 @@ config UART_NS16550_ACCESS_WORD_ONLY
default y
depends on UART_NS16550
config ARC_HAS_ACCL_REGS
default y
endif # ARC_HSDK

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@ -50,4 +50,7 @@ config ZTEST_STACKSIZE
endif # ARC_MPU_VER
config ARC_HAS_ACCL_REGS
default y
endif # SOC_NSIM_EM

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@ -47,4 +47,7 @@ config ZTEST_STACKSIZE
endif # ARC_MPU_VER
config ARC_HAS_ACCL_REGS
default y
endif # SOC_NSIM_EM

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@ -30,4 +30,7 @@ config ARC_FIRQ
config CACHE_MANAGEMENT
default y
config ARC_HAS_ACCL_REGS
default y
endif # SOC_NSIM_HS

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@ -36,4 +36,7 @@ config ARC_FIRQ
config CACHE_MANAGEMENT
default y
config ARC_HAS_ACCL_REGS
default y
endif # SOC_NSIM_HS_MPUV6

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@ -33,4 +33,7 @@ config ARC_FIRQ
config CACHE_MANAGEMENT
default y
config ARC_HAS_ACCL_REGS
default y
endif # SOC_NSIM_SEM