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dma: intel: Merge cavs and ace gpdma

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cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit is contained in:
Flavio Ceolin 2022-07-08 14:14:26 -07:00 committed by Carles Cufí
parent d8c7aed261
commit ad8ae7f735
14 changed files with 129 additions and 422 deletions
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3
drivers/dma/CMakeLists.txt
View file

@ -16,10 +16,9 @@ zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_LPC dma_mcux_lpc.c)
zephyr_library_sources_ifdef(CONFIG_DMA_PL330 dma_pl330.c)
zephyr_library_sources_ifdef(CONFIG_DMA_IPROC_PAX dma_iproc_pax_v1.c)
zephyr_library_sources_ifdef(CONFIG_DMA_IPROC_PAX_V2 dma_iproc_pax_v2.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_GPDMA dma_cavs_gpdma.c dma_dw_common.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA dma_cavs_hda.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_HOST_IN dma_cavs_hda_host_in.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_HOST_OUT dma_cavs_hda_host_out.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_LINK_IN dma_cavs_hda_link_in.c)
zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_LINK_OUT dma_cavs_hda_link_out.c)
zephyr_library_sources_ifdef(CONFIG_DMA_ACE_GPDMA dma_ace_gpdma.c dma_dw_common.c)
zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_GPDMA dma_intel_adsp_gpdma.c dma_dw_common.c)

4
drivers/dma/Kconfig
View file

@ -44,9 +44,7 @@ source "drivers/dma/Kconfig.dma_pl330"
source "drivers/dma/Kconfig.iproc_pax"
source "drivers/dma/Kconfig.cavs_gpdma"
source "drivers/dma/Kconfig.ace_gpdma"
source "drivers/dma/Kconfig.intel_adsp_gpdma"
source "drivers/dma/Kconfig.cavs_hda"

16
drivers/dma/Kconfig.ace_gpdma
View file

@ -1,16 +0,0 @@
# DMA configuration options
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config DMA_ACE_GPDMA
bool "ACE General Purpose Direct Memory Access driver"
default $(dt_compat_enabled,$(DT_COMPAT_DMA_ACE_GPDMA))
help
Intel ACE DMA driver.
if DMA_ACE_GPDMA
source "drivers/dma/Kconfig.dw_common"
endif # DMA_ACE_GPDMA

21
drivers/dma/Kconfig.cavs_gpdma
View file

@ -1,21 +0,0 @@
# cAVS GPDMA configuration options
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config DMA_CAVS_GPDMA
bool "CAVS GPDMA DMA driver"
help
Intel cAVS GPDMA DMA driver.
if DMA_CAVS_GPDMA
config DMA_CAVS_GPDMA_HAS_LLP
bool "cAVS GPDMA Linear Link Position Feature"
help
cAVS GPDMA may optionally have a linear link position
feature.
source "drivers/dma/Kconfig.dw_common"
endif # DMA_CAVS_GPDMA

22
drivers/dma/Kconfig.intel_adsp_gpdma Normal file
View file

@ -0,0 +1,22 @@
# DMA configuration options
# Copyright (c) 2022 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
config DMA_INTEL_ADSP_GPDMA
bool "Intel ADSP General Purpose Direct Memory Access driver"
help
Intel ADSP DMA driver.
if DMA_INTEL_ADSP_GPDMA
config DMA_INTEL_ADSP_GPDMA_HAS_LLP
bool "Intel ADSP GPDMA Linear Link Position Feature"
default y if SOC_SERIES_INTEL_ACE1X
help
Intel ADSP GPDMA may optionally have a linear link position
feature.
source "drivers/dma/Kconfig.dw_common"
endif # DMA_INTEL_ADSP_GPDMA

287
drivers/dma/dma_cavs_gpdma.c
View file

@ -1,287 +0,0 @@
/*
* Copyright (c) 2022 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/dma.h>
#define DT_DRV_COMPAT intel_cavs_gpdma
#define GPDMA_CTL_OFFSET 0x0004
#define GPDMA_CTL_FDCGB BIT(0)
#define GPDMA_CHLLPC_OFFSET(channel) (0x0010 + (channel) * 0x10)
#define GPDMA_CHLLPC_EN BIT(7)
#define GPDMA_CHLLPC_DHRS(x) SET_BITS(6, 0, x)
#define GPDMA_CHLLPL(channel) (0x0018 + (channel) * 0x10)
#define GPDMA_CHLLPU(channel) (0x001c + (channel) * 0x10)
#include "dma_dw_common.h"
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dma_cavs_gpdma);
/* Device run time data */
struct cavs_gpdma_data {
struct dw_dma_dev_data dw_data;
};
/* Device constant configuration parameters */
struct cavs_gpdma_cfg {
struct dw_dma_dev_cfg dw_cfg;
uint32_t shim;
};
/* Disables automatic clock gating (force disable clock gate) */
static void cavs_gpdma_clock_enable(const struct device *dev)
{
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
sys_write32(GPDMA_CTL_FDCGB, reg);
}
static void cavs_gpdma_llp_config(const struct device *dev, uint32_t channel,
uint32_t addr)
{
#ifdef CONFIG_DMA_CAVS_GPDMA_HAS_LLP
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), GPDMA_CHLLPC_DHRS(addr));
#endif
}
static inline void cavs_gpdma_llp_enable(const struct device *dev,
uint32_t channel)
{
#ifdef CONFIG_DMA_CAVS_GPDMA_HAS_LLP
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
uint32_t val;
val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));
if (!(val & GPDMA_CHLLPC_EN)) {
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), val | GPDMA_CHLLPC_EN);
}
#endif
}
static inline void cavs_gpdma_llp_disable(const struct device *dev,
uint32_t channel)
{
#ifdef CONFIG_DMA_CAVS_GPDMA_HAS_LLP
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
uint32_t val;
val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), val | GPDMA_CHLLPC_EN);
#endif
}
static inline void cavs_gpdma_llp_read(const struct device *dev,
uint32_t channel,
uint32_t *llp_l,
uint32_t *llp_u)
{
#ifdef CONFIG_DMA_CAVS_GPDMA_HAS_LLP
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
*llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));
*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));
#endif
}
static int cavs_gpdma_config(const struct device *dev, uint32_t channel,
struct dma_config *cfg)
{
int res = dw_dma_config(dev, channel, cfg);
if (res != 0) {
return res;
}
struct dma_block_config *block_cfg = cfg->head_block;
/* Assume all scatter/gathers are for the same device? */
switch (cfg->channel_direction) {
case MEMORY_TO_PERIPHERAL:
LOG_DBG("%s: dma %s configuring llp for destination %x",
__func__, dev->name, block_cfg->dest_address);
cavs_gpdma_llp_config(dev, channel, block_cfg->dest_address);
break;
case PERIPHERAL_TO_MEMORY:
LOG_DBG("%s: dma %s configuring llp for source %x",
__func__, dev->name, block_cfg->source_address);
cavs_gpdma_llp_config(dev, channel, block_cfg->source_address);
break;
default:
break;
}
return res;
}
static int cavs_gpdma_start(const struct device *dev, uint32_t channel)
{
int ret;
cavs_gpdma_llp_enable(dev, channel);
ret = dw_dma_start(dev, channel);
if (ret != 0) {
cavs_gpdma_llp_disable(dev, channel);
}
return ret;
}
static int cavs_gpdma_stop(const struct device *dev, uint32_t channel)
{
int ret;
ret = dw_dma_stop(dev, channel);
if (ret == 0) {
cavs_gpdma_llp_disable(dev, channel);
}
return ret;
}
int cavs_gpdma_copy(const struct device *dev, uint32_t channel,
uint32_t src, uint32_t dst, size_t size)
{
struct dw_dma_dev_data *const dev_data = dev->data;
struct dw_dma_chan_data *chan_data;
int i = 0;
if (channel >= DW_MAX_CHAN) {
return -EINVAL;
}
chan_data = &dev_data->chan[channel];
/* default action is to clear the DONE bit for all LLI making
* sure the cache is coherent between DSP and DMAC.
*/
for (i = 0; i < chan_data->lli_count; i++) {
chan_data->lli[i].ctrl_hi &= ~DW_CTLH_DONE(1);
}
chan_data->ptr_data.current_ptr += size;
if (chan_data->ptr_data.current_ptr >= chan_data->ptr_data.end_ptr) {
chan_data->ptr_data.current_ptr = chan_data->ptr_data.start_ptr +
(chan_data->ptr_data.current_ptr - chan_data->ptr_data.end_ptr);
}
return 0;
}
int cavs_gpdma_init(const struct device *dev)
{
const struct cavs_gpdma_cfg *const dev_cfg = dev->config;
/* Disable dynamic clock gating appropriately before initializing */
cavs_gpdma_clock_enable(dev);
/* Disable all channels and Channel interrupts */
int ret = dw_dma_setup(dev);
if (ret != 0) {
LOG_ERR("%s: dma %s failed to initialize", __func__, dev->name);
goto out;
}
/* Configure interrupts */
dev_cfg->dw_cfg.irq_config();
LOG_INF("%s: dma %s initialized", __func__, dev->name);
out:
return 0;
}
static const struct dma_driver_api cavs_gpdma_driver_api = {
.config = cavs_gpdma_config,
.reload = cavs_gpdma_copy,
.start = cavs_gpdma_start,
.stop = cavs_gpdma_stop,
.suspend = dw_dma_suspend,
.resume = dw_dma_resume,
.get_status = dw_dma_get_status,
};
#define CAVS_GPDMA_CHAN_ARB_DATA(inst) \
static struct dw_drv_plat_data dmac##inst = { \
.chan[0] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[1] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[2] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[3] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[4] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[5] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[6] = { \
.class = 6, \
.weight = 0, \
}, \
.chan[7] = { \
.class = 6, \
.weight = 0, \
}, \
}
#define CAVS_GPDMA_INIT(inst) \
CAVS_GPDMA_CHAN_ARB_DATA(inst); \
static void cavs_gpdma##inst##_irq_config(void); \
\
static const struct cavs_gpdma_cfg cavs_gpdma##inst##_config = { \
.dw_cfg = { \
.base = DT_INST_REG_ADDR(inst), \
.irq_config = cavs_gpdma##inst##_irq_config, \
}, \
.shim = DT_INST_PROP_BY_IDX(inst, shim, 0), \
}; \
\
static struct cavs_gpdma_data cavs_gpdma##inst##_data = { \
.dw_data = { \
.channel_data = &dmac##inst, \
}, \
}; \
\
\
DEVICE_DT_INST_DEFINE(inst, \
&cavs_gpdma_init, \
NULL, \
&cavs_gpdma##inst##_data, \
&cavs_gpdma##inst##_config, POST_KERNEL, \
CONFIG_DMA_INIT_PRIORITY, \
&cavs_gpdma_driver_api); \
\
static void cavs_gpdma##inst##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), dw_dma_isr, \
DEVICE_DT_INST_GET(inst), \
DT_INST_IRQ(inst, sense)); \
irq_enable(DT_INST_IRQN(inst)); \
}
DT_INST_FOREACH_STATUS_OKAY(CAVS_GPDMA_INIT)

165
drivers/dma/dma_ace_gpdma.c → drivers/dma/dma_intel_adsp_gpdma.c
View file

@ -4,11 +4,11 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "drivers/dma.h"
#define DT_DRV_COMPAT intel_ace_gpdma
#include <zephyr/drivers/dma.h>
#define DT_DRV_COMPAT intel_adsp_gpdma
/* TODO make device tree defined? */
#define GPDMA_CTL_OFFSET 0x0004
#define GPDMA_CTL_FDCGB BIT(0)
#define GPDMA_CTL_DGCD BIT(30)
/* TODO make device tree defined? */
@ -24,68 +24,78 @@
#define SHIM_CLKCTL_LPGPDMA_SPA BIT(0)
#define SHIM_CLKCTL_LPGPDMA_CPA BIT(8)
#include <dma/dma_dw_common.h>
#include "dma_dw_common.h"
#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(dma_ace_gpdma);
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dma_intel_adsp_gpdma);
/* Device run time data */
struct ace_gpdma_data {
struct intel_adsp_gpdma_data {
struct dw_dma_dev_data dw_data;
};
/* Device constant configuration parameters */
struct ace_gpdma_cfg {
struct intel_adsp_gpdma_cfg {
struct dw_dma_dev_cfg dw_cfg;
uint32_t shim;
};
static void ace_gpdma_llp_config(const struct device *dev, uint32_t channel,
uint32_t addr)
static void intel_adsp_gpdma_llp_config(const struct device *dev,
uint32_t channel, uint32_t addr)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
#ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_HAS_LLP
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), GPDMA_CHLLPC_DHRS(addr));
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),
GPDMA_CHLLPC_DHRS(addr));
#endif
}
static inline void ace_gpdma_llp_enable(const struct device *dev,
uint32_t channel)
static inline void intel_adsp_gpdma_llp_enable(const struct device *dev,
uint32_t channel)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
#ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_HAS_LLP
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
uint32_t val;
val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));
if (!(val & GPDMA_CHLLPC_EN)) {
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), val | GPDMA_CHLLPC_EN);
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),
val | GPDMA_CHLLPC_EN);
}
#endif
}
static inline void ace_gpdma_llp_disable(const struct device *dev,
uint32_t channel)
static inline void intel_adsp_gpdma_llp_disable(const struct device *dev,
uint32_t channel)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
#ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_HAS_LLP
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
uint32_t val;
val = dw_read(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel));
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel), val | GPDMA_CHLLPC_EN);
dw_write(dev_cfg->shim, GPDMA_CHLLPC_OFFSET(channel),
val | GPDMA_CHLLPC_EN);
#endif
}
static inline void ace_gpdma_llp_read(const struct device *dev,
uint32_t channel,
uint32_t *llp_l,
uint32_t *llp_u)
static inline void intel_adsp_gpdma_llp_read(const struct device *dev,
uint32_t channel, uint32_t *llp_l,
uint32_t *llp_u)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
#ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_HAS_LLP
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
*llp_l = dw_read(dev_cfg->shim, GPDMA_CHLLPL(channel));
*llp_u = dw_read(dev_cfg->shim, GPDMA_CHLLPU(channel));
#endif
}
static int ace_gpdma_config(const struct device *dev, uint32_t channel,
struct dma_config *cfg)
static int intel_adsp_gpdma_config(const struct device *dev, uint32_t channel,
struct dma_config *cfg)
{
int res = dw_dma_config(dev, channel, cfg);
@ -100,12 +110,14 @@ static int ace_gpdma_config(const struct device *dev, uint32_t channel,
case MEMORY_TO_PERIPHERAL:
LOG_DBG("%s: dma %s configuring llp for destination %x",
__func__, dev->name, block_cfg->dest_address);
ace_gpdma_llp_config(dev, channel, block_cfg->dest_address);
intel_adsp_gpdma_llp_config(dev, channel,
block_cfg->dest_address);
break;
case PERIPHERAL_TO_MEMORY:
LOG_DBG("%s: dma %s configuring llp for source %x",
__func__, dev->name, block_cfg->source_address);
ace_gpdma_llp_config(dev, channel, block_cfg->source_address);
intel_adsp_gpdma_llp_config(dev, channel,
block_cfg->source_address);
break;
default:
break;
@ -114,30 +126,30 @@ static int ace_gpdma_config(const struct device *dev, uint32_t channel,
return res;
}
static int ace_gpdma_start(const struct device *dev, uint32_t channel)
static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel)
{
int ret;
ace_gpdma_llp_enable(dev, channel);
intel_adsp_gpdma_llp_enable(dev, channel);
ret = dw_dma_start(dev, channel);
if (ret != 0) {
ace_gpdma_llp_disable(dev, channel);
intel_adsp_gpdma_llp_disable(dev, channel);
}
return ret;
}
static int ace_gpdma_stop(const struct device *dev, uint32_t channel)
static int intel_adsp_gpdma_stop(const struct device *dev, uint32_t channel)
{
int ret;
ret = dw_dma_stop(dev, channel);
if (ret == 0) {
ace_gpdma_llp_disable(dev, channel);
intel_adsp_gpdma_llp_disable(dev, channel);
}
return ret;
}
int ace_gpdma_copy(const struct device *dev, uint32_t channel,
static int intel_adsp_gpdma_copy(const struct device *dev, uint32_t channel,
uint32_t src, uint32_t dst, size_t size)
{
struct dw_dma_dev_data *const dev_data = dev->data;
@ -166,56 +178,69 @@ int ace_gpdma_copy(const struct device *dev, uint32_t channel,
}
/* Disables automatic clock gating (force disable clock gate) */
static void ace_gpdma_clock_enable(const struct device *dev)
static void intel_adsp_gpdma_clock_enable(const struct device *dev)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
uint32_t val = sys_read32(reg) | GPDMA_CTL_DGCD;
uint32_t val;
if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE1X)) {
val = sys_read32(reg) | GPDMA_CTL_DGCD;
} else {
val = GPDMA_CTL_FDCGB;
}
sys_write32(val, reg);
}
static void ace_gpdma_select_owner(const struct device *dev)
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
static void intel_adsp_gpdma_select_owner(const struct device *dev)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
uint32_t val = sys_read32(reg) | GPDMA_OSEL(0x3);
sys_write32(val, reg);
}
static int ace_gpdma_enable(const struct device *dev)
static int intel_adsp_gpdma_enable(const struct device *dev)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET;
sys_write32(SHIM_CLKCTL_LPGPDMA_SPA, reg);
if (!WAIT_FOR((sys_read32(reg) & SHIM_CLKCTL_LPGPDMA_CPA), 10000, k_busy_wait(1))) {
if (!WAIT_FOR((sys_read32(reg) & SHIM_CLKCTL_LPGPDMA_CPA), 10000,
k_busy_wait(1))) {
return -1;
}
return 0;
}
#endif
int ace_gpdma_init(const struct device *dev)
int intel_adsp_gpdma_init(const struct device *dev)
{
const struct ace_gpdma_cfg *const dev_cfg = dev->config;
const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config;
int ret;
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
/* Power up */
ret = ace_gpdma_enable(dev);
ret = intel_adsp_gpdma_enable(dev);
if (ret != 0) {
LOG_ERR("%s: dma %s failed to initialize", __func__,
dev->name);
goto out;
}
#endif
/* Disable dynamic clock gating appropriately before initializing */
ace_gpdma_clock_enable(dev);
intel_adsp_gpdma_clock_enable(dev);
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
/* DW DMA Owner Select to DSP */
ace_gpdma_select_owner(dev);
intel_adsp_gpdma_select_owner(dev);
#endif
/* Disable all channels and Channel interrupts */
ret = dw_dma_setup(dev);
@ -235,17 +260,17 @@ out:
return 0;
}
static const struct dma_driver_api ace_gpdma_driver_api = {
.config = ace_gpdma_config,
.reload = ace_gpdma_copy,
.start = ace_gpdma_start,
.stop = ace_gpdma_stop,
static const struct dma_driver_api intel_adsp_gpdma_driver_api = {
.config = intel_adsp_gpdma_config,
.reload = intel_adsp_gpdma_copy,
.start = intel_adsp_gpdma_start,
.stop = intel_adsp_gpdma_stop,
.suspend = dw_dma_suspend,
.resume = dw_dma_resume,
.get_status = dw_dma_get_status,
};
#define ACE_GPDMA_CHAN_ARB_DATA(inst) \
#define INTEL_ADSP_GPDMA_CHAN_ARB_DATA(inst) \
static struct dw_drv_plat_data dmac##inst = { \
.chan[0] = { \
.class = 6, \
@ -281,19 +306,19 @@ static const struct dma_driver_api ace_gpdma_driver_api = {
}, \
}
#define ACE_GPDMA_INIT(inst) \
ACE_GPDMA_CHAN_ARB_DATA(inst); \
static void ace_gpdma##inst##_irq_config(void); \
#define INTEL_ADSP_GPDMA_INIT(inst) \
INTEL_ADSP_GPDMA_CHAN_ARB_DATA(inst); \
static void intel_adsp_gpdma##inst##_irq_config(void); \
\
static const struct ace_gpdma_cfg ace_gpdma##inst##_config = { \
static const struct intel_adsp_gpdma_cfg intel_adsp_gpdma##inst##_config = {\
.dw_cfg = { \
.base = DT_INST_REG_ADDR(inst), \
.irq_config = ace_gpdma##inst##_irq_config, \
.base = DT_INST_REG_ADDR(inst), \
.irq_config = intel_adsp_gpdma##inst##_irq_config,\
}, \
.shim = DT_INST_PROP_BY_IDX(inst, shim, 0), \
}; \
\
static struct ace_gpdma_data ace_gpdma##inst##_data = { \
static struct intel_adsp_gpdma_data intel_adsp_gpdma##inst##_data = {\
.dw_data = { \
.channel_data = &dmac##inst, \
}, \
@ -301,20 +326,20 @@ static const struct dma_driver_api ace_gpdma_driver_api = {
\
\
DEVICE_DT_INST_DEFINE(inst, \
&ace_gpdma_init, \
&intel_adsp_gpdma_init, \
NULL, \
&ace_gpdma##inst##_data, \
&ace_gpdma##inst##_config, POST_KERNEL, \
CONFIG_DMA_INIT_PRIORITY, \
&ace_gpdma_driver_api); \
&intel_adsp_gpdma##inst##_data, \
&intel_adsp_gpdma##inst##_config, POST_KERNEL,\
CONFIG_DMA_INIT_PRIORITY, \
&intel_adsp_gpdma_driver_api); \
\
static void ace_gpdma##inst##_irq_config(void) \
static void intel_adsp_gpdma##inst##_irq_config(void) \
{ \
IRQ_CONNECT(DT_INST_IRQN(inst), \
IRQ_CONNECT(DT_INST_IRQN(inst), \
DT_INST_IRQ(inst, priority), dw_dma_isr, \
DEVICE_DT_INST_GET(inst), \
DT_INST_IRQ(inst, sense)); \
irq_enable(DT_INST_IRQN(inst)); \
irq_enable(DT_INST_IRQN(inst)); \
}
DT_INST_FOREACH_STATUS_OKAY(ACE_GPDMA_INIT)
DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_GPDMA_INIT)

13
dts/bindings/dma/intel,ace-gpdma.yaml
View file

@ -1,13 +0,0 @@
# Copyright (c) 2022 Intel Corporation. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
description: Intel ACE Designware based General Purpose DMA Controller node
compatible: "intel,ace-gpdma"
include: snps,designware-dma.yaml
properties:
shim:
type: array
required: true

4
dts/bindings/dma/intel,cavs-gpdma.yaml → dts/bindings/dma/intel,adsp-gpdma.yaml
View file

@ -1,9 +1,9 @@
# Copyright (c) 2022 Intel Corporation. All rights reserved.
# SPDX-License-Identifier: Apache-2.0
description: Intel cAVS Designware based General Purpose DMA Controller node
description: Intel ADSP Designware based General Purpose DMA Controller node
compatible: "intel,cavs-gpdma"
compatible: "intel,adsp-gpdma"
include: snps,designware-dma.yaml

4
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -128,7 +128,7 @@
};
lpgpdma0: dma@7c000 {
compatible = "intel,ace-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0007c000 0x1000>;
shim = <0x0007c800 0x1000>;
@ -139,7 +139,7 @@
};
lpgpdma1: dma@7d000 {
compatible = "intel,ace-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0007d000 0x1000>;
shim = <0x0007d800 0x1000>;

4
dts/xtensa/intel/intel_cavs.dtsi
View file

@ -9,7 +9,7 @@
/ {
soc {
lpgpdma0: dma@7c000 {
compatible = "intel,cavs-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0007c000 0x1000>;
shim = <0x00078400 0x100>;
@ -21,7 +21,7 @@
};
lpgpdma1: dma@7d000 {
compatible = "intel,cavs-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0007d000 0x1000>;
shim = <0x00078500 0x100>;

4
dts/xtensa/intel/intel_cavs15.dtsi
View file

@ -136,7 +136,7 @@
};
lpgpdma0: dma@c000 {
compatible = "intel,cavs-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0000c000 0x1000>;
shim = <0x00000c00 0x080>;
@ -148,7 +148,7 @@
};
lpgpdma1: dma@d000 {
compatible = "intel,cavs-gpdma";
compatible = "intel,adsp-gpdma";
#dma-cells = <1>;
reg = <0x0000d000 0x1000>;
shim = <0x00000c80 0x080>;

2
soc/xtensa/intel_adsp/Kconfig.defconfig
View file

@ -15,7 +15,7 @@ config XTENSA_UNCACHED_REGION
if INTEL_ADSP_CAVS
config DMA_CAVS_GPDMA
config DMA_INTEL_ADSP_GPDMA
default y
depends on DMA

2
soc/xtensa/intel_adsp/ace_v1x/soc.c
View file

@ -104,7 +104,7 @@ static __imr void power_init_mtl(void)
/* Disable idle power gating */
DFDSPBRCP.bootctl[0].bctl |= DFDSPBRCP_BCTL_WAITIPCG | DFDSPBRCP_BCTL_WAITIPPG;
#if CONFIG_DMA_ACE_GPDMA
#if CONFIG_DMA_INTEL_ADSP_GPDMA
sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(0));
sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(1));
#endif