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arch: arm: z_arm_prep_c -> z_prep_c

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Rename to use common naming for z_prep_c applied to all architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-12-08 08:08:54 -05:00
parent fb19d532ed
commit ae39c3f7d7
6 changed files with 9 additions and 9 deletions
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2
arch/arm/core/cortex_a_r/prep_c.c
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@ -145,7 +145,7 @@ extern FUNC_NORETURN void z_cstart(void);
* This routine prepares for the execution of and runs C code. * This routine prepares for the execution of and runs C code.
* *
*/ */
void z_arm_prep_c(void) void z_prep_c(void)
{ {
/* Initialize tpidruro with our struct _cpu instance address */ /* Initialize tpidruro with our struct _cpu instance address */
write_tpidruro((uintptr_t)&_kernel.cpus[0]); write_tpidruro((uintptr_t)&_kernel.cpus[0]);

4
arch/arm/core/cortex_a_r/reset.S
View file

@ -42,7 +42,7 @@ GTEXT(z_arm_platform_init)
* and interrupts are disabled. The processor architectural registers are in * and interrupts are disabled. The processor architectural registers are in
* an indeterminate state. * an indeterminate state.
* *
* When these steps are completed, jump to z_arm_prep_c(), which will finish * When these steps are completed, jump to z_prep_c(), which will finish
* setting up the system for running C code. * setting up the system for running C code.
* *
*/ */
@ -229,7 +229,7 @@ EL1_Reset_Handler:
_primary_core: _primary_core:
#endif #endif
ldr r4, =z_arm_prep_c ldr r4, =z_prep_c
ldr r5, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE) ldr r5, =(z_arm_fiq_stack + CONFIG_ARMV7_FIQ_STACK_SIZE)
ldr r6, =(z_interrupt_stacks + CONFIG_ISR_STACK_SIZE) ldr r6, =(z_interrupt_stacks + CONFIG_ISR_STACK_SIZE)
ldr r7, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE) ldr r7, =(z_arm_abort_stack + CONFIG_ARMV7_EXCEPTION_STACK_SIZE)

2
arch/arm/core/cortex_a_r/vector_table.h
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@ -40,7 +40,7 @@ GTEXT(z_arm_data_abort)
GTEXT(z_arm_pendsv) GTEXT(z_arm_pendsv)
GTEXT(z_arm_reserved) GTEXT(z_arm_reserved)
GTEXT(z_arm_prep_c) GTEXT(z_prep_c)
GTEXT(_isr_wrapper) GTEXT(_isr_wrapper)
#else /* _ASMLANGUAGE */ #else /* _ASMLANGUAGE */

2
arch/arm/core/cortex_m/prep_c.c
View file

@ -179,7 +179,7 @@ extern FUNC_NORETURN void z_cstart(void);
* This routine prepares for the execution of and runs C code. * This routine prepares for the execution of and runs C code.
* *
*/ */
void z_arm_prep_c(void) void z_prep_c(void)
{ {
relocate_vector_table(); relocate_vector_table();
#if defined(CONFIG_CPU_HAS_FPU) #if defined(CONFIG_CPU_HAS_FPU)

6
arch/arm/core/cortex_m/reset.S
View file

@ -53,7 +53,7 @@ GTEXT(arch_pm_s2ram_resume)
* MSP is to be set up to point to the one-and-only interrupt stack during * MSP is to be set up to point to the one-and-only interrupt stack during
* later boot. That would not be possible if in use for running C code. * later boot. That would not be possible if in use for running C code.
* *
* When these steps are completed, jump to z_arm_prep_c(), which will finish * When these steps are completed, jump to z_prep_c(), which will finish
* setting up the system for running C code. * setting up the system for running C code.
* *
*/ */
@ -163,7 +163,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
/* /*
* 'bl' jumps the furthest of the branch instructions that are * 'bl' jumps the furthest of the branch instructions that are
* supported on all platforms. So it is used when jumping to z_arm_prep_c * supported on all platforms. So it is used when jumping to z_prep_c
* (even though we do not intend to return). * (even though we do not intend to return).
*/ */
bl z_arm_prep_c bl z_prep_c

2
arch/arm/core/cortex_m/vector_table.h
View file

@ -50,7 +50,7 @@ GTEXT(z_arm_debug_monitor)
GTEXT(z_arm_pendsv) GTEXT(z_arm_pendsv)
GTEXT(z_arm_exc_spurious) GTEXT(z_arm_exc_spurious)
GTEXT(z_arm_prep_c) GTEXT(z_prep_c)
#if defined(CONFIG_GEN_ISR_TABLES) #if defined(CONFIG_GEN_ISR_TABLES)
GTEXT(_isr_wrapper) GTEXT(_isr_wrapper)
#endif /* CONFIG_GEN_ISR_TABLES */ #endif /* CONFIG_GEN_ISR_TABLES */