arch: arm: Move ARM code to AArch32 sub-directory

Before introducing the code for ARM64 (AArch64) we need to relocate the
current ARM code to a new AArch32 sub-directory. For now we can assume
that no code is shared between ARM and ARM64.

There are no functional changes. The code is moved to the new location
and the file paths are fixed to reflect this change.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

CODEOWNERS

@@ -16,9 +16,9 @@
 /.known-issues/                           @inakypg @nashif
 /arch/arc/                                @vonhust @ruuddw
 /arch/arm/                                @MaureenHelm @galak @ioannisg
-/arch/arm/core/cortex_m/cmse/             @ioannisg
-/arch/arm/include/cortex_m/cmse.h         @ioannisg
-/arch/arm/core/cortex_r/                  @MaureenHelm @galak @ioannisg @bbolen
+/arch/arm/core/aarch32/cortex_m/cmse/     @ioannisg
+/arch/arm/include/aarch32/cortex_m/cmse.h @ioannisg
+/arch/arm/core/aarch32/cortex_r/          @MaureenHelm @galak @ioannisg @bbolen @stephanosio
 /arch/common/                             @andrewboie @ioannisg @andyross
 /soc/arc/snps_*/                          @vonhust @ruuddw
 /soc/nios2/                               @nashif @wentongwu
@@ -245,8 +245,8 @@
 /include/arch/arc/                        @vonhust @ruuddw
 /include/arch/arc/arch.h                  @andrewboie
 /include/arch/arc/v2/irq.h                @andrewboie
-/include/arch/arm/                        @MaureenHelm @galak @ioannisg
-/include/arch/arm/irq.h                   @andrewboie
+/include/arch/arm/aarch32/                @MaureenHelm @galak @ioannisg
+/include/arch/arm/aarch32/irq.h           @andrewboie
 /include/arch/nios2/                      @andrewboie
 /include/arch/nios2/arch.h                @andrewboie
 /include/arch/posix/                      @aescolar

arch/arm/CMakeLists.txt

@@ -1,26 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-set(ARCH_FOR_cortex-m0        armv6s-m        )
-set(ARCH_FOR_cortex-m0plus    armv6s-m        )
-set(ARCH_FOR_cortex-m3        armv7-m         )
-set(ARCH_FOR_cortex-m4        armv7e-m        )
-set(ARCH_FOR_cortex-m23       armv8-m.base    )
-set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
-set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
-set(ARCH_FOR_cortex-r4        armv7-r         )
-
-if(ARCH_FOR_${GCC_M_CPU})
-    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
-endif()
-
-zephyr_compile_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-zephyr_ld_options(
-  -mabi=aapcs
-  ${ARCH_FLAG}
-  )
-
-add_subdirectory(core)
+include(aarch32.cmake)

arch/arm/Kconfig

@@ -6,7 +6,7 @@
 menu "ARM Options"
 	depends on ARM
 
-source "arch/arm/core/Kconfig"
+source "arch/arm/core/aarch32/Kconfig"
 
 config ARCH
 	default "arm"

arch/arm/aarch32.cmake

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(ARCH_FOR_cortex-m0        armv6s-m        )
+set(ARCH_FOR_cortex-m0plus    armv6s-m        )
+set(ARCH_FOR_cortex-m3        armv7-m         )
+set(ARCH_FOR_cortex-m4        armv7e-m        )
+set(ARCH_FOR_cortex-m23       armv8-m.base    )
+set(ARCH_FOR_cortex-m33       armv8-m.main+dsp)
+set(ARCH_FOR_cortex-m33+nodsp armv8-m.main    )
+set(ARCH_FOR_cortex-r4        armv7-r         )
+
+if(ARCH_FOR_${GCC_M_CPU})
+    set(ARCH_FLAG -march=${ARCH_FOR_${GCC_M_CPU}})
+endif()
+
+zephyr_compile_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+zephyr_ld_options(
+  -mabi=aapcs
+  ${ARCH_FLAG}
+  )
+
+add_subdirectory(core/aarch32)

arch/arm/core/aarch32/Kconfig

@@ -271,9 +271,9 @@ endchoice
 
 endmenu
 
-source "arch/arm/core/cortex_m/Kconfig"
-source "arch/arm/core/cortex_r/Kconfig"
+source "arch/arm/core/aarch32/cortex_m/Kconfig"
+source "arch/arm/core/aarch32/cortex_r/Kconfig"
 
-source "arch/arm/core/cortex_m/mpu/Kconfig"
+source "arch/arm/core/aarch32/cortex_m/mpu/Kconfig"
 
-source "arch/arm/core/cortex_m/tz/Kconfig"
+source "arch/arm/core/aarch32/cortex_m/tz/Kconfig"

arch/arm/core/aarch32/cortex_m/cmse/arm_core_cmse.c

@@ -5,7 +5,7 @@
  */
 
 #include <zephyr.h>
-#include <cortex_m/cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 
 int arm_cmse_mpu_region_get(u32_t addr)
 {

arch/arm/core/aarch32/cortex_m/irq_init.c

@@ -11,7 +11,7 @@
  */
 
 #include <arch/cpu.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/mpu/arm_mpu_v8_internal.h

@@ -8,7 +8,7 @@
 #ifndef ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
 #define ZEPHYR_ARCH_ARM_CORE_CORTEX_M_MPU_ARM_MPU_V8_INTERNAL_H_
 
-#include <cmse.h>
+#include <aarch32/cortex_m/cmse.h>
 #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL
 #include <logging/log.h>
 

arch/arm/core/aarch32/cortex_m/scb.c

@@ -17,7 +17,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #include <sys/util.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /**
  *

arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c

@@ -4,9 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/cmsis.h>
-#include <cortex_m/tz.h>
-#include <cortex_m/exc.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <aarch32/cortex_m/tz.h>
+#include <aarch32/cortex_m/exc.h>
 
 static void configure_nonsecure_vtor_offset(u32_t vtor_ns)
 {

arch/arm/core/aarch32/cortex_r/stacks.c

@@ -5,7 +5,7 @@
  */
 
 #include <kernel.h>
-#include <cortex_r/stack.h>
+#include <aarch32/cortex_r/stack.h>
 #include <string.h>
 
 K_THREAD_STACK_DEFINE(z_arm_fiq_stack,   CONFIG_ARMV7_FIQ_STACK_SIZE);

arch/arm/core/aarch32/irq_manage.c

@@ -17,7 +17,7 @@
 #include <kernel.h>
 #include <arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 #elif defined(CONFIG_CPU_CORTEX_R)
 #include <device.h>
 #include <irq_nextlevel.h>
@@ -171,7 +171,7 @@ void _arch_isr_direct_pm(void)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	/* Lock all interrupts. irq_lock() will on this CPU only disable those
 	 * lower than BASEPRI, which is not what we want. See comments in
-	 * arch/arm/core/isr_wrapper.S
+	 * arch/arm/core/aarch32/isr_wrapper.S
 	 */
 	__asm__ volatile("cpsid i" : : : "memory");
 #else

arch/arm/core/aarch32/prep_c.c

@@ -21,7 +21,7 @@
 #include <linker/linker-defs.h>
 
 #if defined(CONFIG_ARMV7_R)
-#include <cortex_r/stack.h>
+#include <aarch32/cortex_r/stack.h>
 #endif
 
 #if defined(__GNUC__)

arch/arm/include/aarch32/cortex_m/exc.h

@@ -22,8 +22,8 @@
 
 #else
 
-#include <arch/arm/cortex_m/cmsis.h>
-#include <arch/arm/exc.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/exc.h>
 #include <irq_offload.h>
 
 #ifdef __cplusplus

arch/arm/include/aarch32/cortex_m/stack.h

@@ -20,7 +20,7 @@
 
 #else
 
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 #ifdef __cplusplus
 extern "C" {

arch/arm/include/kernel_arch_data.h

@@ -30,11 +30,11 @@
 #define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
 
 #ifdef CONFIG_CPU_CORTEX_M
-#include <cortex_m/stack.h>
-#include <cortex_m/exc.h>
+#include <aarch32/cortex_m/stack.h>
+#include <aarch32/cortex_m/exc.h>
 #elif defined(CONFIG_CPU_CORTEX_R)
-#include <cortex_r/stack.h>
-#include <cortex_r/exc.h>
+#include <aarch32/cortex_r/stack.h>
+#include <aarch32/cortex_r/exc.h>
 #endif
 
 #ifndef _ASMLANGUAGE

arch/common/timing_info_bench.c

@@ -38,7 +38,7 @@ u64_t arch_timing_value_swap_temp;
 #define SUBTRACT_CLOCK_CYCLES(val)     (val)
 
 #elif CONFIG_ARM
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 #define TIMING_INFO_PRE_READ()
 #define TIMING_INFO_OS_GET_TIME()      (k_cycle_get_32())
 #define TIMING_INFO_GET_TIMER_VALUE()  (SysTick->VAL)

doc/guides/code-relocation.rst

@@ -99,4 +99,4 @@ A sample showcasing this feature is provided at
 This is an example of using the code relocation feature.
 
 This example will place .text, .data, .bss from 3 files to various parts in the SRAM
-using a custom linker file derived from ``include/arch/arm/cortex_m/scripts/linker.ld``
+using a custom linker file derived from ``include/arch/arm/aarch32/cortex_m/scripts/linker.ld``

doc/guides/porting/arch.rst

@@ -160,7 +160,7 @@ we strongly suggest that handlers at least print some debug information. The
 information helps figuring out what went wrong when hitting an exception that
 is a fault, like divide-by-zero or invalid memory access, or an interrupt that
 is not expected (:dfn:`spurious interrupt`). See the ARM implementation in
-:zephyr_file:`arch/arm/core/cortex_m/fault.c` for an example.
+:zephyr_file:`arch/arm/core/aarch32/cortex_m/fault.c` for an example.
 
 Thread Context Switching
 ************************
@@ -299,7 +299,7 @@ gracefully exits its entry point function.
 This means implementing an architecture-specific version of
 :cpp:func:`k_thread_abort`, and setting the Kconfig option
 :option:`CONFIG_ARCH_HAS_THREAD_ABORT` as needed for the architecture (e.g. see
-:zephyr_file:`arch/arm//core/cortex_m/Kconfig`).
+:zephyr_file:`arch/arm/core/aarch32/cortex_m/Kconfig`).
 
 Device Drivers
 **************

doc/reference/usermode/memory_domain.rst

@@ -440,7 +440,7 @@ dependent.
 
 The complete list of available partition attributes for a specific architecture
 is found in the architecture-specific include file
-``include/arch/<arch name>/arch.h``, (for example, ``include/arch/arm/arch.h``.)
+``include/arch/<arch name>/arch.h``, (for example, ``include/arch/arm/aarch32/arch.h``.)
 Some examples of partition attributes are:
 
 .. code-block:: c

drivers/timer/cortex_m_systick.c

@@ -6,7 +6,7 @@
 #include <drivers/timer/system_timer.h>
 #include <sys_clock.h>
 #include <spinlock.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 void z_arm_exc_exit(void);
 

include/arch/arm/aarch32/arch.h

@@ -22,23 +22,23 @@
 /* ARM GPRs are often designated by two different names */
 #define sys_define_gpr_with_alias(name1, name2) union { u32_t name1, name2; }
 
-#include <arch/arm/thread.h>
-#include <arch/arm/exc.h>
-#include <arch/arm/irq.h>
-#include <arch/arm/error.h>
-#include <arch/arm/misc.h>
+#include <arch/arm/aarch32/thread.h>
+#include <arch/arm/aarch32/exc.h>
+#include <arch/arm/aarch32/irq.h>
+#include <arch/arm/aarch32/error.h>
+#include <arch/arm/aarch32/misc.h>
 #include <arch/common/addr_types.h>
 #include <arch/common/ffs.h>
-#include <arch/arm/nmi.h>
-#include <arch/arm/asm_inline.h>
+#include <arch/arm/aarch32/nmi.h>
+#include <arch/arm/aarch32/asm_inline.h>
 
 #ifdef CONFIG_CPU_CORTEX_M
-#include <arch/arm/cortex_m/cpu.h>
-#include <arch/arm/cortex_m/memory_map.h>
+#include <arch/arm/aarch32/cortex_m/cpu.h>
+#include <arch/arm/aarch32/cortex_m/memory_map.h>
 #include <arch/common/sys_io.h>
 #elif defined(CONFIG_CPU_CORTEX_R)
-#include <arch/arm/cortex_r/cpu.h>
-#include <arch/arm/cortex_r/sys_io.h>
+#include <arch/arm/aarch32/cortex_r/cpu.h>
+#include <arch/arm/aarch32/cortex_r/sys_io.h>
 #endif
 
 #ifdef __cplusplus
@@ -245,10 +245,10 @@ extern "C" {
 /* Legacy case: retain containing extern "C" with C++ */
 #ifdef CONFIG_ARM_MPU
 #ifdef CONFIG_CPU_HAS_ARM_MPU
-#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+#include <arch/arm/aarch32/cortex_m/mpu/arm_mpu.h>
 #endif /* CONFIG_CPU_HAS_ARM_MPU */
 #ifdef CONFIG_CPU_HAS_NXP_MPU
-#include <arch/arm/cortex_m/mpu/nxp_mpu.h>
+#include <arch/arm/aarch32/cortex_m/mpu/nxp_mpu.h>
 #endif /* CONFIG_CPU_HAS_NXP_MPU */
 #endif /* CONFIG_ARM_MPU */
 

include/arch/arm/aarch32/asm_inline.h

@@ -15,7 +15,7 @@
  */
 
 #if defined(__GNUC__)
-#include <arch/arm/asm_inline_gcc.h>
+#include <arch/arm/aarch32/asm_inline_gcc.h>
 #else
 #include <arch/arm/asm_inline_other.h>
 #endif

include/arch/arm/aarch32/asm_inline_gcc.h

@@ -19,7 +19,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <zephyr/types.h>
-#include <arch/arm/exc.h>
+#include <arch/arm/aarch32/exc.h>
 #include <irq.h>
 
 #ifdef __cplusplus

include/arch/arm/aarch32/cortex_m/mpu/arm_mpu.h

@@ -10,10 +10,10 @@
 	defined(CONFIG_CPU_CORTEX_M3) || \
 	defined(CONFIG_CPU_CORTEX_M4) || \
 	defined(CONFIG_CPU_CORTEX_M7)
-#include <arch/arm/cortex_m/mpu/arm_mpu_v7m.h>
+#include <arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h>
 #elif defined(CONFIG_CPU_CORTEX_M23) || \
 	defined(CONFIG_CPU_CORTEX_M33)
-#include <arch/arm/cortex_m/mpu/arm_mpu_v8m.h>
+#include <arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h>
 #else
 #error "Unsupported ARM CPU"
 #endif

include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v7m.h

@@ -7,7 +7,7 @@
 
 #ifndef _ASMLANGUAGE
 
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /* Convenience macros to represent the ARMv7-M-specific
  * configuration for memory access permission and

include/arch/arm/aarch32/cortex_m/mpu/arm_mpu_v8m.h

@@ -7,7 +7,7 @@
 
 #ifndef _ASMLANGUAGE
 
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /* Convenience macros to represent the ARMv8-M-specific
  * configuration for memory access permission and

include/arch/arm/aarch32/error.h

@@ -14,8 +14,8 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_ERROR_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM_ERROR_H_
 
-#include <arch/arm/syscall.h>
-#include <arch/arm/exc.h>
+#include <arch/arm/aarch32/syscall.h>
+#include <arch/arm/aarch32/exc.h>
 #include <stdbool.h>
 
 #ifdef __cplusplus

include/arch/arm/aarch32/irq.h

@@ -100,7 +100,7 @@ extern void _arch_isr_direct_pm(void);
 #define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
 #define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
 
-/* arch/arm/core/exc_exit.S */
+/* arch/arm/core/aarch32/exc_exit.S */
 extern void z_arm_int_exit(void);
 
 #ifdef CONFIG_TRACING

include/arch/arm/aarch32/syscall.h

@@ -26,7 +26,7 @@
 
 #include <zephyr/types.h>
 #include <stdbool.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 #ifdef __cplusplus
 extern "C" {

include/arch/cpu.h

@@ -14,7 +14,7 @@
 #if defined(CONFIG_X86)
 #include <arch/x86/arch.h>
 #elif defined(CONFIG_ARM)
-#include <arch/arm/arch.h>
+#include <arch/arm/aarch32/arch.h>
 #elif defined(CONFIG_ARC)
 #include <arch/arc/arch.h>
 #elif defined(CONFIG_NIOS2)

include/arch/syscall.h

@@ -12,7 +12,7 @@
 #if defined(CONFIG_X86) && !defined(CONFIG_X86_64)
 #include <arch/x86/ia32/syscall.h>
 #elif defined(CONFIG_ARM)
-#include <arch/arm/syscall.h>
+#include <arch/arm/aarch32/syscall.h>
 #elif defined(CONFIG_ARC)
 #include <arch/arc/syscall.h>
 #endif

samples/application_development/code_relocation/linker_arm_sram2.ld

@@ -37,4 +37,4 @@ MEMORY
 #endif
     }
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

samples/application_development/code_relocation/src/main.c

@@ -17,7 +17,7 @@
  */
 
 #ifdef CONFIG_ARM_MPU
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 void disable_mpu_rasr_xn(void)
 {
 	u32_t index;

soc/arm/arm/beetle/linker.ld

@@ -6,4 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/arm/mps2/linker.ld

@@ -6,4 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/arm/musca_a/linker.ld

@@ -6,4 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/arm/musca_b1/linker.ld

@@ -6,4 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/atmel_sam/sam3x/linker.ld

@@ -6,4 +6,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <arch/arm/cortex_m/scripts/linker.ld>
+#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/atmel_sam/sam3x/soc.c

@@ -18,7 +18,7 @@
 #include <init.h>
 #include <soc.h>
 #include <arch/cpu.h>
-#include <arch/arm/cortex_m/cmsis.h>
+#include <arch/arm/aarch32/cortex_m/cmsis.h>
 
 /*
  * PLL clock = Main * (MULA + 1) / DIVA