arch: introduce DSP_SHARING and CPU_HAS_DSP configs

introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-11-16 09:16:42 -05:00 committed by Fabio Baltieri
parent b58a1f15af
commit aed0c451f8
12 changed files with 33 additions and 22 deletions

View file

@ -656,6 +656,11 @@ config CPU_HAS_FPU
This option is enabled when the CPU has hardware floating point
unit.
config CPU_HAS_DSP
bool
help
This option is enabled when the CPU has hardware DSP unit.
config CPU_HAS_FPU_DOUBLE_PRECISION
bool
select CPU_HAS_FPU
@ -820,6 +825,17 @@ config CODE_DATA_RELOCATION
the target regions should be specified in CMakeLists.txt using
zephyr_code_relocate().
menu "DSP Options"
config DSP_SHARING
bool "DSP register sharing"
depends on CPU_HAS_DSP
help
This option enables preservation of the hardware DSP registers
across context switches to allow multiple threads to perform concurrent
DSP operations.
endmenu
menu "Floating Point Options"
config FPU

View file

@ -3,13 +3,8 @@
# Copyright (c) 2022 Synopsys
# SPDX-License-Identifier: Apache-2.0
config ARC_HAS_DSP
bool
help
This option is enabled when the ARC CPU has hardware DSP unit.
menu "ARC DSP Options"
depends on ARC_HAS_DSP
depends on CPU_HAS_DSP
config ARC_DSP
bool "digital signal processing (DSP)"
@ -22,7 +17,7 @@ config ARC_DSP_TURNED_OFF
help
This option disables DSP block via resetting DSP_CRTL register.
config ARC_DSP_SHARING
config DSP_SHARING
bool "DSP register sharing"
depends on ARC_DSP && MULTITHREADING
select ARC_HAS_ACCL_REGS
@ -49,7 +44,7 @@ config ARC_XY_ENABLE
config ARC_AGU_SHARING
bool "ARC address generation unit register sharing"
depends on ARC_XY_ENABLE && MULTITHREADING
default y if ARC_DSP_SHARING
default y if DSP_SHARING
help
This option enables preservation of the hardware AGU registers
across context switches to allow multiple threads to perform concurrent

View file

@ -9,7 +9,7 @@
* @brief ARCv2 DSP and AGU structure member offset definition file
*
*/
#ifdef CONFIG_ARC_DSP_SHARING
#ifdef CONFIG_DSP_SHARING
GEN_OFFSET_SYM(_callee_saved_stack_t, dsp_ctrl);
GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_glo);
GEN_OFFSET_SYM(_callee_saved_stack_t, acc0_ghi);

View file

@ -10,7 +10,7 @@
*
*/
.macro _save_dsp_regs
#ifdef CONFIG_ARC_DSP_SHARING
#ifdef CONFIG_DSP_SHARING
ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
bbit0 r13, K_DSP_IDX, dsp_skip_save
lr r13, [_ARC_V2_DSP_CTRL]
@ -136,7 +136,7 @@ agu_skip_save :
.endm
.macro _load_dsp_regs
#ifdef CONFIG_ARC_DSP_SHARING
#ifdef CONFIG_DSP_SHARING
ld_s r13, [r2, ___thread_base_t_user_options_OFFSET]
bbit0 r13, K_DSP_IDX, dsp_skip_load
ld_s r13, [sp, ___callee_saved_stack_t_dsp_ctrl_OFFSET]

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@ -26,7 +26,7 @@
#include <kernel_arch_data.h>
#include <gen_offset.h>
#include <kernel_offsets.h>
#ifdef CONFIG_ARC_DSP_SHARING
#ifdef CONFIG_DSP_SHARING
#include "../dsp/dsp_offsets.c"
#endif

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@ -19,7 +19,7 @@
#include <zephyr/arch/arc/v2/mpu/arc_core_mpu.h>
#endif
#if defined(CONFIG_ARC_DSP) && defined(CONFIG_ARC_DSP_SHARING)
#if defined(CONFIG_ARC_DSP) && defined(CONFIG_DSP_SHARING)
#include <zephyr/arch/arc/v2/dsp/arc_dsp.h>
static struct k_spinlock lock;
#endif
@ -297,7 +297,7 @@ FUNC_NORETURN void z_arc_switch_to_main_no_multithreading(k_thread_entry_t main_
}
#endif /* !CONFIG_MULTITHREADING */
#if defined(CONFIG_ARC_DSP) && defined(CONFIG_ARC_DSP_SHARING)
#if defined(CONFIG_ARC_DSP) && defined(CONFIG_DSP_SHARING)
void arc_dsp_disable(struct k_thread *thread, unsigned int options)
{
/* Ensure a preemptive context switch does not occur */
@ -319,4 +319,4 @@ void arc_dsp_enable(struct k_thread *thread, unsigned int options)
k_spin_unlock(&lock, key);
}
#endif /* CONFIG_ARC_DSP && CONFIG_ARC_DSP_SHARING */
#endif /* CONFIG_ARC_DSP && CONFIG_DSP_SHARING */

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@ -160,7 +160,7 @@ struct _callee_saved_stack {
#endif
#endif
#ifdef CONFIG_ARC_DSP_SHARING
#ifdef CONFIG_DSP_SHARING
#ifdef CONFIG_ARC_DSP_BFLY_SHARING
uintptr_t dsp_fft_ctrl;
uintptr_t dsp_bfly0;

View file

@ -5,4 +5,4 @@ config SOC_ARC_HSDK4XD
bool "Synopsys ARC HSDK4XD SoC"
select ARC
select CPU_HAS_FPU
select ARC_HAS_DSP
select CPU_HAS_DSP

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@ -18,7 +18,7 @@ config SOC_NSIM_EM7D_V22
config SOC_NSIM_EM11D
bool "Synopsys ARC EM11D in nSIM"
select CPU_HAS_MPU
select ARC_HAS_DSP
select CPU_HAS_DSP
config SOC_NSIM_SEM
bool "Synopsys ARC SEM in nSIM"

View file

@ -1,5 +1,5 @@
CONFIG_ZTEST=y
CONFIG_ARC_DSP=y
CONFIG_ARC_DSP_SHARING=y
CONFIG_DSP_SHARING=y
CONFIG_MAIN_STACK_SIZE=1024
CONFIG_ARC_DSP_BFLY_SHARING=y

View file

@ -11,7 +11,7 @@
#error Rebuild with the ARC_DSP config option enabled
#endif
#ifndef CONFIG_ARC_DSP_SHARING
#ifndef CONFIG_DSP_SHARING
#error Rebuild with the ARC_DSP_SHARING config option enabled
#endif

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@ -1,8 +1,8 @@
tests:
arch.arc.dsp_sharing.test_load_store:
filter: CONFIG_ISA_ARCV2 and CONFIG_ARC_HAS_DSP
filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP
platform_allow: nsim_em11d
arch.arc.dsp_sharing.test_calculation:
filter: CONFIG_ISA_ARCV2 and CONFIG_ARC_HAS_DSP
filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP
toolchain_allow: arcmwdt
platform_allow: nsim_em11d