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drivers: spi: spi_dw: Remove clock gate support

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The SoC that utilized the clock support isn't supported in Zephyr
anymore and there are no users of this code.  Remove it for now as it
should get converted to utilize devicetree if needed in the future.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2021-02-25 05:36:06 -06:00 committed by Kumar Gala
parent 497b837aeb
commit b08c5d2bb8
3 changed files with 0 additions and 137 deletions
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58
drivers/spi/Kconfig.dw
View file

@ -48,20 +48,6 @@ config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_0_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_0_CLOCK_GATE
config SPI_DW_PORT_0_CLOCK_GATE_DRV_NAME
string
config SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_0_CLOCK_GATE
endif # SPI_0
if SPI_1
@ -70,20 +56,6 @@ config SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
bool "Single interrupt line for all interrupts"
default y
config SPI_DW_PORT_1_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_1_CLOCK_GATE
config SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME
string
config SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_1_CLOCK_GATE
endif # SPI_1
if SPI_2
@ -95,21 +67,6 @@ config SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_2_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_2_CLOCK_GATE
config SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME
string
default ""
config SPI_DW_PORT_2_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_2_CLOCK_GATE
endif # SPI_2
if SPI_3
@ -121,21 +78,6 @@ config SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
Only one line is used to trigger interrupts: RX, TX and ERROR
interrupt go all through that line, undifferentiated.
config SPI_DW_PORT_3_CLOCK_GATE
bool "Enable clock gating"
depends on CLOCK_CONTROL
if SPI_DW_PORT_3_CLOCK_GATE
config SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME
string
default ""
config SPI_DW_PORT_3_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
endif # SPI_DW_PORT_3_CLOCK_GATE
endif # SPI_3
endif # SPI_DW

20
drivers/spi/spi_dw.c
View file

@ -35,7 +35,6 @@ LOG_MODULE_REGISTER(spi_dw);
#include <init.h>
#include <sys/sys_io.h>
#include <drivers/clock_control.h>
#include <sys/util.h>
#ifdef CONFIG_IOAPIC
@ -521,9 +520,6 @@ int spi_dw_init(const struct device *dev)
const struct spi_dw_config *info = dev->config;
struct spi_dw_data *spi = dev->data;
clock_config(dev);
clock_on(dev);
info->config_func();
/* Masking interrupt and making sure controller is disabled */
@ -557,10 +553,6 @@ struct spi_dw_data spi_dw_data_port_0 = {
const struct spi_dw_config spi_dw_config_0 = {
.regs = DT_INST_REG_ADDR(0),
.clock_frequency = INST_0_SNPS_DESIGNWARE_SPI_CLOCK_FREQ,
#ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS),
#endif /* CONFIG_SPI_DW_PORT_0_CLOCK_GATE */
.config_func = spi_config_0_irq,
.op_modes = CONFIG_SPI_0_OP_MODES
};
@ -623,10 +615,6 @@ struct spi_dw_data spi_dw_data_port_1 = {
static const struct spi_dw_config spi_dw_config_1 = {
.regs = DT_INST_REG_ADDR(1),
.clock_frequency = INST_1_SNPS_DESIGNWARE_SPI_CLOCK_FREQ,
#ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS),
#endif /* CONFIG_SPI_DW_PORT_1_CLOCK_GATE */
.config_func = spi_config_1_irq,
.op_modes = CONFIG_SPI_1_OP_MODES
};
@ -689,10 +677,6 @@ struct spi_dw_data spi_dw_data_port_2 = {
static const struct spi_dw_config spi_dw_config_2 = {
.regs = DT_INST_REG_ADDR(2),
.clock_frequency = INST_2_SNPS_DESIGNWARE_SPI_CLOCK_FREQ,
#ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS),
#endif /* CONFIG_SPI_DW_PORT_2_CLOCK_GATE */
.config_func = spi_config_2_irq,
.op_modes = CONFIG_SPI_2_OP_MODES
};
@ -755,10 +739,6 @@ struct spi_dw_data spi_dw_data_port_3 = {
static const struct spi_dw_config spi_dw_config_3 = {
.regs = DT_INST_REG_ADDR(3),
.clock_frequency = INST_3_SNPS_DESIGNWARE_SPI_CLOCK_FREQ,
#ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE
.clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME,
.clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS),
#endif /* CONFIG_SPI_DW_PORT_3_CLOCK_GATE */
.config_func = spi_config_3_irq,
.op_modes = CONFIG_SPI_3_OP_MODES
};

59
drivers/spi/spi_dw.h
View file

@ -24,18 +24,11 @@ typedef void (*spi_dw_config_t)(void);
struct spi_dw_config {
uint32_t regs;
uint32_t clock_frequency;
#ifdef CONFIG_CLOCK_CONTROL
const char *clock_name;
void *clock_data;
#endif /* CONFIG_CLOCK_CONTROL */
spi_dw_config_t config_func;
uint8_t op_modes;
};
struct spi_dw_data {
#ifdef CONFIG_CLOCK_CONTROL
const struct device *clock;
#endif /* CONFIG_CLOCK_CONTROL */
struct spi_context ctx;
uint8_t dfs; /* dfs in bytes: 1,2 or 4 */
uint8_t fifo_diff; /* cannot be bigger than FIFO depth */
@ -227,58 +220,6 @@ DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
DEFINE_TEST_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
DEFINE_TEST_BIT_OP(sr_busy, DW_SPI_REG_SR, DW_SPI_SR_BUSY_BIT)
#ifdef CONFIG_CLOCK_CONTROL
static inline int clock_config(const struct device *dev)
{
const struct spi_dw_config *info = dev->config;
struct spi_dw_data *spi = dev->data;
if (!info->clock_name || strlen(info->clock_name) == 0) {
spi->clock = NULL;
return 0;
}
spi->clock = device_get_binding(info->clock_name);
if (!spi->clock) {
return -ENODEV;
}
return 0;
}
static inline void clock_on(const struct device *dev)
{
struct spi_dw_data *spi = dev->data;
if (spi->clock) {
const struct spi_dw_config *info = dev->config;
clock_control_on(spi->clock, info->clock_data);
}
extra_clock_on(dev);
}
static inline void clock_off(const struct device *dev)
{
struct spi_dw_data *spi = dev->data;
if (spi->clock) {
const struct spi_dw_config *info = dev->config;
clock_control_off(spi->clock, info->clock_data);
}
extra_clock_off(dev);
}
#else /* CONFIG_CLOCK_CONTROL */
#define clock_config(...)
#define clock_on(...)
#define clock_off(...)
#endif /* CONFIG_CLOCK_CONTROL */
#ifdef __cplusplus
}
#endif