arm: Removed support for CC2650
The SoC, driver, and board support for the CC2650 and CC2650 Sensortag aren't currently supported and we are removing them as such. If anyone is interesting in supporting this platform we can easily recovery it from git. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
e393a26270
commit
b1602c8e39
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@ -1,5 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources(pinmux.c)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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@ -1,7 +0,0 @@
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# TI CC2650 SensorTag configuration
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_CC2650_SENSORTAG
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endif # BOARD_CC2650_SENSORTAG
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@ -1,7 +0,0 @@
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# TI SimpleLink CC2650 SensorTag Board
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_CC2650_SENSORTAG
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bool "TI CC2650 SensorTag"
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depends on SOC_CC2650
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@ -1,13 +0,0 @@
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# TI CC2650 SensorTag board configuration
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_CC2650_SENSORTAG
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config BOARD
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default "cc2650_sensortag"
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config BOARD_DEPRECATED_RELEASE
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default "2.2.0"
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endif # BOARD_CC2650_SENSORTAG
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@ -1,58 +0,0 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Board-specific information for Texas Instruments'
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* SensorTag device.
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*/
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#ifndef _CC2650_SENSORTAG_BOARD_H_
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#define _CC2650_SENSORTAG_BOARD_H_
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/* Match a feature on the board to an I/O pin
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* (DIOx in local jargon)
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*/
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#define SENSORTAG_BUTTON2 0
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#define SENSORTAG_TMP_RDY 1
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#define SENSORTAG_AUDIO_D 2
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#define SENSORTAG_REED 3
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#define SENSORTAG_BUTTON1 4
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#define SENSORTAG_SDA 5
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#define SENSORTAG_SCL 6
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#define SENSORTAG_MPU_INT 7
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#define SENSORTAG_SDA_HP 8
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#define SENSORTAG_SCL_HP 9
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#define SENSORTAG_LED1 10
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#define SENSORTAG_DP7 11
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#define SENSORTAG_AUDIO_CLK SENSORTAG_DP7
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#define SENSORTAG_MPU_PWR 12
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#define SENSORTAG_MIC_PWR 13
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#define SENSORTAG_FLASH_CS 14
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#define SENSORTAG_LED2 15
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#define SENSORTAG_DP12 16
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#define SENSORTAG_AUDIO_FS SENSORTAG_DP12
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#define SENSORTAG_TDO SENSORTAG_DP12
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#define SENSORTAG_DP8 17
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#define SENSORTAG_SCLK SENSORTAG_DP8
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#define SENSORTAG_TDI SENSORTAG_DP8
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#define SENSORTAG_DP9 18
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#define SENSORTAG_MISO SENSORTAG_DP9
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#define SENSORTAG_DP10 19
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#define SENSORTAG_MOSI SENSORTAG_DP10
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#define SENSORTAG_DP11 20
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#define SENSORTAG_CSN SENSORTAG_DP11
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#define SENSORTAG_BUZZER 21
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#define SENSORTAG_DP6 22
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#define SENSORTAG_AUDIO_DO SENSORTAG_DP6
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#define SENSORTAG_DP2 23
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#define SENSORTAG_DP1 24
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#define SENSORTAG_DP0 25
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#define SENSORTAG_VDD 26
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#define SENSORTAG_DP3 27
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#define SENSORTAG_DP4 28
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#define SENSORTAG_UART_RX SENSORTAG_DP4
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#define SENSORTAG_DP5 29
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#define SENSORTAG_UART_TX SENSORTAG_DP5
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#define SENSORTAG_DP_D 30
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#endif /* _CC2650_SENSORTAG_BOARD_H_ */
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@ -1,39 +0,0 @@
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/* SPDX-License-Identifier: Apache-2.0 */
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/dts-v1/;
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#include "ti/cc2650.dtsi"
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/ {
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model = "TI CC2650 SensorTag";
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compatible = "ti,cc2650";
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aliases {
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gpio-a = &gpioa;
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pinmux-a = &pinmux_a;
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prcm0 = &prcm0;
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trng0 = &trng0;
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uart-0 = &uart0;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&gpioa {
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status = "okay";
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};
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&trng0 {
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status = "okay";
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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@ -1,9 +0,0 @@
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identifier: cc2650_sensortag
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name: SimpleLink multi-standard CC2650 SensorTag kit
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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ram: 20
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@ -1,37 +0,0 @@
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# SPDX-License-Identifier: Apache-2.0
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# General options
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
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CONFIG_BOOTLOADER_SRAM_SIZE=0
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CONFIG_XIP=y
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CONFIG_PRINTK=y
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# Platform-specific options
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CONFIG_ARM=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_BOARD_CC2650_SENSORTAG=y
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CONFIG_SOC_SERIES_CC2650=y
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CONFIG_SOC_CC2650=y
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# Pinmux driver
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CONFIG_PINMUX=y
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CONFIG_PINMUX_CC2650=y
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# GPIO driver
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CONFIG_GPIO=y
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CONFIG_GPIO_CC2650=y
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CONFIG_GPIO_CC2650_INIT_PRIO=0
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# UART driver
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CONFIG_SERIAL=y
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CONFIG_UART_STELLARIS=y
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CONFIG_UART_STELLARIS_PORT_0=y
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# Console driver
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Random number generator driver
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CONFIG_ENTROPY_GENERATOR=y
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Binary file not shown.
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Before Width: | Height: | Size: 31 KiB |
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@ -1,215 +0,0 @@
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.. _cc2650_sensortag:
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CC2650 SensorTag
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################
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Overview
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********
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The SimpleLink CC2650 SensorTag is a Texas Instruments board based
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on the CC2650 wireless MCU. It contains multiple sensors and provides
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Bluetooth and IEEE 802.15.4 connectivity.
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.. image:: img/cc2650_sensortag.jpg
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:width: 600px
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:height: 600px
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:align: center
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:alt: TI SensorTag v2
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Features
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========
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* CC2650 low-power wireless MCU: Bluetooth + IEEE 802.15.4 connectivity
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* Autonomous low-power sensor controller
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* Autonomous radio controller
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* Program, debug, and serial line through "DevPack" JTAG probe's USB port
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* Power from DevPack USB or batteries
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* 2 buttons and 2 LEDs for user interaction
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Hardware
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********
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The SensorTag board provides the following hardware:
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* CC2650 SoC in RGZ (7x7mm) 48 pins format package
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* Programmable Cortex-M3 CPU, clocked at 48MHz
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* Proprietary sensor controller
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* 12-bit ADC, 200ks/s
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* 2 comparators
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* SPI + I2C digital interfaces for sensors
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* Programmable with register-based interface
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* Cortex-M0 "RF Core" radio controller
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* 4KB of dedicated SRAM
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* Single transceiver, with modem and frequency synthesizer
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* Programmable with register-based interface
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* 128KB flash
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* 20KB SRAM
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* 8KB cache
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* SPI
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* I2C
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* I2S
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* UART
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* 31 GPIOs
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* 4 32-bit timers
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* True Random Number Generator
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* Real Time Clock
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* Watchdog timer
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* 32 channels DMA controller
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* 10 sensors: ambient light, digital microphone, magnetic sensor, humidity,
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pressure, accelerometer, gyroscope, magnetometer, object temperature and
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ambient temperature
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Supported features
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==================
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The following SensorTag features are currently supported:
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+-----------+------------+------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+====================================+
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| NVIC | on-chip | Nested Vector Interrupt Controller |
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+-----------+------------+------------------------------------+
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| UART | on-chip | serial port polling |
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+-----------+------------+------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+------------------------------------+
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Connections and IOs
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===================
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The SensorTag has one GPIO controller, along with a flexible pin
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multiplexer. In practice, the pins are routed as described in
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:zephyr_file:`boards/arm/cc2650_sensortag/board.h`; the most commonly used being:
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+----------------+---------------+----------------------+
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| Physical pin # | Digital I/O # | Signal |
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+================+===============+======================+
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| 5 | DIO_0 | BUTTON_2 (right) |
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+----------------+---------------+----------------------+
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| 9 | DIO_4 | BUTTON_1 (left) |
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+----------------+---------------+----------------------+
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| 10 | DIO_5 | SDA |
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+----------------+---------------+----------------------+
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| 11 | DIO_6 | SCL |
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+----------------+---------------+----------------------+
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| 16 | DIO_10 | LED_1 (red) |
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+----------------+---------------+----------------------+
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| 21 | DIO_15 | LED_2 (green) |
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+----------------+---------------+----------------------+
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| 27 | DIO_17 | SCLK |
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+----------------+---------------+----------------------+
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| 28 | DIO_18 | MISO |
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+----------------+---------------+----------------------+
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| 29 | DIO_19 | MOSI |
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+----------------+---------------+----------------------+
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| 31 | DIO_21 | BUZZER |
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+----------------+---------------+----------------------+
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| 41 | DIO_28 | UART_RX |
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+----------------+---------------+----------------------+
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| 42 | DIO_29 | UART_TX |
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+----------------+---------------+----------------------+
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System Clock
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============
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The CC2650 clocks its Cortex-M3 CPU through a 48MHz internal oscillator
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by default. 2 system clocks, a high-frequency one and a low-frequency one,
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are available to clock the CPU and the peripherals.
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Available clock sources for them are:
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* 48MHz internal oscillator
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* 24MHz internal oscillator
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* 32KHz internal oscillator
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* 32.768KHz external oscillator
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Programming and debugging
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*************************
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The ROM in the CC2650 contains a proprietary bootloader, executed
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before the program stored on flash. The bootloader looks at a special
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configuration area expected to be written at the end of flash, the
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CCFG ("Customer Configuration" area). A 32-bit word in this area,
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*IMAGE_VALID_CONF*, needs to be 0 in order for the bootloader to actually
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pass control to your program. You can find more information on the CCFG
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in the `CC2650 reference manual`_, section 9.1. The current CC2650 port
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for Zephyr already does this by default; if you wish to check or modify
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the CCFG content, see :zephyr_file:`soc/arm/ti_simplelink/cc2650/soc.c`.
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Building
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========
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You can build an application in the usual way. Here is an example for
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the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: cc2650_sensortag
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:goals: build flash
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Flashing
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========
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The CC2650 SensorTag can be flashed using a XDS110 JTAG device, the "DevPack",
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designed to plug on it. For now, flashing with it is not supported
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within Zephyr. However, you can use Uniflash, a TI proprietary tool, to do
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the job for now.
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.. note::
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Uniflash comes with some firmware for the "DevPeck" XDS110 JTAG probe.
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Different versions of Uniflash may have different firmware version.
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Currently, the most stable version is the 3.4. You should be able
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to grab it here:
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http://processors.wiki.ti.com/index.php/CCS_UniFlash_v3.4.1_Release_Notes
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To update the "DevPack", reach the installation path of Uniflash 3.4,
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then to the :file:`ccs_base/common/uscif/xds110/` subdirectory.
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Then follow the :file:`ReadMe.txt`'s instructions:
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.. code-block:: console
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$ ./xdsdfu -m
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$ ./xdsdfu -f firmware.bin -r
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The green LED of the "DevPack" should blink repeatedly during the
|
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operation, then light up again upon completion.
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Debugging
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=========
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Debugging can be done with OpenOCD 0.10, which is supported
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by the Zephyr SDK since v0.9.2. A basic configuration file for the
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SensorTag board would be:
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.. code-block:: console
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source [find interface/cmsis-dap.cfg]
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transport select jtag
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gdb_memory_map enable
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gdb_flash_program enable
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source [find target/cc26xx.cfg]
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adapter_khz 5000
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Copy this in a file named ``ti-sensortag.cfg``, located in the
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:file:`scripts/board` subdirectory of your local OpenOCD installation path.
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When you wish to launch the OpenOCD server, just type:
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.. code-block:: console
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$ openocd -f board/ti-sensortag.cfg
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References
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**********
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TI CC2650 datasheet:
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http://www.ti.com/lit/ds/symlink/cc2650.pdf
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CC2650 reference manual:
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http://www.ti.com/lit/ug/swcu117h/swcu117h.pdf
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Uniflash 3.4 release notes:
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http://processors.wiki.ti.com/index.php/CCS_UniFlash_v3.4.1_Release_Notes
|
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.. _CC2650 reference manual:
|
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http://www.ti.com/lit/ug/swcu117h/swcu117h.pdf
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@ -1,43 +0,0 @@
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/*
|
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* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
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* Board-specific pin multiplexing for Texas Instruments'
|
||||
* SensorTag device.
|
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*
|
||||
* For now, this only setups a default configuration
|
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* at initialization (not a real pinmux driver).
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*/
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#include <toolchain/gcc.h>
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#include <init.h>
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#include <drivers/pinmux.h>
|
||||
#include <soc.h>
|
||||
|
||||
#include "board.h"
|
||||
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||||
|
||||
static int sensortag_pinmux_init(struct device *dev)
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{
|
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dev = device_get_binding(CONFIG_PINMUX_NAME);
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/* DIO10 is LED 1 */
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pinmux_pin_set(dev, SENSORTAG_LED1, CC2650_IOC_GPIO);
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pinmux_pin_input_enable(dev, SENSORTAG_LED1, PINMUX_OUTPUT_ENABLED);
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||||
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||||
/* DIO15 is LED 2 */
|
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pinmux_pin_set(dev, SENSORTAG_LED2, CC2650_IOC_GPIO);
|
||||
pinmux_pin_input_enable(dev, SENSORTAG_LED2, PINMUX_OUTPUT_ENABLED);
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||||
|
||||
/* UART RX */
|
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pinmux_pin_set(dev, SENSORTAG_UART_RX, CC2650_IOC_MCU_UART0_RX);
|
||||
pinmux_pin_input_enable(dev, SENSORTAG_UART_RX, PINMUX_INPUT_ENABLED);
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||||
|
||||
/* UART TX */
|
||||
pinmux_pin_set(dev, SENSORTAG_UART_TX, CC2650_IOC_MCU_UART0_TX);
|
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pinmux_pin_input_enable(dev, SENSORTAG_UART_TX, PINMUX_OUTPUT_ENABLED);
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||||
|
||||
return 0;
|
||||
}
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||||
|
||||
SYS_INIT(sensortag_pinmux_init, PRE_KERNEL_1,
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||||
CONFIG_PINMUX_INIT_PRIORITY);
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|
|
@ -316,7 +316,6 @@ html_redirect_pages = [
|
|||
('boards/arm/arduino_zero/doc/arduino_zero', 'boards/arm/arduino_zero/doc/index'),
|
||||
('boards/arm/atsamd20_xpro/doc/atsamd20_xpro', 'boards/arm/atsamd20_xpro/doc/index'),
|
||||
('boards/arm/bbc_microbit/doc/board', 'boards/arm/bbc_microbit/doc/index'),
|
||||
('boards/arm/cc2650_sensortag/doc/cc2650_sensortag', 'boards/arm/cc2650_sensortag/doc/index'),
|
||||
('boards/arm/cc3220sf_launchxl/doc/cc3220sf_launchxl', 'boards/arm/cc3220sf_launchxl/doc/index'),
|
||||
('boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4', 'boards/arm/colibri_imx7d_m4/doc/index'),
|
||||
('boards/arm/disco_l475_iot1/doc/disco_l475_iot1', 'boards/arm/disco_l475_iot1/doc/index'),
|
||||
|
|
|
|||
|
|
@ -76,7 +76,7 @@ Architectures
|
|||
|
||||
* ARM:
|
||||
|
||||
* <TBD>
|
||||
* Removed support for CC2650
|
||||
|
||||
* POSIX:
|
||||
|
||||
|
|
|
|||
|
|
@ -3,7 +3,6 @@
|
|||
zephyr_library()
|
||||
|
||||
zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_GPIO_CC2650 gpio_cc2650.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX gpio_cc32xx.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB gpio_cmsdk_ahb.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_GPIO_DW gpio_dw.c)
|
||||
|
|
|
|||
|
|
@ -43,8 +43,6 @@ source "drivers/gpio/Kconfig.cc32xx"
|
|||
|
||||
source "drivers/gpio/Kconfig.sifive"
|
||||
|
||||
source "drivers/gpio/Kconfig.cc2650"
|
||||
|
||||
source "drivers/gpio/Kconfig.esp32"
|
||||
|
||||
source "drivers/gpio/Kconfig.gecko"
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# GPIO configuration options for the CC2650 SoC (Texas Instruments).
|
||||
|
||||
menuconfig GPIO_CC2650
|
||||
bool "TI CC2650 GPIO driver"
|
||||
depends on SOC_SERIES_CC2650
|
||||
help
|
||||
Enable the GPIO driver on boards equipped with TI CC2650.
|
||||
|
||||
if GPIO_CC2650
|
||||
|
||||
# A single block of GPIO exist.
|
||||
|
||||
config GPIO_CC2650_NAME
|
||||
string "GPIO driver name."
|
||||
default "GPIO_0"
|
||||
|
||||
config GPIO_CC2650_INIT_PRIO
|
||||
int "GPIO driver initialization priority."
|
||||
default 40
|
||||
|
||||
endif # GPIO_CC2650
|
||||
|
|
@ -1,336 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* GPIO driver for the CC2650 SOC from Texas Instruments.
|
||||
*/
|
||||
|
||||
#include <toolchain/gcc.h>
|
||||
#include <device.h>
|
||||
#include <drivers/gpio.h>
|
||||
#include <init.h>
|
||||
#include <soc.h>
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
#include "gpio_utils.h"
|
||||
|
||||
|
||||
struct gpio_cc2650_data {
|
||||
u32_t pin_callback_enables;
|
||||
sys_slist_t callbacks;
|
||||
};
|
||||
|
||||
/* Pre-declarations */
|
||||
static int gpio_cc2650_init(struct device *dev);
|
||||
static int gpio_cc2650_config(struct device *port, int access_op,
|
||||
u32_t pin, int flags);
|
||||
static int gpio_cc2650_write(struct device *port, int access_op,
|
||||
u32_t pin, u32_t value);
|
||||
|
||||
static int gpio_cc2650_read(struct device *port, int access_op,
|
||||
u32_t pin, u32_t *value);
|
||||
static int gpio_cc2650_manage_callback(struct device *port,
|
||||
struct gpio_callback *callback,
|
||||
bool set);
|
||||
static int gpio_cc2650_enable_callback(struct device *port,
|
||||
int access_op,
|
||||
u32_t pin);
|
||||
static int gpio_cc2650_disable_callback(struct device *port,
|
||||
int access_op,
|
||||
u32_t pin);
|
||||
static u32_t gpio_cc2650_get_pending_int(struct device *dev);
|
||||
|
||||
/* GPIO registers */
|
||||
static const u32_t doutset31_0 =
|
||||
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
|
||||
CC2650_GPIO_DOUTSET31_0);
|
||||
static const u32_t doutclr31_0 =
|
||||
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
|
||||
CC2650_GPIO_DOUTCLR31_0);
|
||||
static const u32_t din31_0 =
|
||||
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
|
||||
CC2650_GPIO_DIN31_0);
|
||||
static const u32_t doe31_0 =
|
||||
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
|
||||
CC2650_GPIO_DOE31_0);
|
||||
static const u32_t evflags31_0 =
|
||||
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
|
||||
CC2650_GPIO_EVFLAGS31_0);
|
||||
|
||||
static struct gpio_cc2650_data gpio_cc2650_data = {
|
||||
.pin_callback_enables = 0
|
||||
};
|
||||
|
||||
static const struct gpio_driver_api gpio_cc2650_funcs = {
|
||||
.config = gpio_cc2650_config,
|
||||
.write = gpio_cc2650_write,
|
||||
.read = gpio_cc2650_read,
|
||||
.manage_callback = gpio_cc2650_manage_callback,
|
||||
.enable_callback = gpio_cc2650_enable_callback,
|
||||
.disable_callback = gpio_cc2650_disable_callback,
|
||||
.get_pending_int = gpio_cc2650_get_pending_int
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(gpio_cc2650_0, CONFIG_GPIO_CC2650_NAME,
|
||||
gpio_cc2650_init, &gpio_cc2650_data, NULL,
|
||||
PRE_KERNEL_1, CONFIG_GPIO_CC2650_INIT_PRIO,
|
||||
&gpio_cc2650_funcs);
|
||||
static void disconnect(const int pin, u32_t *gpiodoe31_0,
|
||||
u32_t *iocfg)
|
||||
{
|
||||
*gpiodoe31_0 &= ~BIT(pin);
|
||||
|
||||
*iocfg &= ~(CC2650_IOC_IOCFGX_PULL_CTL_MASK |
|
||||
CC2650_IOC_IOCFGX_IE_MASK);
|
||||
*iocfg |= CC2650_IOC_INPUT_DISABLED |
|
||||
CC2650_IOC_NO_PULL;
|
||||
}
|
||||
|
||||
/* Configure a single pin.
|
||||
* If any asked option is not implementable, rollback entirely to
|
||||
* previous configuration.
|
||||
*
|
||||
* Note: For pin drive strength, the CC2650 devices only support
|
||||
* symmetric sink/source capabilities.
|
||||
* Thus, you may ONLY determine the common drive strength with
|
||||
* GPIO *low output state* flags. Flags for *high output state*
|
||||
* will be ignored.
|
||||
*/
|
||||
static int gpio_cc2650_config_pin(int pin, int flags)
|
||||
{
|
||||
const u32_t iocfg = REG_ADDR(DT_TI_CC2650_PINMUX_40081000_BASE_ADDRESS,
|
||||
CC2650_IOC_IOCFG0 + 0x4 * pin);
|
||||
u32_t iocfg_config = sys_read32(iocfg);
|
||||
u32_t gpio_doe31_0_config = sys_read32(doe31_0);
|
||||
|
||||
/* Reset all configurable fields to 0 */
|
||||
iocfg_config &= ~(CC2650_IOC_IOCFGX_IOSTR_MASK |
|
||||
CC2650_IOC_IOCFGX_PULL_CTL_MASK |
|
||||
CC2650_IOC_IOCFGX_EDGE_DET_MASK |
|
||||
CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK |
|
||||
CC2650_IOC_IOCFGX_IOMODE_MASK |
|
||||
CC2650_IOC_IOCFGX_IE_MASK |
|
||||
CC2650_IOC_IOCFGX_HYST_EN_MASK);
|
||||
|
||||
if (flags & GPIO_DIR_OUT) {
|
||||
gpio_doe31_0_config |= BIT(pin);
|
||||
iocfg_config |= CC2650_IOC_INPUT_DISABLED;
|
||||
} else {
|
||||
gpio_doe31_0_config &= ~BIT(pin);
|
||||
iocfg_config |= CC2650_IOC_INPUT_ENABLED;
|
||||
}
|
||||
|
||||
if (flags & GPIO_INT) {
|
||||
if (!(flags & GPIO_INT_EDGE) &&
|
||||
!(flags & GPIO_INT_DOUBLE_EDGE)) {
|
||||
/* Can't do level-based interrupt */
|
||||
/* Don't commit changes */
|
||||
return -ENOTSUP;
|
||||
}
|
||||
|
||||
iocfg_config |= BIT(CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS);
|
||||
|
||||
if (flags & GPIO_INT_EDGE) {
|
||||
if (flags & GPIO_INT_ACTIVE_HIGH) {
|
||||
iocfg_config |= CC2650_IOC_POS_EDGE_DET;
|
||||
} else {
|
||||
iocfg_config |= CC2650_IOC_NEG_EDGE_DET;
|
||||
}
|
||||
} else if (flags & GPIO_INT_DOUBLE_EDGE) {
|
||||
iocfg_config |= CC2650_IOC_NEG_AND_POS_EDGE_DET;
|
||||
}
|
||||
|
||||
if (flags & GPIO_INT_DEBOUNCE) {
|
||||
iocfg_config |= CC2650_IOC_HYSTERESIS_ENABLED;
|
||||
} else {
|
||||
iocfg_config |= CC2650_IOC_HYSTERESIS_DISABLED;
|
||||
}
|
||||
}
|
||||
|
||||
if (flags & GPIO_POL_INV) {
|
||||
iocfg_config |= CC2650_IOC_INVERTED_IO;
|
||||
} else {
|
||||
iocfg_config |= CC2650_IOC_NORMAL_IO;
|
||||
}
|
||||
|
||||
if (flags & GPIO_PUD_PULL_UP) {
|
||||
iocfg_config |= CC2650_IOC_PULL_UP;
|
||||
} else if (flags & GPIO_PUD_PULL_DOWN) {
|
||||
iocfg_config |= CC2650_IOC_PULL_DOWN;
|
||||
} else {
|
||||
iocfg_config |= CC2650_IOC_NO_PULL;
|
||||
}
|
||||
|
||||
/* Remember, we only look at GPIO_DS_*_LOW ! */
|
||||
if (flags & GPIO_DS_DISCONNECT_LOW) {
|
||||
disconnect(pin, &gpio_doe31_0_config, &iocfg_config);
|
||||
}
|
||||
if (flags & GPIO_DS_ALT_LOW) {
|
||||
iocfg_config |= CC2650_IOC_MAX_DRIVE_STRENGTH;
|
||||
} else {
|
||||
iocfg_config |= CC2650_IOC_MIN_DRIVE_STRENGTH;
|
||||
}
|
||||
|
||||
/* Commit changes */
|
||||
sys_write32(iocfg_config, iocfg);
|
||||
sys_write32(gpio_doe31_0_config, doe31_0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void gpio_cc2650_write_pin(int pin, u32_t value)
|
||||
{
|
||||
value ? sys_write32(BIT(pin), doutset31_0) :
|
||||
sys_write32(BIT(pin), doutclr31_0);
|
||||
}
|
||||
|
||||
static inline void gpio_cc2650_read_pin(int pin, u32_t *value)
|
||||
{
|
||||
*value = sys_read32(din31_0) & BIT(pin);
|
||||
}
|
||||
|
||||
static void gpio_cc2650_isr(void *arg)
|
||||
{
|
||||
struct device *dev = (struct device *)arg;
|
||||
struct gpio_cc2650_data *data = dev->driver_data;
|
||||
|
||||
const u32_t events = sys_read32(evflags31_0);
|
||||
const u32_t call_mask = events & data->pin_callback_enables;
|
||||
|
||||
/* Clear GPIO trigger events */
|
||||
u32_t evflags = sys_read32(evflags31_0);
|
||||
|
||||
sys_write32(evflags | call_mask, evflags31_0);
|
||||
|
||||
gpio_fire_callbacks(&data->callbacks, dev, call_mask);
|
||||
}
|
||||
|
||||
|
||||
static int gpio_cc2650_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
/* ISR setup */
|
||||
IRQ_CONNECT(DT_TI_CC2650_GPIO_40022000_IRQ_0,
|
||||
DT_TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY,
|
||||
gpio_cc2650_isr, DEVICE_GET(gpio_cc2650_0),
|
||||
0);
|
||||
irq_enable(DT_TI_CC2650_GPIO_40022000_IRQ_0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_cc2650_config(struct device *port, int access_op,
|
||||
u32_t pin, int flags)
|
||||
{
|
||||
ARG_UNUSED(port);
|
||||
|
||||
if (access_op == GPIO_ACCESS_BY_PIN) {
|
||||
return gpio_cc2650_config_pin(pin, flags);
|
||||
}
|
||||
|
||||
const u32_t nb_pins = 32U;
|
||||
|
||||
for (u8_t i = 0; i < nb_pins; ++i) {
|
||||
if (pin & 0x1 &&
|
||||
gpio_cc2650_config_pin(i, flags) == -ENOTSUP) {
|
||||
/* The flags being treated the same for
|
||||
* every pin, if we get here then it's
|
||||
* necessarily the first pin on which we act.
|
||||
*
|
||||
* We expect gpio_cc2650_config_pin() to
|
||||
* NOT commit its changes if any problem
|
||||
* arises, thus we do nothing special here
|
||||
* to implement rollback to previous
|
||||
* configuration.
|
||||
*/
|
||||
return -ENOTSUP;
|
||||
}
|
||||
pin >>= 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_cc2650_write(struct device *port, int access_op,
|
||||
u32_t pin, u32_t value)
|
||||
{
|
||||
ARG_UNUSED(port);
|
||||
|
||||
if (access_op == GPIO_ACCESS_BY_PIN) {
|
||||
gpio_cc2650_write_pin(pin, value);
|
||||
} else {
|
||||
const u32_t nb_pins = 32U;
|
||||
|
||||
for (u32_t i = 0; i < nb_pins; ++i) {
|
||||
if (pin & 0x1) {
|
||||
gpio_cc2650_write_pin(i, value);
|
||||
}
|
||||
pin >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_cc2650_read(struct device *port, int access_op,
|
||||
u32_t pin, u32_t *value)
|
||||
{
|
||||
ARG_UNUSED(port);
|
||||
|
||||
if (access_op == GPIO_ACCESS_BY_PIN) {
|
||||
gpio_cc2650_read_pin(pin, value);
|
||||
*value >>= pin;
|
||||
} else {
|
||||
const u32_t nb_pins = 32U;
|
||||
|
||||
for (u32_t i = 0; i < nb_pins; ++i) {
|
||||
if (pin & 0x1) {
|
||||
gpio_cc2650_read_pin(i, value);
|
||||
}
|
||||
pin >>= 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_cc2650_manage_callback(struct device *port,
|
||||
struct gpio_callback *callback,
|
||||
bool set)
|
||||
{
|
||||
struct gpio_cc2650_data *data = port->driver_data;
|
||||
|
||||
return gpio_manage_callback(&data->callbacks, callback, set);
|
||||
}
|
||||
|
||||
static int gpio_cc2650_enable_callback(struct device *port,
|
||||
int access_op,
|
||||
u32_t pin)
|
||||
{
|
||||
struct gpio_cc2650_data *data = port->driver_data;
|
||||
|
||||
if (access_op == GPIO_ACCESS_BY_PIN) {
|
||||
data->pin_callback_enables |= BIT(pin);
|
||||
} else {
|
||||
data->pin_callback_enables |= pin;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int gpio_cc2650_disable_callback(struct device *port,
|
||||
int access_op,
|
||||
u32_t pin)
|
||||
{
|
||||
struct gpio_cc2650_data *data = port->driver_data;
|
||||
|
||||
if (access_op == GPIO_ACCESS_BY_PIN) {
|
||||
data->pin_callback_enables &= ~BIT(pin);
|
||||
} else {
|
||||
data->pin_callback_enables &= ~pin;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32_t gpio_cc2650_get_pending_int(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
return sys_read32(evflags31_0);
|
||||
}
|
||||
|
|
@ -2,7 +2,6 @@
|
|||
|
||||
# Board initialization
|
||||
zephyr_sources_ifdef(CONFIG_PINMUX_CC13XX_CC26XX pinmux_cc13xx_cc26xx.c)
|
||||
zephyr_sources_ifdef(CONFIG_PINMUX_CC2650 pinmux_cc2650.c)
|
||||
zephyr_sources_ifdef(CONFIG_PINMUX_ESP32 pinmux_esp32.c)
|
||||
zephyr_sources_ifdef(CONFIG_PINMUX_SIFIVE pinmux_sifive.c)
|
||||
zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
|
||||
|
|
|
|||
|
|
@ -42,8 +42,6 @@ source "drivers/pinmux/Kconfig.sifive"
|
|||
|
||||
source "drivers/pinmux/Kconfig.cc13xx_cc26xx"
|
||||
|
||||
source "drivers/pinmux/Kconfig.cc2650"
|
||||
|
||||
source "drivers/pinmux/Kconfig.esp32"
|
||||
|
||||
source "drivers/pinmux/Kconfig.sam0"
|
||||
|
|
|
|||
|
|
@ -1,16 +0,0 @@
|
|||
# TI CC2650 SoC pinmux driver.
|
||||
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config PINMUX_CC2650
|
||||
bool "Pinmux driver for CC2650 SoC"
|
||||
depends on SOC_SERIES_CC2650
|
||||
depends on GPIO
|
||||
depends on GPIO_CC2650
|
||||
help
|
||||
Enable pin multiplexer for CC2650 SoC.
|
||||
|
||||
For hardware reasons, the pinmux depends on the GPIO module
|
||||
being activated; it must initialize *before* the pinmux does.
|
||||
Please take care that the pinmux init priority value is *lower*
|
||||
that the GPIO driver init priority.
|
||||
|
|
@ -1,155 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Driver for the I/O controller (pinmux) for
|
||||
* Texas Instrument's CC2650 SoC.
|
||||
*
|
||||
* For these SoCs, available pin functions are as follows:
|
||||
*
|
||||
* 0x00 - GPIO
|
||||
* 0x07 - AON 32 Khz clock
|
||||
* 0x08 - AUX IO
|
||||
* 0x09 - SSI0 RX
|
||||
* 0x0A - SSI0 TX
|
||||
* 0x0B - SSI0 FSS
|
||||
* 0x0C - SSI0 CLK
|
||||
* 0x0D - I2C SDA
|
||||
* 0x0E - I2C SCL
|
||||
* 0x0F - UART0 RX
|
||||
* 0x10 - UART0 TX
|
||||
* 0x11 - UART0 CTS
|
||||
* 0x12 - UART0 RTS
|
||||
* 0x17 - Port event 0
|
||||
* 0x18 - Port event 1
|
||||
* 0x19 - Port event 2
|
||||
* 0x1A - Port event 3
|
||||
* 0x1B - Port event 4
|
||||
* 0x1C - Port event 5
|
||||
* 0x1D - Port event 6
|
||||
* 0x1E - Port event 7
|
||||
* 0x20 - CPU SWV
|
||||
* 0x21 - SSI1 RX
|
||||
* 0x22 - SSI1 TX
|
||||
* 0x23 - SSI1 FSS
|
||||
* 0x24 - SSI1 CLK
|
||||
* 0x25 - I2S data 0
|
||||
* 0x26 - I2S data 1
|
||||
* 0x27 - I2S WCLK
|
||||
* 0x28 - I2S BCLK
|
||||
* 0x29 - I2S MCLK
|
||||
* 0x2E - RF Core Trace
|
||||
* 0x2F - RF Core data out 0
|
||||
* 0x30 - RF Core data out 1
|
||||
* 0x31 - RF Core data out 2
|
||||
* 0x32 - RF Core data out 3
|
||||
* 0x33 - RF Core data in 0
|
||||
* 0x34 - RF Core data in 1
|
||||
* 0x35 - RF Core SMI data link out
|
||||
* 0x36 - RF Core SMI data link in
|
||||
* 0x37 - RF Core SMI command link out
|
||||
* 0x38 - RF Core SMI command link in
|
||||
*/
|
||||
|
||||
#include <sys/__assert.h>
|
||||
#include <sys/util.h>
|
||||
#include <toolchain.h>
|
||||
#include <device.h>
|
||||
#include <drivers/pinmux.h>
|
||||
#include <soc.h>
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
|
||||
#define IOCFG_REG(Func) \
|
||||
REG_ADDR(DT_TI_CC2650_PINMUX_40081000_BASE_ADDRESS, \
|
||||
CC2650_IOC_IOCFG0 + 0x4 * Func)
|
||||
|
||||
static int pinmux_cc2650_init(struct device *dev)
|
||||
{
|
||||
/* Do nothing */
|
||||
ARG_UNUSED(dev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinmux_cc2650_set(struct device *dev, u32_t pin,
|
||||
u32_t func)
|
||||
{
|
||||
const u32_t iocfg = IOCFG_REG(pin);
|
||||
u32_t conf = sys_read32(iocfg);
|
||||
|
||||
conf &= ~CC2650_IOC_IOCFGX_PORT_ID_MASK;
|
||||
conf |= func & CC2650_IOC_IOCFGX_PORT_ID_MASK;
|
||||
sys_write32(conf, iocfg);
|
||||
|
||||
return 0;
|
||||
};
|
||||
|
||||
static int pinmux_cc2650_get(struct device *dev, u32_t pin,
|
||||
u32_t *func)
|
||||
{
|
||||
const u32_t iocfg = IOCFG_REG(pin);
|
||||
u32_t conf = sys_read32(iocfg);
|
||||
|
||||
*func = conf & CC2650_IOC_IOCFGX_PORT_ID_MASK;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinmux_cc2650_pullup(struct device *dev, u32_t pin,
|
||||
u8_t func)
|
||||
{
|
||||
__ASSERT((func == PINMUX_PULLUP_ENABLE) |
|
||||
(func == PINMUX_PULLUP_DISABLE),
|
||||
"Pullup mode is invalid");
|
||||
|
||||
const u32_t iocfg = IOCFG_REG(pin);
|
||||
u32_t conf = sys_read32(iocfg);
|
||||
|
||||
conf &= ~CC2650_IOC_IOCFGX_PULL_CTL_MASK;
|
||||
if (func == PINMUX_PULLUP_ENABLE) {
|
||||
conf |= CC2650_IOC_PULL_UP;
|
||||
} else {
|
||||
conf |= CC2650_IOC_NO_PULL;
|
||||
}
|
||||
sys_write32(conf, iocfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pinmux_cc2650_input(struct device *dev, u32_t pin,
|
||||
u8_t func)
|
||||
{
|
||||
__ASSERT((func == PINMUX_INPUT_ENABLED) |
|
||||
(func == PINMUX_OUTPUT_ENABLED),
|
||||
"I/O mode is invalid");
|
||||
|
||||
const u32_t iocfg = IOCFG_REG(pin);
|
||||
const u32_t gpio_doe = DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS +
|
||||
CC2650_GPIO_DOE31_0;
|
||||
u32_t iocfg_conf = sys_read32(iocfg);
|
||||
u32_t gpio_doe_conf = sys_read32(gpio_doe);
|
||||
|
||||
iocfg_conf &= ~CC2650_IOC_IOCFGX_IE_MASK;
|
||||
if (func == PINMUX_INPUT_ENABLED) {
|
||||
iocfg_conf |= CC2650_IOC_INPUT_ENABLED;
|
||||
gpio_doe_conf &= ~BIT(pin);
|
||||
} else {
|
||||
iocfg_conf |= CC2650_IOC_INPUT_DISABLED;
|
||||
gpio_doe_conf |= BIT(pin);
|
||||
}
|
||||
sys_write32(iocfg_conf, iocfg);
|
||||
sys_write32(gpio_doe_conf, gpio_doe);
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
const struct pinmux_driver_api pinmux_cc2650_funcs = {
|
||||
.set = pinmux_cc2650_set,
|
||||
.get = pinmux_cc2650_get,
|
||||
.pullup = pinmux_cc2650_pullup,
|
||||
.input = pinmux_cc2650_input
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pinmux_cc2650_0, CONFIG_PINMUX_NAME,
|
||||
pinmux_cc2650_init, NULL, NULL,
|
||||
PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY,
|
||||
&pinmux_cc2650_funcs);
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
menuconfig UART_STELLARIS
|
||||
bool "Stellaris serial driver"
|
||||
depends on SOC_TI_LM3S6965 || SOC_CC2650
|
||||
depends on SOC_TI_LM3S6965
|
||||
select SERIAL_HAS_DRIVER
|
||||
select SERIAL_SUPPORT_INTERRUPT
|
||||
help
|
||||
|
|
|
|||
|
|
@ -1,78 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Device Tree include file for CC2650 SoC from Texas Instruments.
|
||||
*/
|
||||
|
||||
#include "armv7-m.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m3";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20000000 0x5000>;
|
||||
};
|
||||
|
||||
flash0: serial-flash@0 {
|
||||
compatible = "serial-flash";
|
||||
reg = <0x0 0x20000>;
|
||||
};
|
||||
|
||||
sysclk: system-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <48000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
gpioa: gpio@40022000 {
|
||||
compatible = "ti,cc2650-gpio";
|
||||
reg = <0x40022000 0xE4>;
|
||||
interrupts = <0 0>;
|
||||
status = "disabled";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
};
|
||||
|
||||
pinmux_a: pinmux@40081000 {
|
||||
compatible = "ti,cc2650-pinmux";
|
||||
reg = <0x40081000 0x80>;
|
||||
};
|
||||
|
||||
prcm0: prcm@40082000 {
|
||||
compatible = "ti,cc2650-prcm";
|
||||
reg = <0x40082000 0x228>;
|
||||
};
|
||||
|
||||
trng0: trng@40028000 {
|
||||
compatible = "ti,cc2650-trng";
|
||||
reg = <0x40028000 0x1FFC>;
|
||||
interrupts = <33 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: uart@40001000 {
|
||||
compatible = "ti,stellaris-uart";
|
||||
reg = <0x40001000 0x4C>;
|
||||
clocks = <&sysclk>;
|
||||
interrupts = <5 0>, <6 0>;
|
||||
status = "disabled";
|
||||
label = "UART_0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
};
|
||||
|
|
@ -1,11 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: TI CC2650 PRCM (Power, Reset, and Clock control Module)
|
||||
|
||||
compatible: "ti,cc2650-prcm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
description: TI CC2650 GPIO node
|
||||
|
||||
compatible: "ti,cc2650-gpio"
|
||||
|
||||
include: [gpio-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
description: TI CC2650 pinmux node
|
||||
|
||||
compatible: "ti,cc2650-pinmux"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinmux-cells:
|
||||
- pin
|
||||
- function
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(soc.c)
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
# TI SimpleLink CC2650
|
||||
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_CC2650
|
||||
|
||||
config SOC_SERIES
|
||||
default "cc2650"
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 48000000
|
||||
|
||||
config NUM_IRQS
|
||||
default 34
|
||||
|
||||
endif # SOC_SERIES_CC2650
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
# TI SimpleLink CC2650
|
||||
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_CC2650
|
||||
bool "TI SimpleLink Family CC2650"
|
||||
select CPU_CORTEX_M3
|
||||
select SOC_FAMILY_TISIMPLELINK
|
||||
help
|
||||
Enable support for TI SimpleLink CC2650.
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
# Texas Instruments CC2650
|
||||
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
choice
|
||||
prompt "TI SimpleLink MCU Selection"
|
||||
depends on SOC_SERIES_CC2650
|
||||
|
||||
config SOC_CC2650
|
||||
bool "CC2650"
|
||||
|
||||
endchoice
|
||||
|
||||
if SOC_SERIES_CC2650
|
||||
|
||||
config TI_CCFG_PRESENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC
|
||||
default "cc2650"
|
||||
|
||||
config SOC_DEPRECATED_RELEASE
|
||||
default "2.2.0"
|
||||
|
||||
endif # SOC_SERIES_CC2650
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: Apache-2.0 */
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
|
||||
|
||||
#define DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS DT_TI_STELLARIS_UART_40001000_BASE_ADDRESS
|
||||
#define DT_TI_STELLARIS_UART_4000C000_CURRENT_SPEED DT_TI_STELLARIS_UART_40001000_CURRENT_SPEED
|
||||
#define DT_TI_STELLARIS_UART_4000C000_CLOCKS_CLOCK_FREQUENCY DT_TI_STELLARIS_UART_40001000_CLOCKS_CLOCK_FREQUENCY
|
||||
#define DT_TI_STELLARIS_UART_4000C000_IRQ_0 DT_TI_STELLARIS_UART_40001000_IRQ_0
|
||||
#define DT_TI_STELLARIS_UART_4000C000_IRQ_0_PRIORITY DT_TI_STELLARIS_UART_40001000_IRQ_0_PRIORITY
|
||||
#define DT_TI_STELLARIS_UART_4000C000_LABEL DT_TI_STELLARIS_UART_40001000_LABEL
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* linker.ld - Linker command/script file
|
||||
*/
|
||||
|
||||
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>
|
||||
|
|
@ -1,749 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* CCFG (User configuration area) interface registers and bit offsets
|
||||
* for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_CCFG_H_
|
||||
#define _CC2650_CCFG_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_CCFG_Registers {
|
||||
CC2650_CCFG_EXT_LF_CLK = 0xFA8,
|
||||
CC2650_CCFG_MODE_CONF_1 = 0xFAC,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS = 0xFB0,
|
||||
CC2650_CCFG_MODE_CONF = 0xFB4,
|
||||
CC2650_CCFG_VOLT_LOAD_0 = 0xFB8,
|
||||
CC2650_CCFG_VOLT_LOAD_1 = 0xFBC,
|
||||
CC2650_CCFG_RTC_OFFSET = 0xFC0,
|
||||
CC2650_CCFG_FREQ_OFFSET = 0xFC4,
|
||||
CC2650_CCFG_IEEE_MAC_0 = 0xFC8,
|
||||
CC2650_CCFG_IEEE_MAC_1 = 0xFCC,
|
||||
CC2650_CCFG_IEEE_BLE_0 = 0xFD0,
|
||||
CC2650_CCFG_IEEE_BLE_1 = 0xFD4,
|
||||
CC2650_CCFG_BL_CONFIG = 0xFD8,
|
||||
CC2650_CCFG_ERASE_CONF = 0xFDC,
|
||||
CC2650_CCFG_CCFG_TI_OPTIONS = 0xFE0,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0 = 0xFE4,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1 = 0xFE8,
|
||||
CC2650_CCFG_IMAGE_VALID_CONF = 0xFEC,
|
||||
CC2650_CCFG_CCFG_PROT_31_0 = 0xFF0,
|
||||
CC2650_CCFG_CCFG_PROT_63_32 = 0xFF4,
|
||||
CC2650_CCFG_CCFG_PROT_95_64 = 0xFF8,
|
||||
CC2650_CCFG_CCFG_PROT_127_96 = 0xFFC
|
||||
};
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* EXT_LF_CLK */
|
||||
enum CC2650_CCFG_EXT_LF_CLK_POS {
|
||||
CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_POS = 0,
|
||||
CC2650_CCFG_EXT_LF_CLK_DIO_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_EXT_LF_CLK_MASK {
|
||||
CC2650_CCFG_EXT_LF_CLK_RTC_INCREMENT_MASK = 0x00FFFFFF,
|
||||
CC2650_CCFG_EXT_LF_CLK_DIO_MASK = 0xFF000000
|
||||
};
|
||||
|
||||
/* MODE_CONF_1 */
|
||||
enum CC2650_CCFG_MODE_CONF_1_POS {
|
||||
CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_POS = 0,
|
||||
CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_POS = 8,
|
||||
CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_POS = 12,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_POS = 16,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_POS = 19,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_POS = 20
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_MODE_CONF_1_MASK {
|
||||
CC2650_CCFG_MODE_CONF_1_XOSC_MAX_START_MASK = 0x000000FF,
|
||||
CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_MASK = 0x00000F00,
|
||||
CC2650_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_MASK = 0x0000F000,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_MASK = 0x00070000,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_MASK = 0x00080000,
|
||||
CC2650_CCFG_MODE_CONF_1_ALT_DCDC_VMIN_MASK = 0x00F00000
|
||||
};
|
||||
|
||||
/* SIZE_AND_DIS_FLAGS */
|
||||
enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_POS {
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_POS = 0,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_POS = 1,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_POS = 2,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_POS = 3,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_POS = 4,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_SIZE_AND_DIS_FLAGS_MASK {
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCD_C_SETTING_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_MASK =
|
||||
0x0000FFF0,
|
||||
CC2650_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_MASK =
|
||||
0xFFFF0000
|
||||
};
|
||||
|
||||
/* MODE_CONF */
|
||||
enum CC2650_CCFG_MODE_CONF_POS {
|
||||
CC2650_CCFG_MODE_CONF_VDDR_CAP_POS = 0,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_POS = 8,
|
||||
CC2650_CCFG_MODE_CONF_HF_COMP_POS = 16,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_POS = 17,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_FREQ_POS = 18,
|
||||
CC2650_CCFG_MODE_CONF_RTC_COMP_POS = 20,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_POS = 21,
|
||||
CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_POS = 22,
|
||||
CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_POS = 24,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_POS = 25,
|
||||
CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_POS = 26,
|
||||
CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_POS = 27,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_POS = 28
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_MODE_CONF_MASK {
|
||||
CC2650_CCFG_MODE_CONF_VDDR_CAP_MASK =
|
||||
0x000000FF,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_MASK =
|
||||
0x0000FF00,
|
||||
CC2650_CCFG_MODE_CONF_HF_COMP_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_CAP_MOD_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_MODE_CONF_XOSC_FREQ_MASK =
|
||||
0x000C0000,
|
||||
CC2650_CCFG_MODE_CONF_RTC_COMP_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_MODE_CONF_SCLK_LF_OPTION_MASK =
|
||||
0x00C00000,
|
||||
CC2650_CCFG_MODE_CONF_VDDS_BOD_LEVEL_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_EXT_LOAD_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_MODE_CONF_DCDC_ACTIVE_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_MODE_CONF_DCDC_RECHARGE_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_MASK =
|
||||
0xF0000000
|
||||
};
|
||||
|
||||
/* VOLT_LOAD_0 */
|
||||
enum CC2650_CCFG_VOLT_LOAD_0_POS {
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_POS = 0,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_POS = 8,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_POS = 16,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_VOLT_LOAD_0_MASK {
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_MASK = 0x000000FF,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_MASK = 0x0000FF00,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_MASK = 0x00FF0000,
|
||||
CC2650_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_MASK = 0xFF000000
|
||||
};
|
||||
|
||||
/* VOLT_LOAD_1 */
|
||||
enum CC2650_CCFG_VOLT_LOAD_1_POS {
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_POS = 0,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_POS = 8,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_POS = 16,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_VOLT_LOAD_1_MASK {
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_MASK = 0x000000FF,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_MASK = 0x0000FF00,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_MASK = 0x00FF0000,
|
||||
CC2650_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_MASK = 0xFF000000
|
||||
};
|
||||
|
||||
/* RTC_OFFSET */
|
||||
enum CC2650_CCFG_RTC_OFFSET_POS {
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_POS = 0,
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_POS = 8,
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_RTC_OFFSET_MASK {
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P2_MASK = 0x000000FF,
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P1_MASK = 0x0000FF00,
|
||||
CC2650_CCFG_RTC_OFFSET_RTC_COMP_P0_MASK = 0xFFFF0000
|
||||
};
|
||||
|
||||
/* FREQ_OFFSET */
|
||||
enum CC2650_CCFG_FREQ_OFFSET_POS {
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_POS = 0,
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_POS = 8,
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_FREQ_OFFSET_MASK {
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P2_MASK = 0x000000FF,
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P1_MASK = 0x0000FF00,
|
||||
CC2650_CCFG_FREQ_OFFSET_HF_COMP_P0_MASK = 0xFFFF0000
|
||||
};
|
||||
|
||||
/* IEEE_MAC_0 */
|
||||
enum CC2650_CCFG_IEEE_MAC_0_POS {
|
||||
CC2650_CCFG_IEEE_MAC_0_ADDR_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IEEE_MAC_0_MASK {
|
||||
CC2650_CCFG_IEEE_MAC_0_ADDR_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
/* IEEE_MAC_1 */
|
||||
enum CC2650_CCFG_IEEE_MAC_1_POS {
|
||||
CC2650_CCFG_IEEE_MAC_1_ADDR_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IEEE_MAC_1_MASK {
|
||||
CC2650_CCFG_IEEE_MAC_1_ADDR_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
/* IEEE_BLE_0 */
|
||||
enum CC2650_CCFG_IEEE_BLE_POS {
|
||||
CC2650_CCFG_IEEE_BLE_0_ADDR_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IEEE_BLE_MASK {
|
||||
CC2650_CCFG_IEEE_BLE_0_ADDR_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
/* IEEE_BLE_1 */
|
||||
enum CC2650_CCFG_IEEE_BLE_1_POS {
|
||||
CC2650_CCFG_IEEE_BLE_1_ADDR_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IEEE_BLE_1_MASK {
|
||||
CC2650_CCFG_IEEE_BLE_1_ADDR_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
/* BL_CONFIG */
|
||||
enum CC2650_CCFG_BL_CONFIG_POS {
|
||||
CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS = 0,
|
||||
CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS = 8,
|
||||
CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS = 16,
|
||||
CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_BL_CONFIG_MASK {
|
||||
CC2650_CCFG_BL_CONFIG_BL_ENABLE_MASK = 0x000000FF,
|
||||
CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_MASK = 0x0000FF00,
|
||||
CC2650_CCFG_BL_CONFIG_BL_LEVEL_MASK = 0x00010000,
|
||||
CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_MASK = 0xFF000000
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_BL_CONFIG_VALUES {
|
||||
CC2650_CCFG_BACKDOOR_ENABLED =
|
||||
0xC5 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS,
|
||||
CC2650_CCFG_BACKDOOR_DISABLED =
|
||||
0x00 << CC2650_CCFG_BL_CONFIG_BL_ENABLE_POS,
|
||||
CC2650_CCFG_BACKDOOR_ACTIVE_HIGH =
|
||||
0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS,
|
||||
CC2650_CCFG_BACKDOOR_ACTIVE_LOW =
|
||||
0x0 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS,
|
||||
CC2650_CCFG_BOOTLOADER_ENABLED =
|
||||
0xC5 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS,
|
||||
CC2650_CCFG_BOOTLOADER_DISABLED =
|
||||
0x00 << CC2650_CCFG_BL_CONFIG_BOOTLOADER_ENABLE_POS
|
||||
};
|
||||
|
||||
/* ERASE_CONF */
|
||||
enum CC2650_CCFG_ERASE_CONF_POS {
|
||||
CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_POS = 0,
|
||||
CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_POS = 8
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_ERASE_CONF_MASK {
|
||||
CC2650_CCFG_ERASE_CONF_BANK_ERASE_DIS_N_MASK = 0x00000001,
|
||||
CC2650_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_MASK = 0x00000100
|
||||
};
|
||||
|
||||
/* CCFG_TI_OPTIONS */
|
||||
enum CC2650_CCFG_TI_OPTIONS_POS {
|
||||
CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_TI_OPTIONS_MASK {
|
||||
CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_MASK = 0x000000FF
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_TI_OPTIONS_VALUES {
|
||||
CC2650_CCFG_TI_FA_ENABLED =
|
||||
0xC5 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS,
|
||||
CC2650_CCFG_TI_FA_DISABLED =
|
||||
0x00 << CC2650_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_POS
|
||||
};
|
||||
|
||||
/* CCFG_TAP_DAP_0 */
|
||||
enum CC2650_CCFG_TAP_DAP_0_POS {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_POS = 0,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_POS = 8,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_TAP_DAP_0_MASK {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_MASK =
|
||||
0x000000FF,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_MASK =
|
||||
0x0000FF00,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_MASK =
|
||||
0x00FF0000
|
||||
};
|
||||
|
||||
/* CCFG_TAP_DAP_1 */
|
||||
enum CC2650_CCFG_CCFG_TAP_DAP_1_POS {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_POS = 0,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_POS = 8,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_POS = 16
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_TAP_DAP_1_MASK {
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_MASK =
|
||||
0x000000FF,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_MASK =
|
||||
0x0000FF00,
|
||||
CC2650_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_MASK =
|
||||
0x00FF0000
|
||||
};
|
||||
|
||||
/* IMAGE_VALID_CONF */
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_POS {
|
||||
CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_MASK {
|
||||
CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_MASK = 0xFFFFFFFF
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_IMAGE_VALID_CONF_VALUES {
|
||||
CC2650_CCFG_IMAGE_IS_VALID =
|
||||
0x00000000 << CC2650_CCFG_IMAGE_VALID_CONF_IMAGE_VALID_POS
|
||||
};
|
||||
|
||||
/* CCFG_PROT_31_0 */
|
||||
enum CC2650_CCFG_CCFG_PROT_31_0_POS {
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_POS = 0,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_POS = 1,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_POS = 2,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_POS = 3,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_POS = 4,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_POS = 5,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_POS = 6,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_POS = 7,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_POS = 8,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_POS = 9,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_POS = 10,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_POS = 11,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_POS = 12,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_POS = 13,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_POS = 14,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_POS = 15,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_POS = 16,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_POS = 17,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_POS = 18,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_POS = 19,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_POS = 20,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_POS = 21,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_POS = 22,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_POS = 23,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_POS = 24,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_POS = 25,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_POS = 26,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_POS = 27,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_POS = 28,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_POS = 29,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_POS = 30,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_31_0_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_63_32 */
|
||||
enum CC2650_CCFG_CCFG_PROT_63_32_POS {
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_POS = 32,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_POS = 33,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_POS = 34,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_POS = 35,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_POS = 36,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_POS = 37,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_POS = 38,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_POS = 39,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_POS = 40,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_POS = 41,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_POS = 42,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_POS = 43,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_POS = 44,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_POS = 45,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_POS = 46,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_POS = 47,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_POS = 48,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_POS = 49,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_POS = 50,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_POS = 51,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_POS = 52,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_POS = 53,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_POS = 54,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_POS = 55,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_POS = 56,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_POS = 57,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_POS = 58,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_POS = 59,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_POS = 60,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_POS = 61,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_POS = 62,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_POS = 63
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_63_32_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_95_64 */
|
||||
enum CC2650_CCFG_CCFG_PROT_95_64_POS {
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_POS = 64,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_POS = 65,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_POS = 66,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_POS = 67,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_POS = 68,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_POS = 69,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_POS = 70,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_POS = 71,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_POS = 72,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_POS = 73,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_POS = 74,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_POS = 75,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_POS = 76,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_POS = 77,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_POS = 78,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_POS = 79,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_POS = 80,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_POS = 81,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_POS = 82,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_POS = 83,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_POS = 84,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_POS = 85,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_POS = 86,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_POS = 87,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_POS = 88,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_POS = 89,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_POS = 90,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_POS = 91,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_POS = 92,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_POS = 93,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_POS = 94,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_POS = 95
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_95_64_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
/* CCFG_PROT_127_96 */
|
||||
enum CC2650_CCFG_CCFG_PROT_127_96_POS {
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_POS = 96,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_POS = 97,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_POS = 98,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_POS = 99,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_POS = 100,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_POS = 101,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_POS = 102,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_POS = 103,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_POS = 104,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_POS = 105,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_POS = 106,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_POS = 107,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_POS = 108,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_POS = 109,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_POS = 110,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_POS = 111,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_POS = 112,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_POS = 113,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_POS = 114,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_POS = 115,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_POS = 116,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_POS = 117,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_POS = 118,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_POS = 119,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_POS = 120,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_POS = 121,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_POS = 122,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_POS = 123,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_POS = 124,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_POS = 125,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_POS = 126,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_POS = 127
|
||||
};
|
||||
|
||||
enum CC2650_CCFG_CCFG_PROT_127_96_MASK {
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_MASK =
|
||||
0x00000001,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_MASK =
|
||||
0x00000002,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_MASK =
|
||||
0x00000004,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_MASK =
|
||||
0x00000008,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_MASK =
|
||||
0x00000010,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_MASK =
|
||||
0x00000020,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_MASK =
|
||||
0x00000040,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_MASK =
|
||||
0x00000080,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_MASK =
|
||||
0x00000100,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_MASK =
|
||||
0x00000200,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_MASK =
|
||||
0x00000400,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_MASK =
|
||||
0x00000800,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_MASK =
|
||||
0x00001000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_MASK =
|
||||
0x00002000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_MASK =
|
||||
0x00004000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_MASK =
|
||||
0x00008000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_MASK =
|
||||
0x00010000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_MASK =
|
||||
0x00020000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_MASK =
|
||||
0x00040000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_MASK =
|
||||
0x00080000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_MASK =
|
||||
0x00100000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_MASK =
|
||||
0x00200000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_MASK =
|
||||
0x00400000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_MASK =
|
||||
0x00800000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_MASK =
|
||||
0x01000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_MASK =
|
||||
0x02000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_MASK =
|
||||
0x04000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_MASK =
|
||||
0x08000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_MASK =
|
||||
0x10000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_MASK =
|
||||
0x20000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_MASK =
|
||||
0x40000000,
|
||||
CC2650_CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_MASK =
|
||||
0x80000000
|
||||
};
|
||||
|
||||
#endif /* _CC2650_CCFG_H_ */
|
||||
|
|
@ -1,658 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* GPIO registers and bit offsets for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_GPIO_H_
|
||||
#define _CC2650_GPIO_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_GPIO_Registers {
|
||||
CC2650_GPIO_DOUT3_0 = 0x0,
|
||||
CC2650_GPIO_DOUT7_4 = 0x4,
|
||||
CC2650_GPIO_DOUT11_8 = 0x8,
|
||||
CC2650_GPIO_DOUT15_12 = 0xC,
|
||||
CC2650_GPIO_DOUT19_16 = 0x10,
|
||||
CC2650_GPIO_DOUT23_20 = 0x14,
|
||||
CC2650_GPIO_DOUT27_24 = 0x18,
|
||||
CC2650_GPIO_DOUT31_28 = 0x1C,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUT31_0 = 0x80,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTSET31_0 = 0x90,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTCLR31_0 = 0XA0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOUTTGL31_0 = 0xB0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DIN31_0 = 0xC0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_DOE31_0 = 0xD0,
|
||||
/* Reserved */
|
||||
CC2650_GPIO_EVFLAGS31_0 = 0xE0
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* DOUT3_0 */
|
||||
enum CC2650_GPIO_DOUT3_0_POS {
|
||||
CC2650_GPIO_DOUT3_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUT3_0_DIO1_POS = 8,
|
||||
CC2650_GPIO_DOUT3_0_DIO2_POS = 16,
|
||||
CC2650_GPIO_DOUT3_0_DIO3_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT3_0_MASK {
|
||||
CC2650_GPIO_DOUT3_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT3_0_DIO1_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT3_0_DIO2_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT3_0_DIO3_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT7_4 */
|
||||
enum CC2650_GPIO_DOUT7_4_POS {
|
||||
CC2650_GPIO_DOUT7_4_DIO4_POS = 0,
|
||||
CC2650_GPIO_DOUT7_4_DIO5_POS = 8,
|
||||
CC2650_GPIO_DOUT7_4_DIO6_POS = 16,
|
||||
CC2650_GPIO_DOUT7_4_DIO7_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT7_4_MASK {
|
||||
CC2650_GPIO_DOUT7_4_DIO4_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT7_4_DIO5_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT7_4_DIO6_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT7_4_DIO7_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT11_8 */
|
||||
enum CC2650_GPIO_DOUT11_8_POS {
|
||||
CC2650_GPIO_DOUT11_8_DIO8_POS = 0,
|
||||
CC2650_GPIO_DOUT11_8_DIO9_POS = 8,
|
||||
CC2650_GPIO_DOUT11_8_DIO10_POS = 16,
|
||||
CC2650_GPIO_DOUT11_8_DIO11_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT11_8_MASK {
|
||||
CC2650_GPIO_DOUT11_8_DIO8_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT11_8_DIO9_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT11_8_DIO10_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT11_8_DIO11_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT15_12 */
|
||||
enum CC2650_GPIO_DOUT15_12_POS {
|
||||
CC2650_GPIO_DOUT15_12_DIO12_POS = 0,
|
||||
CC2650_GPIO_DOUT15_12_DIO13_POS = 8,
|
||||
CC2650_GPIO_DOUT15_12_DIO14_POS = 16,
|
||||
CC2650_GPIO_DOUT15_12_DIO15_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT15_12_MASK {
|
||||
CC2650_GPIO_DOUT15_12_DIO12_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT15_12_DIO13_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT15_12_DIO14_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT15_12_DIO15_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT19_16 */
|
||||
enum CC2650_GPIO_DOUT19_16_POS {
|
||||
CC2650_GPIO_DOUT19_16_DIO16_POS = 0,
|
||||
CC2650_GPIO_DOUT19_16_DIO17_POS = 8,
|
||||
CC2650_GPIO_DOUT19_16_DIO18_POS = 16,
|
||||
CC2650_GPIO_DOUT19_16_DIO19_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT19_16_MASK {
|
||||
CC2650_GPIO_DOUT19_16_DIO16_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT19_16_DIO17_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT19_16_DIO18_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT19_16_DIO19_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT23_20 */
|
||||
enum CC2650_GPIO_DOUT23_20_POS {
|
||||
CC2650_GPIO_DOUT23_20_DIO20_POS = 0,
|
||||
CC2650_GPIO_DOUT23_20_DIO21_POS = 8,
|
||||
CC2650_GPIO_DOUT23_20_DIO22_POS = 16,
|
||||
CC2650_GPIO_DOUT23_20_DIO23_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT23_20_MASK {
|
||||
CC2650_GPIO_DOUT23_20_DIO20_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT23_20_DIO21_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT23_20_DIO22_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT23_20_DIO23_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT27_24 */
|
||||
enum CC2650_GPIO_DOUT27_24_POS {
|
||||
CC2650_GPIO_DOUT27_24_DIO24_POS = 0,
|
||||
CC2650_GPIO_DOUT27_24_DIO25_POS = 8,
|
||||
CC2650_GPIO_DOUT27_24_DIO26_POS = 16,
|
||||
CC2650_GPIO_DOUT27_24_DIO27_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT27_24_MASK {
|
||||
CC2650_GPIO_DOUT27_24_DIO24_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT27_24_DIO25_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT27_24_DIO26_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT27_24_DIO27_MASK = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT31_28 */
|
||||
enum CC2650_GPIO_DOUT31_28_POS {
|
||||
CC2650_GPIO_DOUT31_28_DIO28_POS = 0,
|
||||
CC2650_GPIO_DOUT31_28_DIO29_POS = 8,
|
||||
CC2650_GPIO_DOUT31_28_DIO30_POS = 16,
|
||||
CC2650_GPIO_DOUT31_28_DIO31_POS = 24
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT31_28_MASK {
|
||||
CC2650_GPIO_DOUT31_28_DIO28 = 0x00000001,
|
||||
CC2650_GPIO_DOUT31_28_DIO29 = 0x00000100,
|
||||
CC2650_GPIO_DOUT31_28_DIO30 = 0x00010000,
|
||||
CC2650_GPIO_DOUT31_28_DIO31 = 0x01000000
|
||||
};
|
||||
|
||||
/* DOUT31_0 */
|
||||
enum CC2650_GPIO_DOUT31_0_POS {
|
||||
CC2650_GPIO_DOUT31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUT31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUT31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUT31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUT31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUT31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUT31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUT31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUT31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUT31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUT31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUT31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUT31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUT31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUT31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUT31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUT31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUT31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUT31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUT31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUT31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUT31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUT31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUT31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUT31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUT31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUT31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUT31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUT31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUT31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUT31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUT31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUT31_0_MASK {
|
||||
CC2650_GPIO_DOUT31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUT31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUT31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUT31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUT31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUT31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUT31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUT31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUT31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUT31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUT31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUT31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUT31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUT31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUT31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUT31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUT31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUT31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUT31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUT31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUT31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUT31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUT31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUT31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUT31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUT31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTSET31_0 */
|
||||
enum CC2650_GPIO_DOUTSET31_0_POS {
|
||||
CC2650_GPIO_DOUTSET31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTSET31_0_MASK {
|
||||
CC2650_GPIO_DOUTSET31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTSET31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTCLR31_0 */
|
||||
enum CC2650_GPIO_DOUTCLR31_0_POS {
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTCLR31_0_MASK {
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTCLR31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOUTTGL31_0 */
|
||||
enum CC2650_GPIO_DOUTTGL31_0_POS {
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOUTTGL31_0_MASK {
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOUTTGL31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DIN31_0 */
|
||||
enum CC2650_GPIO_DIN31_0_POS {
|
||||
CC2650_GPIO_DIN31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DIN31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DIN31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DIN31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DIN31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DIN31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DIN31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DIN31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DIN31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DIN31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DIN31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DIN31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DIN31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DIN31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DIN31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DIN31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DIN31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DIN31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DIN31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DIN31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DIN31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DIN31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DIN31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DIN31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DIN31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DIN31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DIN31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DIN31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DIN31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DIN31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DIN31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DIN31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DIN31_0_MASK {
|
||||
CC2650_GPIO_DIN31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DIN31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DIN31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DIN31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DIN31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DIN31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DIN31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DIN31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DIN31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DIN31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DIN31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DIN31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DIN31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DIN31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DIN31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DIN31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DIN31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DIN31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DIN31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DIN31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DIN31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DIN31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DIN31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DIN31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DIN31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DIN31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DIN31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DIN31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DIN31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DIN31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DIN31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DIN31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* DOE31_0 */
|
||||
enum CC2650_GPIO_DOE31_0_POS {
|
||||
CC2650_GPIO_DOE31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_DOE31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_DOE31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_DOE31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_DOE31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_DOE31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_DOE31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_DOE31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_DOE31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_DOE31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_DOE31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_DOE31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_DOE31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_DOE31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_DOE31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_DOE31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_DOE31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_DOE31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_DOE31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_DOE31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_DOE31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_DOE31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_DOE31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_DOE31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_DOE31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_DOE31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_DOE31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_DOE31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_DOE31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_DOE31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_DOE31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_DOE31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_DOE31_0_MASK {
|
||||
CC2650_GPIO_DOE31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_DOE31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_DOE31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_DOE31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_DOE31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_DOE31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_DOE31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_DOE31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_DOE31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_DOE31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_DOE31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_DOE31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_DOE31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_DOE31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_DOE31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_DOE31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_DOE31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_DOE31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_DOE31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_DOE31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_DOE31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_DOE31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_DOE31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_DOE31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_DOE31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_DOE31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_DOE31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_DOE31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_DOE31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_DOE31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_DOE31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_DOE31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
/* EVFLAGS31_0 */
|
||||
enum CC2650_GPIO_EVFLAGS31_0_POS {
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO0_POS = 0,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO1_POS = 1,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO2_POS = 2,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO3_POS = 3,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO4_POS = 4,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO5_POS = 5,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO6_POS = 6,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO7_POS = 7,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO8_POS = 8,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO9_POS = 9,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO10_POS = 10,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO11_POS = 11,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO12_POS = 12,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO13_POS = 13,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO14_POS = 14,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO15_POS = 15,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO16_POS = 16,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO17_POS = 17,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO18_POS = 18,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO19_POS = 19,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO20_POS = 20,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO21_POS = 21,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO22_POS = 22,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO23_POS = 23,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO24_POS = 24,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO25_POS = 25,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO26_POS = 26,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO27_POS = 27,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO28_POS = 28,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO29_POS = 29,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO30_POS = 30,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO31_POS = 31
|
||||
};
|
||||
|
||||
enum CC2650_GPIO_EVFLAGS31_0_MASK {
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO0_MASK = 0x00000001,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO1_MASK = 0x00000002,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO2_MASK = 0x00000004,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO3_MASK = 0x00000008,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO4_MASK = 0x00000010,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO5_MASK = 0x00000020,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO6_MASK = 0x00000040,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO7_MASK = 0x00000080,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO8_MASK = 0x00000100,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO9_MASK = 0x00000200,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO10_MASK = 0x00000400,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO11_MASK = 0x00000800,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO12_MASK = 0x00001000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO13_MASK = 0x00002000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO14_MASK = 0x00004000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO15_MASK = 0x00008000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO16_MASK = 0x00010000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO17_MASK = 0x00020000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO18_MASK = 0x00040000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO19_MASK = 0x00080000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO20_MASK = 0x00100000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO21_MASK = 0x00200000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO22_MASK = 0x00400000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO23_MASK = 0x00800000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO24_MASK = 0x01000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO25_MASK = 0x02000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO26_MASK = 0x04000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO27_MASK = 0x08000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO28_MASK = 0x10000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO29_MASK = 0x20000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO30_MASK = 0x40000000,
|
||||
CC2650_GPIO_EVFLAGS31_0_DIO31_MASK = 0x80000000
|
||||
};
|
||||
|
||||
#endif /* _CC2650_GPIO_H_ */
|
||||
|
|
@ -1,270 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* GPIO & I/O controller registers and bit offsets for the
|
||||
* CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_IOC_H_
|
||||
#define _CC2650_IOC_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_IOC_Registers {
|
||||
CC2650_IOC_IOCFG0 = 0x0,
|
||||
CC2650_IOC_IOCFG1 = 0x4,
|
||||
CC2650_IOC_IOCFG2 = 0x8,
|
||||
CC2650_IOC_IOCFG3 = 0xC,
|
||||
CC2650_IOC_IOCFG4 = 0x10,
|
||||
CC2650_IOC_IOCFG5 = 0x14,
|
||||
CC2650_IOC_IOCFG6 = 0x18,
|
||||
CC2650_IOC_IOCFG7 = 0x1C,
|
||||
CC2650_IOC_IOCFG8 = 0x20,
|
||||
CC2650_IOC_IOCFG9 = 0x24,
|
||||
CC2650_IOC_IOCFG10 = 0x28,
|
||||
CC2650_IOC_IOCFG11 = 0x2C,
|
||||
CC2650_IOC_IOCFG12 = 0x30,
|
||||
CC2650_IOC_IOCFG13 = 0x34,
|
||||
CC2650_IOC_IOCFG14 = 0x38,
|
||||
CC2650_IOC_IOCFG15 = 0x3C,
|
||||
CC2650_IOC_IOCFG16 = 0x40,
|
||||
CC2650_IOC_IOCFG17 = 0x44,
|
||||
CC2650_IOC_IOCFG18 = 0x48,
|
||||
CC2650_IOC_IOCFG19 = 0x4C,
|
||||
CC2650_IOC_IOCFG20 = 0x50,
|
||||
CC2650_IOC_IOCFG21 = 0x54,
|
||||
CC2650_IOC_IOCFG22 = 0x58,
|
||||
CC2650_IOC_IOCFG23 = 0x5C,
|
||||
CC2650_IOC_IOCFG24 = 0x60,
|
||||
CC2650_IOC_IOCFG25 = 0x64,
|
||||
CC2650_IOC_IOCFG26 = 0x68,
|
||||
CC2650_IOC_IOCFG27 = 0x6C,
|
||||
CC2650_IOC_IOCFG28 = 0x70,
|
||||
CC2650_IOC_IOCFG29 = 0x74,
|
||||
CC2650_IOC_IOCFG30 = 0x78,
|
||||
CC2650_IOC_IOCFG31 = 0x7C
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* I/O Controller */
|
||||
/* All IOCFGx registers are the same. */
|
||||
enum CC2650_IOC_IOCFGX_POS {
|
||||
CC2650_IOC_IOCFGX_PORT_ID_POS = 0,
|
||||
CC2650_IOC_IOCFGX_IOSTR_POS = 8,
|
||||
CC2650_IOC_IOCFGX_IOCURR_POS = 10,
|
||||
CC2650_IOC_IOCFGX_SLEW_RED_POS = 12,
|
||||
CC2650_IOC_IOCFGX_PULL_CTL_POS = 13,
|
||||
CC2650_IOC_IOCFGX_EDGE_DET_POS = 16,
|
||||
CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS = 18,
|
||||
CC2650_IOC_IOCFGX_IOMODE_POS = 24,
|
||||
CC2650_IOC_IOCFGX_WU_CFG_POS = 27,
|
||||
CC2650_IOC_IOCFGX_IE_POS = 29,
|
||||
CC2650_IOC_IOCFGX_HYST_EN_POS = 30
|
||||
};
|
||||
|
||||
enum CC2650_IOC_IOCFGX_MASK {
|
||||
CC2650_IOC_IOCFGX_PORT_ID_MASK = 0x0000003F,
|
||||
CC2650_IOC_IOCFGX_IOSTR_MASK = 0x00000300,
|
||||
CC2650_IOC_IOCFGX_IOCURR_MASK = 0x00000C00,
|
||||
CC2650_IOC_IOCFGX_SLEW_RED_MASK = 0x00001000,
|
||||
CC2650_IOC_IOCFGX_PULL_CTL_MASK = 0x00006000,
|
||||
CC2650_IOC_IOCFGX_EDGE_DET_MASK = 0x00030000,
|
||||
CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK = 0x00040000,
|
||||
CC2650_IOC_IOCFGX_IOMODE_MASK = 0x07000000,
|
||||
CC2650_IOC_IOCFGX_WU_CFG_MASK = 0x18000000,
|
||||
CC2650_IOC_IOCFGX_IE_MASK = 0x20000000,
|
||||
CC2650_IOC_IOCFGX_HYST_EN_MASK = 0x40000000
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* Port-IDs available */
|
||||
enum CC2650_IOC_PORTID {
|
||||
CC2650_IOC_GPIO =
|
||||
0 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SCS =
|
||||
1 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SCK =
|
||||
2 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SDI =
|
||||
3 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AON_SDO =
|
||||
4 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_AON_CLK32K =
|
||||
7 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_AUX_IO =
|
||||
8 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_RX =
|
||||
9 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_TX =
|
||||
10 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_FSS =
|
||||
11 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI0_CLK =
|
||||
12 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2C_MSSDA =
|
||||
13 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2C_MSSCL =
|
||||
14 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_RX =
|
||||
15 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_TX =
|
||||
16 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_CTS =
|
||||
17 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_UART0_RTS =
|
||||
18 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_MCU_GPTM_GPTM0 =
|
||||
23 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM1 =
|
||||
24 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM2 =
|
||||
25 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM3 =
|
||||
26 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM4 =
|
||||
27 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM5 =
|
||||
28 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM6 =
|
||||
29 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_GPTM_GPTM7 =
|
||||
30 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_MCU_CM3_SWV =
|
||||
32 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_RX =
|
||||
33 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_TX =
|
||||
34 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_FSS =
|
||||
35 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_SSI1_CLK =
|
||||
36 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_AD0 =
|
||||
37 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_AD1 =
|
||||
38 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_WCLK =
|
||||
39 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_BCLK =
|
||||
40 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_MCU_I2S_MCLK =
|
||||
41 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
/* Reserved */
|
||||
CC2650_IOC_RFC_GP0 =
|
||||
47 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP1 =
|
||||
48 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP2 =
|
||||
49 << CC2650_IOC_IOCFGX_PORT_ID_POS,
|
||||
CC2650_IOC_RFC_GP3 =
|
||||
50 << CC2650_IOC_IOCFGX_PORT_ID_POS
|
||||
/* Reserved */
|
||||
};
|
||||
|
||||
/* IOSTR (drive strength) values available */
|
||||
enum CC2650_IOC_IOSTR {
|
||||
CC2650_IOC_AUTO_DRIVE_STRENGTH =
|
||||
0 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MIN_DRIVE_STRENGTH =
|
||||
1 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MED_DRIVE_STRENGTH =
|
||||
2 << CC2650_IOC_IOCFGX_IOSTR_POS,
|
||||
CC2650_IOC_MAX_DRIVE_STRENGTH =
|
||||
3 << CC2650_IOC_IOCFGX_IOSTR_POS
|
||||
};
|
||||
|
||||
/* IOCURR (IO current) values available */
|
||||
enum CC2650_IOC_IOCURR {
|
||||
CC2650_IOC_LOW_CURRENT_MODE =
|
||||
0 << CC2650_IOC_IOCFGX_IOCURR_POS,
|
||||
CC2650_IOC_HIGH_CURRENT_MODE =
|
||||
1 << CC2650_IOC_IOCFGX_IOCURR_POS,
|
||||
CC2650_IOC_EXTENDED_CURRENT_MODE =
|
||||
2 << CC2650_IOC_IOCFGX_IOCURR_POS
|
||||
};
|
||||
|
||||
/* SLEW_RED (slew rate) values available */
|
||||
enum CC2650_IOC_SLEW_RED {
|
||||
CC2650_IOC_NORMAL_SLEW_RATE =
|
||||
0 << CC2650_IOC_IOCFGX_SLEW_RED_POS,
|
||||
CC2650_IOC_REDUCED_SLEW_RATE =
|
||||
1 << CC2650_IOC_IOCFGX_SLEW_RED_POS
|
||||
};
|
||||
|
||||
/* PULL_CTL (pull-* modes) values available */
|
||||
enum CC2650_IOC_PULL_CTL {
|
||||
CC2650_IOC_PULL_DOWN =
|
||||
1 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
|
||||
CC2650_IOC_PULL_UP =
|
||||
2 << CC2650_IOC_IOCFGX_PULL_CTL_POS,
|
||||
CC2650_IOC_NO_PULL =
|
||||
3 << CC2650_IOC_IOCFGX_PULL_CTL_POS
|
||||
};
|
||||
|
||||
/* EDGE_DET (edge detection) values available */
|
||||
enum CC2650_IOC_EDGE_DET {
|
||||
CC2650_IOC_NO_EDGE_DET =
|
||||
0 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_NEG_EDGE_DET =
|
||||
1 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_POS_EDGE_DET =
|
||||
2 << CC2650_IOC_IOCFGX_EDGE_DET_POS,
|
||||
CC2650_IOC_NEG_AND_POS_EDGE_DET =
|
||||
3 << CC2650_IOC_IOCFGX_EDGE_DET_POS
|
||||
};
|
||||
|
||||
/* IOMODE values available */
|
||||
enum CC2650_IOC_IOMODE {
|
||||
CC2650_IOC_NORMAL_IO =
|
||||
0 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_INVERTED_IO =
|
||||
1 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_DRAIN_IO =
|
||||
4 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_DRAIN_INVERTED_IO =
|
||||
5 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_SOURCE_IO =
|
||||
6 << CC2650_IOC_IOCFGX_IOMODE_POS,
|
||||
CC2650_IOC_OPEN_SOURCE_INVERTED_IO =
|
||||
7 << CC2650_IOC_IOCFGX_IOMODE_POS
|
||||
};
|
||||
|
||||
/* WU_CFG (Wake-up control) values available */
|
||||
enum CC2650_IOC_WU_CFG {
|
||||
/* Values' meaning change with PORT_ID, so here we only
|
||||
* give very generic names...
|
||||
*/
|
||||
CC2650_IOC_WAKE_UP_0 =
|
||||
0 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_1 =
|
||||
1 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_2 =
|
||||
2 << CC2650_IOC_IOCFGX_WU_CFG_POS,
|
||||
CC2650_IOC_WAKE_UP_3 =
|
||||
3 << CC2650_IOC_IOCFGX_WU_CFG_POS
|
||||
};
|
||||
|
||||
/* IE (Input control) values available */
|
||||
enum CC2650_IOC_IE {
|
||||
CC2650_IOC_INPUT_DISABLED =
|
||||
0 << CC2650_IOC_IOCFGX_IE_POS,
|
||||
CC2650_IOC_INPUT_ENABLED =
|
||||
1 << CC2650_IOC_IOCFGX_IE_POS
|
||||
};
|
||||
|
||||
/* HYST_EN (Hysteresis control) values available */
|
||||
enum CC2650_IOC_HYST_EN {
|
||||
CC2650_IOC_HYSTERESIS_DISABLED =
|
||||
0 << CC2650_IOC_IOCFGX_HYST_EN_POS,
|
||||
CC2650_IOC_HYSTERESIS_ENABLED =
|
||||
1 << CC2650_IOC_IOCFGX_HYST_EN_POS
|
||||
};
|
||||
|
||||
#endif /* _CC2650_IOC_H_ */
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Offsets for the Power, Reset, and Clock Management module
|
||||
* registers, in the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_PRCM_H_
|
||||
#define _CC2650_PRCM_H_
|
||||
|
||||
/* Registers */
|
||||
|
||||
enum CC2650_PRCM_Registers {
|
||||
CC2650_PRCM_CLKLOADCTL = 0x28,
|
||||
CC2650_PRCM_SECDMACLKGR = 0x3C,
|
||||
CC2650_PRCM_GPIOCLKGR = 0x48,
|
||||
CC2650_PRCM_UARTCLKGR = 0x6C,
|
||||
CC2650_PRCM_UARTCLKGS = 0x70,
|
||||
CC2650_PRCM_UARTCLKGDS = 0x74,
|
||||
CC2650_PRCM_PDCTL0 = 0x12C,
|
||||
CC2650_PRCM_PDSTAT0 = 0x140
|
||||
};
|
||||
|
||||
|
||||
/* Register-specific bits */
|
||||
|
||||
/* CLKLOADCTL */
|
||||
enum CC2650_PRCM_CLKLOADCT_POS {
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_POS = 0,
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_DONE_POS = 1
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_CLKLOADCTL_MASK {
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_MASK = 0x00000001,
|
||||
CC2650_PRCM_CLKLOADCTL_LOAD_DONE_MASK = 0x00000002
|
||||
};
|
||||
|
||||
/* SECDMACLKGR */
|
||||
enum CC2650_PRCM_SECDMACLKGR_POS {
|
||||
CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS = 1
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_SECDMACLKGR_MASK {
|
||||
CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_MASK = 0x00000002
|
||||
};
|
||||
|
||||
/* GPIOCLKGR */
|
||||
enum CC2650_PRCM_GPIOCLKGR_POS {
|
||||
CC2650_PRCM_GPIOCLKGR_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_GPIOCLKGR_MASK {
|
||||
CC2650_PRCM_GPIOCLKGR_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGR */
|
||||
enum CC2650_PRCM_UARTCLKGR_POS {
|
||||
CC2650_PRCM_UARTCLKGR_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGR_MASK {
|
||||
CC2650_PRCM_UARTCLKGR_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGS */
|
||||
enum CC2650_PRCM_UARTCLKGS_POS {
|
||||
CC2650_PRCM_UARTCLKGS_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGS_MASK {
|
||||
CC2650_PRCM_UARTCLKGS_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* UARTCLKGDS */
|
||||
enum CC2650_PRCM_UARTCLKGDS_POS {
|
||||
CC2650_PRCM_UARTCLKGDS_CLK_EN_POS = 0
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_UARTCLKGDS_MASK {
|
||||
CC2650_PRCM_UARTCLKGDS_CLK_EN_MASK = 0x00000001
|
||||
};
|
||||
|
||||
/* PDCTL0 */
|
||||
enum CC2650_PRCM_PDCTL0_POS {
|
||||
CC2650_PRCM_PDCTL0_SERIAL_ON_POS = 1,
|
||||
CC2650_PRCM_PDCTL0_PERIPH_ON_POS = 2
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_PDCTL0_MASK {
|
||||
CC2650_PRCM_PDCTL0_SERIAL_ON_MASK = 0x00000002,
|
||||
CC2650_PRCM_PDCTL0_PERIPH_ON_MASK = 0x00000004
|
||||
};
|
||||
|
||||
/* PDSTAT0 */
|
||||
enum CC2650_PRCM_PDSTAT0_POS {
|
||||
CC2650_PRCM_PDSTAT0_RFC_ON_POS = 0,
|
||||
CC2650_PRCM_PDSTAT0_SERIAL_ON_POS = 1,
|
||||
CC2650_PRCM_PDSTAT0_PERIPH_ON_POS = 2
|
||||
};
|
||||
|
||||
enum CC2650_PRCM_PDSTAT0_MASK {
|
||||
CC2650_PRCM_PDSTAT0_RFC_ON_MASK = 0x00000001,
|
||||
CC2650_PRCM_PDSTAT0_SERIAL_ON_MASK = 0x00000002,
|
||||
CC2650_PRCM_PDSTAT0_PERIPH_ON_MASK = 0x00000004
|
||||
};
|
||||
|
||||
#endif /* _CC2650_PRCM_H_ */
|
||||
|
|
@ -1,141 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Basic initialization for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#include <toolchain/gcc.h>
|
||||
#include <init.h>
|
||||
#include <sys/sys_io.h>
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
|
||||
#define CCFG_SIZE 88
|
||||
|
||||
/* The bootloader of the SoC (in ROM) reads configuration
|
||||
* data (CCFG) at a fixed address (last page of flash).
|
||||
* The most notable information being whether to run the
|
||||
* code stored in flash or not.
|
||||
*
|
||||
* We put configuration data in a specific section so that
|
||||
* the linker script can map it accordingly.
|
||||
*/
|
||||
const u32_t
|
||||
__ti_ccfg_section
|
||||
ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = {
|
||||
0x00008001, /* EXT_LF_CLK: default values */
|
||||
0xFF13FFFF, /* MODE_CONF_1: default values */
|
||||
0x0058FFFF, /* SIZE_AND_DIS_FLAGS: 88 bytes long, no external osc. */
|
||||
0xFFFFFFFF, /* MODE_CONF: default values */
|
||||
0xFFFFFFFF, /* VOLT_LOAD_0: default values */
|
||||
0xFFFFFFFF, /* VOLT_LOAD_1: default values */
|
||||
0xFFFFFFFF, /* RTC_OFFSET: default values */
|
||||
0xFFFFFFFF, /* FREQ_OFFSET: default values */
|
||||
0xFFFFFFFF, /* IEEE_MAC_0: use MAC address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_MAC_1: use MAC address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_BLE_0: use BLE address from FCFG */
|
||||
0xFFFFFFFF, /* IEEE_BLE_1: use BLE address from FCFG */
|
||||
/* BL_CONFIG: disable backdoor and bootloader,
|
||||
* default pin, default active level (high)
|
||||
*/
|
||||
CC2650_CCFG_BACKDOOR_DISABLED |
|
||||
(0xFF << CC2650_CCFG_BL_CONFIG_BL_PIN_NUMBER_POS) |
|
||||
(0x1 << CC2650_CCFG_BL_CONFIG_BL_LEVEL_POS) |
|
||||
0x00FE0000 | /* reserved */
|
||||
CC2650_CCFG_BOOTLOADER_DISABLED,
|
||||
0xFFFFFFFF, /* ERASE_CONF: default values (banks + chip erase) */
|
||||
/* CCFG_TI_OPTIONS: disable TI failure analysis */
|
||||
CC2650_CCFG_TI_FA_DISABLED |
|
||||
0xFFFFFF00, /* reserved */
|
||||
0xFFC5C5C5, /* CCFG_TAP_DAP_0: default values */
|
||||
0xFFC5C5C5, /* CCFG_TAP_DAP_1: default values */
|
||||
/* IMAGE_VALID_CONF: authorize program on flash to run */
|
||||
CC2650_CCFG_IMAGE_IS_VALID,
|
||||
/* Make all flash chip programmable + erasable
|
||||
* (which is default)
|
||||
*/
|
||||
0xFFFFFFFF, /* CCFG_PROT_31_0 */
|
||||
0xFFFFFFFF, /* CCFG_PROT_61_32 */
|
||||
0xFFFFFFFF, /* CCFG_PROT_95_64 */
|
||||
0xFFFFFFFF /* CCFG_PROT_127_96 */
|
||||
};
|
||||
|
||||
/* PRCM Registers */
|
||||
static const u32_t clkloadctl =
|
||||
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_CLKLOADCTL);
|
||||
static const u32_t gpioclkgr =
|
||||
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_GPIOCLKGR);
|
||||
static const u32_t pdctl0 =
|
||||
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_PDCTL0);
|
||||
static const u32_t pdstat0 =
|
||||
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_PDSTAT0);
|
||||
#ifdef CONFIG_SERIAL
|
||||
static const u32_t uartclkgr =
|
||||
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
|
||||
CC2650_PRCM_UARTCLKGR);
|
||||
#endif
|
||||
|
||||
/* Setup power and clock for needed hardware modules. */
|
||||
static void setup_modules_prcm(void)
|
||||
{
|
||||
#if defined(CONFIG_GPIO_CC2650) || \
|
||||
defined(CONFIG_SERIAL)
|
||||
|
||||
/* Setup power */
|
||||
#if defined(CONFIG_GPIO_CC2650)
|
||||
sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_PERIPH_ON_POS);
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL
|
||||
sys_set_bit(pdctl0, CC2650_PRCM_PDCTL0_SERIAL_ON_POS);
|
||||
#endif
|
||||
|
||||
/* Setup clocking */
|
||||
#ifdef CONFIG_GPIO_CC2650
|
||||
sys_set_bit(gpioclkgr, CC2650_PRCM_GPIOCLKGR_CLK_EN_POS);
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL
|
||||
sys_set_bit(uartclkgr, CC2650_PRCM_UARTCLKGR_CLK_EN_POS);
|
||||
#endif
|
||||
/* Reload clocking configuration for device */
|
||||
sys_set_bit(clkloadctl, CC2650_PRCM_CLKLOADCTL_LOAD_POS);
|
||||
|
||||
/* Wait for power to be completely on, to avoid bus faults
|
||||
* when accessing modules' registers.
|
||||
*/
|
||||
#if defined(CONFIG_GPIO_CC2650)
|
||||
while (!(sys_read32(pdstat0) &
|
||||
BIT(CC2650_PRCM_PDSTAT0_PERIPH_ON_POS))) {
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL)
|
||||
while (!(sys_read32(pdstat0) &
|
||||
BIT(CC2650_PRCM_PDSTAT0_SERIAL_ON_POS))) {
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static int ti_cc2650(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
NMI_INIT();
|
||||
setup_modules_prcm();
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(ti_cc2650, PRE_KERNEL_1, 0);
|
||||
|
||||
int bit_is_set(u32_t reg, u8_t bit)
|
||||
{
|
||||
return sys_read32(reg) & BIT(bit);
|
||||
}
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* General header for the CC2650 System on Chip.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CC2650_SOC_H_
|
||||
#define _CC2650_SOC_H_
|
||||
|
||||
#include <sys/util.h>
|
||||
#include "registers/ccfg.h"
|
||||
#include "registers/gpio.h"
|
||||
#include "registers/ioc.h"
|
||||
#include "registers/prcm.h"
|
||||
|
||||
|
||||
/* Helper functions and macros */
|
||||
|
||||
#define REG_ADDR(Base, Offset) (u32_t)(Base + (u32_t)Offset)
|
||||
|
||||
int bit_is_set(u32_t reg, u8_t bit);
|
||||
|
||||
|
||||
#endif /* _CC2650_SOC_H_ */
|
||||
Loading…
Reference in a new issue