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dma: Add config option for cyclic transfer lists

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Adds a bit flag config option for cyclic transfer lists, where the
transfer list tail may link to its head creating a never ending
loop of transfer descriptors.

DesignWare DMA supports such cyclic transfers.

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This commit is contained in:
Adrian Bonislawski 2022-03-23 13:28:10 -05:00 committed by Anas Nashif
parent 5ae78fbca5
commit b19e8cf979
1 changed files with 5 additions and 2 deletions
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7
include/drivers/dma.h
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@ -172,7 +172,9 @@ typedef void (*dma_callback_t)(const struct device *dev, void *user_data,
* @param linked_channel [ 20 : 26 ] - after channel count exhaust will
* initiate a channel service request
* at this channel
* @param reserved [ 27 : 31 ]
* @param cyclic [ 27 ] - enable/disable cyclic buffer
* 0-disable, 1-enable
* @param reserved [ 28 : 31 ]
* @param source_data_size [ 0 : 15 ] - width of source data (in bytes)
* @param dest_data_size [ 16 : 31 ] - width of dest data (in bytes)
* @param source_burst_length [ 0 : 15 ] - number of source data units
@ -193,7 +195,8 @@ struct dma_config {
uint32_t source_chaining_en : 1;
uint32_t dest_chaining_en : 1;
uint32_t linked_channel : 7;
uint32_t reserved : 5;
uint32_t cyclic : 1;
uint32_t reserved : 4;
uint32_t source_data_size : 16;
uint32_t dest_data_size : 16;
uint32_t source_burst_length : 16;