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drivers/clock_control: stm32 common: Use new bus clock bindings

Browse source 
Make use of new bus clocks bindings and make subsequent code
simplifications.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-29 16:19:02 +02:00 committed by Carles Cufí
parent bccf8afa59
commit b636e4c799
18 changed files with 78 additions and 166 deletions
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176
drivers/clock_control/clock_stm32_ll_common.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017 Linaro Limited.
* Copyright (c) 2017-2022 Linaro Limited.
* Copyright (c) 2017 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
@ -70,69 +70,15 @@ static inline int stm32_clock_control_on(const struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
volatile uint32_t *reg;
uint32_t reg_val;
ARG_UNUSED(dev);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_EnableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
#if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
break;
#endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_EnableClock(pclken->enr);
break;
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP:
LL_IOP_GRP1_EnableClock(pclken->enr);
break;
#endif
default:
return -ENOTSUP;
}
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
reg_val = *reg;
reg_val |= pclken->enr;
*reg = reg_val;
return 0;
}
@ -142,70 +88,21 @@ static inline int stm32_clock_control_off(const struct device *dev,
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
volatile uint32_t *reg;
uint32_t reg_val;
ARG_UNUSED(dev);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_DisableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB2_SUPPORT) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) && defined(RCC_AHB3_SUPPORT) || \
defined(CONFIG_SOC_SERIES_STM32F7X) || \
defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_DisableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr);
break;
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_DisableClock(pclken->enr);
break;
#endif /* CONFIG_SOC_SERIES_STM32_* */
#if !defined(CONFIG_SOC_SERIES_STM32F0X)
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr);
break;
#endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_DisableClock(pclken->enr);
break;
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP:
LL_IOP_GRP1_DisableClock(pclken->enr);
break;
#endif
default:
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
/* Attemp to toggle a wrong periph clock bit */
return -ENOTSUP;
}
reg = (uint32_t *)(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
reg_val = *reg;
reg_val &= ~pclken->enr;
*reg = reg_val;
return 0;
}
@ -225,54 +122,49 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), apb2_prescaler)
uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
#elif defined(STM32_CLOCK_BUS_APB2)
/* APB2 bus exists, but w/o dedicated prescaler */
uint32_t apb2_clock = apb1_clock;
#endif
#if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
uint32_t ahb3_clock = get_bus_clock(ahb_clock * STM32_CPU1_PRESCALER,
STM32_AHB3_PRESCALER);
#elif defined(STM32_CLOCK_BUS_AHB3)
/* AHB3 bus exists, but w/o dedicated prescaler */
uint32_t ahb3_clock = ahb_clock;
#endif
ARG_UNUSED(clock);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
#if defined(STM32_CLOCK_BUS_AHB2)
case STM32_CLOCK_BUS_AHB2:
#if !defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_AHB3:
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X)
#if defined(STM32_CLOCK_BUS_IOP)
case STM32_CLOCK_BUS_IOP:
#endif
*rate = ahb_clock;
break;
#if defined(STM32_CLOCK_BUS_AHB3)
case STM32_CLOCK_BUS_AHB3:
*rate = ahb3_clock;
break;
#endif
case STM32_CLOCK_BUS_APB1:
#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32WBX) || \
defined(CONFIG_SOC_SERIES_STM32WLX) || \
defined(CONFIG_SOC_SERIES_STM32G4X)
#if defined(STM32_CLOCK_BUS_APB1_2)
case STM32_CLOCK_BUS_APB1_2:
#endif /* CONFIG_SOC_SERIES_STM32_* */
#if defined(CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_APB2:
/*
* STM32G0x only has one APB, but two reset/clock enable
* registers for peripherals, so return the APB1 clock rate here
*/
#endif /* CONFIG_SOC_SERIES_STM32G0X */
#endif
*rate = apb1_clock;
break;
#if !defined (CONFIG_SOC_SERIES_STM32F0X) && \
!defined (CONFIG_SOC_SERIES_STM32G0X)
#if defined(STM32_CLOCK_BUS_APB2)
case STM32_CLOCK_BUS_APB2:
*rate = apb2_clock;
break;
#endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_AHB3:
#if defined(STM32_CLOCK_BUS_APB3)
case STM32_CLOCK_BUS_APB3:
/* AHB3 and APB3 share the same clock and prescaler. */
/* STM32WL: AHB3 and APB3 share the same clock and prescaler. */
*rate = ahb3_clock;
break;
#endif

16
dts/arm/st/f0/stm32f0.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f1_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
@ -157,7 +157,7 @@
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <27 0>;
status = "disabled";
label = "UART_1";
@ -203,7 +203,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <25 3>;
status = "disabled";
label = "SPI_1";
@ -237,7 +237,7 @@
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
@ -313,7 +313,7 @@
timers15: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
@ -331,7 +331,7 @@
timers16: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
@ -349,7 +349,7 @@
timers17: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
@ -367,7 +367,7 @@
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <12 0>;
status = "disabled";
label = "ADC_1";

2
dts/arm/st/f0/stm32f030Xc.dtsi
View file

@ -66,7 +66,7 @@
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <29 0>;
status = "disabled";
label = "UART_6";

2
dts/arm/st/f1/stm32f1.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f1_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/f2/stm32f2.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f4_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/f3/stm32f3.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f1_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/f4/stm32f4.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f4_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/f7/stm32f7.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32f4_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/g0/stm32g0.dtsi
View file

@ -9,7 +9,7 @@
*/
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32g0_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/g4/stm32g4.dtsi
View file

@ -7,7 +7,7 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l4_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/l0/stm32l0.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l0_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/l1/stm32l1.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l1_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/l4/stm32l4.dtsi
View file

@ -7,7 +7,7 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l4_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/l5/stm32l5.dtsi
View file

@ -7,7 +7,7 @@
#include <arm/armv8-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l4_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>

1
dts/arm/st/u5/stm32u5.dtsi
View file

@ -7,7 +7,6 @@
#include <arm/armv8-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32u5_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>

2
dts/arm/st/wb/stm32wb.dtsi
View file

@ -6,7 +6,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32l4_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>

2
dts/arm/st/wl/stm32wl.dtsi
View file

@ -5,7 +5,7 @@
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/clock/stm32wl_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/lora/sx126x.h>

23
include/zephyr/drivers/clock_control/stm32_clock_control.h
View file

@ -11,7 +11,28 @@
#include <drivers/clock_control.h>
#if defined(CONFIG_SOC_SERIES_STM32H7X)
#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
defined(CONFIG_SOC_SERIES_STM32F1X) || \
defined(CONFIG_SOC_SERIES_STM32F3X)
#include <dt-bindings/clock/stm32f1_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32F2X) || \
defined(CONFIG_SOC_SERIES_STM32F4X) || \
defined(CONFIG_SOC_SERIES_STM32F7X)
#include <dt-bindings/clock/stm32f4_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32G0X)
#include <dt-bindings/clock/stm32g0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32L0X)
#include <dt-bindings/clock/stm32l0_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32L1X)
#include <dt-bindings/clock/stm32l1_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32G4X) || \
defined(CONFIG_SOC_SERIES_STM32L4X) || \
defined(CONFIG_SOC_SERIES_STM32L5X) || \
defined(CONFIG_SOC_SERIES_STM32WBX)
#include <dt-bindings/clock/stm32l4_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32WLX)
#include <dt-bindings/clock/stm32wl_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32H7X)
#include <dt-bindings/clock/stm32h7_clock.h>
#elif defined(CONFIG_SOC_SERIES_STM32U5X)
#include <dt-bindings/clock/stm32u5_clock.h>