drivers: sdhc: add support of Renesas MMC driver
Add basic functionality of Renesas SD/MMC driver. It can be used
for both gen3 and gen4 R-car boards, but tested only with H3ULCB,
Salvator XS M3 and Spider boards. This driver working with SDHC
subsystem.
The driver supports regularal reading/writing throught SD/MMC
controller buffer, DMA mode w/o interrupts and timing tuning.
Add gpio5 and sd0 nodes to h3ulcb and salvator xs which are needed
for working with SD cards. The GPIO node is needed for switching
voltage on SD card through gpio regulator driver.
Notes:
* the driver doesn't support SPI mode;
* SCC tuning and DMA mode based on IRQs are enabled by default;
* an address of a data buffer has to be aligned to 128 bytes if it
is not, driver will use non-DMA mode automatically;
* Renesas MMC DMAC doesn't support 64-bit DMA addresses, so for
case when we have 64-bit xref data address we use non-DMA mode;
* SD/MMC controller supports block size between 512 and 1 with
a lot of restrictions, more details you can find in code;
* support of HS400 mode isn't implemented inside driver.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit is contained in:
Mykola Kvach
Anas Nashif
parent
11eed84775
commit
b8f7fc3cc3
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@ -6,6 +6,7 @@ zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_IMX_USDHC imx_usdhc.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SDHC sdhc_spi.c)
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zephyr_library_sources_ifdef(CONFIG_MCUX_SDIF mcux_sdif.c)
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zephyr_library_sources_ifdef(CONFIG_RCAR_MMC rcar_mmc.c)
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zephyr_library_sources_ifdef(CONFIG_SAM_HSMCI sam_hsmci.c)
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zephyr_library_sources_ifdef(CONFIG_INTEL_EMMC_HOST intel_emmc_host.c)
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zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c)
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@ -12,6 +12,7 @@ source "drivers/sdhc/Kconfig.ifx_cat1"
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source "drivers/sdhc/Kconfig.imx"
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source "drivers/sdhc/Kconfig.spi"
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source "drivers/sdhc/Kconfig.mcux_sdif"
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source "drivers/sdhc/Kconfig.rcar"
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source "drivers/sdhc/Kconfig.sam_hsmci"
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source "drivers/sdhc/Kconfig.intel"
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source "drivers/sdhc/Kconfig.sdhc_cdns"
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42
drivers/sdhc/Kconfig.rcar
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42
drivers/sdhc/Kconfig.rcar
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@ -0,0 +1,42 @@
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# Copyright (c) 2023 EPAM Systems
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# SPDX-License-Identifier: Apache-2.0
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config RCAR_MMC
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bool "Renesas Rcar MMC driver"
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default y
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depends on DT_HAS_RENESAS_RCAR_MMC_ENABLED
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select SDHC_SUPPORTS_NATIVE_MODE
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select REGULATOR
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select GPIO
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select SDHC_SUPPORTS_UHS if SDMMC_STACK
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help
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Renesas Rcar MMC driver.
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if RCAR_MMC
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config RCAR_MMC_DMA_SUPPORT
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bool "Internal DMA support for Renesas Rcar MMC driver"
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select CACHE_MANAGEMENT
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select DCACHE
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default y
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help
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Internal DMA support for Renesas Rcar MMC driver.
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config RCAR_MMC_SCC_SUPPORT
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bool "Support of SCC"
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default y
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help
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Enable support of Sampling Clock Controller for Renesas Rcar MMC driver.
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if RCAR_MMC_DMA_SUPPORT
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config SDHC_BUFFER_ALIGNMENT
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default 128
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config RCAR_MMC_DMA_IRQ_DRIVEN_SUPPORT
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bool "Internal DMA IRQ driven support for Renesas Rcar MMC driver"
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default y
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endif # RCAR_MMC_DMA_SUPPORT
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endif # RCAR_MMC
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2223
drivers/sdhc/rcar_mmc.c
Normal file
2223
drivers/sdhc/rcar_mmc.c
Normal file
File diff suppressed because it is too large
Load diff
221
drivers/sdhc/rcar_mmc_registers.h
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221
drivers/sdhc/rcar_mmc_registers.h
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@ -0,0 +1,221 @@
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/*
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* Copyright (c) 2023 EPAM Systems
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __RCAR_MMC_REGISTERS_H__
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#define __RCAR_MMC_REGISTERS_H__
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#include <zephyr/sys/util_macro.h> /* for BIT macro */
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/*
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* The command type register is used to select the command type
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* and response type
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*/
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#define RCAR_MMC_CMD 0x000 /* command */
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#define RCAR_MMC_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
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#define RCAR_MMC_CMD_MULTI BIT(13) /* multiple block transfer */
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#define RCAR_MMC_CMD_RD BIT(12) /* 1: read, 0: write */
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#define RCAR_MMC_CMD_DATA BIT(11) /* data transfer */
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#define RCAR_MMC_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
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#define RCAR_MMC_CMD_NORMAL (0 << 8) /* auto-detect of resp-type */
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#define RCAR_MMC_CMD_RSP_NONE (3 << 8) /* response: none */
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#define RCAR_MMC_CMD_RSP_R1 (4 << 8) /* response: R1, R5, R6, R7 */
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#define RCAR_MMC_CMD_RSP_R1B (5 << 8) /* response: R1b, R5b */
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#define RCAR_MMC_CMD_RSP_R2 (6 << 8) /* response: R2 */
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#define RCAR_MMC_CMD_RSP_R3 (7 << 8) /* response: R3, R4 */
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/* Command arguments register for SD card */
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#define RCAR_MMC_ARG 0x010 /* command argument */
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/*
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* The data stop register is used to enable or disable block counting at
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* multiple block transfer, and to control the issuing of CMD12 within
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* command sequences.
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*/
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#define RCAR_MMC_STOP 0x020 /* stop action control */
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#define RCAR_MMC_STOP_SEC BIT(8) /* use sector count */
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#define RCAR_MMC_STOP_STP BIT(0) /* issue CMD12 */
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/*
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* The block count register is used to specify the number of
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* transfer blocks at multiple block transfer.
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*/
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#define RCAR_MMC_SECCNT 0x028 /* sector counter */
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/* The SD card response registers hold the response from the SD card */
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#define RCAR_MMC_RSP10 0x030 /* response[39:8] */
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#define RCAR_MMC_RSP32 0x040 /* response[71:40] */
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#define RCAR_MMC_RSP54 0x050 /* response[103:72] */
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#define RCAR_MMC_RSP76 0x060 /* response[127:104] */
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/*
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* The SD card interrupt flag register 1 indicates the response end and access
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* end in the command sequence. This register also indicates the card
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* detect/write protect state.
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*/
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#define RCAR_MMC_INFO1 0x070 /* IRQ status 1 */
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#define RCAR_MMC_INFO1_CD BIT(5) /* state of card detect */
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#define RCAR_MMC_INFO1_INSERT BIT(4) /* card inserted */
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#define RCAR_MMC_INFO1_REMOVE BIT(3) /* card removed */
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#define RCAR_MMC_INFO1_CMP BIT(2) /* data complete */
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#define RCAR_MMC_INFO1_RSP BIT(0) /* response complete */
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/*
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* The SD card interrupt flag register 2 indicates the access status of the
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* SD buffer and SD card.
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*/
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#define RCAR_MMC_INFO2 0x078 /* IRQ status 2 */
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#define RCAR_MMC_INFO2_ERR_ILA BIT(15) /* illegal access err */
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#define RCAR_MMC_INFO2_CBSY BIT(14) /* command busy */
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#define RCAR_MMC_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
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#define RCAR_MMC_INFO2_CLEAR BIT(11) /* the write value should always be 1 */
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#define RCAR_MMC_INFO2_BWE BIT(9) /* write buffer ready */
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#define RCAR_MMC_INFO2_BRE BIT(8) /* read buffer ready */
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#define RCAR_MMC_INFO2_DAT0 BIT(7) /* SDDAT0 */
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#define RCAR_MMC_INFO2_ERR_RTO BIT(6) /* response time out */
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#define RCAR_MMC_INFO2_ERR_ILR BIT(5) /* illegal read err */
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#define RCAR_MMC_INFO2_ERR_ILW BIT(4) /* illegal write err */
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#define RCAR_MMC_INFO2_ERR_TO BIT(3) /* time out error */
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#define RCAR_MMC_INFO2_ERR_END BIT(2) /* END bit error */
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#define RCAR_MMC_INFO2_ERR_CRC BIT(1) /* CRC error */
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#define RCAR_MMC_INFO2_ERR_IDX BIT(0) /* cmd index error */
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#define RCAR_MMC_INFO2_ERRORS \
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(RCAR_MMC_INFO2_ERR_RTO | RCAR_MMC_INFO2_ERR_ILR | \
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RCAR_MMC_INFO2_ERR_ILW | RCAR_MMC_INFO2_ERR_TO | \
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RCAR_MMC_INFO2_ERR_END | RCAR_MMC_INFO2_ERR_CRC | \
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RCAR_MMC_INFO2_ERR_IDX | RCAR_MMC_INFO2_ERR_ILA)
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/*
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* The interrupt mask 1 register is used to enable or disable
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* the RCAR_MMC_INFO1 interrupt.
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*/
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#define RCAR_MMC_INFO1_MASK 0x080
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/*
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* The interrupt mask 2 register is used to enable or disable
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* the RCAR_MMC_INFO2 interrupt.
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*/
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#define RCAR_MMC_INFO2_MASK 0x088
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/*
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* The SD clock control register is used to control
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* the SD clock output and to set the frequency.
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*/
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#define RCAR_MMC_CLKCTL 0x090
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#define RCAR_MMC_CLKCTL_DIV_MASK 0x104ff
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#define RCAR_MMC_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
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#define RCAR_MMC_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
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#define RCAR_MMC_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
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#define RCAR_MMC_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
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#define RCAR_MMC_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
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#define RCAR_MMC_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
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#define RCAR_MMC_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
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#define RCAR_MMC_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
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#define RCAR_MMC_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
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#define RCAR_MMC_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
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#define RCAR_MMC_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
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#define RCAR_MMC_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
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/*
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* The transfer data length register is used to specify
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* the transfer data size.
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*/
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#define RCAR_MMC_SIZE 0x098
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/*
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* The SD card access control option register is used to set
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* the bus width and timeout counter.
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*/
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#define RCAR_MMC_OPTION 0x0A0
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#define RCAR_MMC_OPTION_WIDTH_MASK (5 << 13)
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#define RCAR_MMC_OPTION_WIDTH_1 (4 << 13)
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#define RCAR_MMC_OPTION_WIDTH_4 (0 << 13)
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#define RCAR_MMC_OPTION_WIDTH_8 (1 << 13)
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/*
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* The SD error status register 1 indicates the CRC status, CRC error,
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* End error, and CMD error.
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*/
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#define RCAR_MMC_ERR_STS1 0x0B0
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/* The SD error status register 2 indicates the timeout state. */
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#define RCAR_MMC_ERR_STS2 0x0B8
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/* SD Buffer Read/Write Register */
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#define RCAR_MMC_BUF0 0x0C0
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/* The DMA mode enable register enables the DMA transfer. */
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#define RCAR_MMC_EXTMODE 0x360
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#define RCAR_MMC_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
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/* The software reset register sets a software reset. */
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#define RCAR_MMC_SOFT_RST 0x380
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#define RCAR_MMC_SOFT_RST_RSTX BIT(0) /* reset deassert */
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/* The version register indicates the version of the SD host interface. */
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#define RCAR_MMC_VERSION 0x388
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#define RCAR_MMC_VERSION_IP 0xff /* IP version */
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/*
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* The host interface mode setting register selects the width for access to
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* the data bus.
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*/
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#define RCAR_MMC_HOST_MODE 0x390
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/* The SD interface mode setting register specifies HS400 mode. */
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#define RCAR_MMC_IF_MODE 0x398
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#define RCAR_MMC_IF_MODE_DDR BIT(0) /* DDR mode */
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/* Set of DMAC registers */
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#define RCAR_MMC_DMA_MODE 0x820
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#define RCAR_MMC_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
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#define RCAR_MMC_DMA_MODE_WIDTH (BIT(4) | BIT(5))
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#define RCAR_MMC_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
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#define RCAR_MMC_DMA_CTL 0x828
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#define RCAR_MMC_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
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#define RCAR_MMC_DMA_RST 0x830
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#define RCAR_MMC_DMA_RST_DTRAN0 BIT(8)
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#define RCAR_MMC_DMA_RST_DTRAN1 BIT(9)
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#define RCAR_MMC_DMA_INFO1 0x840
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#define RCAR_MMC_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
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#define RCAR_MMC_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
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#define RCAR_MMC_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
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#define RCAR_MMC_DMA_INFO1_MASK 0x848
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#define RCAR_MMC_DMA_INFO2 0x850
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#define RCAR_MMC_DMA_INFO2_ERR_RD BIT(17)
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#define RCAR_MMC_DMA_INFO2_ERR_WR BIT(16)
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#define RCAR_MMC_DMA_INFO2_MASK 0x858
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#define RCAR_MMC_DMA_ADDR_L 0x880
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#define RCAR_MMC_DMA_ADDR_H 0x888
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/* set of SCC registers */
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/* Initial setting register */
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#define RENESAS_SDHI_SCC_DTCNTL 0x1000
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#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
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/* Sampling clock position setting register */
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#define RENESAS_SDHI_SCC_TAPSET 0x1008
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#define RENESAS_SDHI_SCC_DT2FF 0x1010
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/* Sampling Clock Selection Register */
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#define RENESAS_SDHI_SCC_CKSEL 0x1018
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#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
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/* Sampling Clock Position Correction Register */
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#define RENESAS_SDHI_SCC_RVSCNTL 0x1020
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#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
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/* Sampling Clock Position Correction Request Register */
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#define RENESAS_SDHI_SCC_RVSREQ 0x1028
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#define RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0)
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#define RENESAS_SDHI_SCC_RVSREQ_REQTAPUP BIT(1)
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#define RENESAS_SDHI_SCC_RVSREQ_REQTAP_MASK \
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(RENESAS_SDHI_SCC_RVSREQ_REQTAPDOWN | RENESAS_SDHI_SCC_RVSREQ_REQTAPUP)
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#define RENESAS_SDHI_SCC_RVSREQ_ERR BIT(2)
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/* Sampling data comparison register */
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#define RENESAS_SDHI_SCC_SMPCMP 0x1030
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/* Hardware Adjustment Register 2, used for configuration HS400 mode */
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#define RENESAS_SDHI_SCC_TMPPORT2 0x1038
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#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
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#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
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#endif /* __RCAR_MMC_REGISTERS_H__ */
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@ -28,6 +28,26 @@
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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};
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reg_3p3v: regulator_3p3v {
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compatible = "regulator-fixed";
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regulator-name = "reg_3p3v";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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status = "okay";
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};
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reg_1p8v: regulator_1p8v {
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compatible = "regulator-fixed";
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regulator-name = "reg_1p8v";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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status = "okay";
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};
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gic: interrupt-controller@f1010000 {
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compatible = "arm,gic-400", "arm,gic-v2", "arm,gic" ;
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#interrupt-cells = <4>;
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@ -53,13 +73,36 @@
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#reset-cells = <1>;
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};
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gpio5: gpio@e6055000 {
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compatible = "renesas,rcar-gpio";
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reg = <0 0xe6055000 0 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg CPG_MOD 907>;
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status = "disabled";
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};
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sd0: mmc@ee100000 {
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compatible = "renesas,rcar-mmc";
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reg = <0 0xee100000 0 0x2000>;
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interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>;
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max-bus-freq = <200000000>;
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status = "disabled";
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};
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emmc2: mmc@ee140000 {
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compatible = "renesas,rcar-mmc";
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reg = <0 0xee140000 0 0x2000>;
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vmmc-supply = <®_3p3v>;
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vqmmc-supply = <®_1p8v>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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clocks = <&cpg CPG_MOD 312>;
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max-frequency = <200000000>;
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clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>;
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max-bus-freq = <200000000>;
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status = "disabled";
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};
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63
dts/bindings/mmc/renesas,rcar-emmc.yaml
Normal file
63
dts/bindings/mmc/renesas,rcar-emmc.yaml
Normal file
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@ -0,0 +1,63 @@
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description: Renesas R-Car eMMC
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compatible: "renesas,rcar-mmc"
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|
||||
include: [sdhc.yaml, mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
|
||||
|
||||
properties:
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
reg:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
|
||||
max-bus-freq:
|
||||
required: true
|
||||
|
||||
non-removable:
|
||||
type: boolean
|
||||
description: |
|
||||
Non-removable slots (like eMMC), which are assumed to always be present,
|
||||
will affect the `sdhc_card_present` call. This call will always return
|
||||
true if this property exists for the node.
|
||||
|
||||
mmc-sdr104-support:
|
||||
type: boolean
|
||||
|
||||
cd-gpios:
|
||||
type: phandle-array
|
||||
description: Card Detect pin
|
||||
|
||||
pwr-gpios:
|
||||
type: phandle-array
|
||||
description: Power pin
|
||||
|
||||
vmmc-supply:
|
||||
type: phandle
|
||||
description: |
|
||||
Supply for the card power
|
||||
|
||||
vqmmc-supply:
|
||||
type: phandle
|
||||
description: |
|
||||
Supply for the bus IO line power, such as a level shifter.
|
||||
If the level shifter is controlled by a GPIO line, this shall
|
||||
be modeled as a "regulator-fixed" with a GPIO line for
|
||||
switching the level shifter on/off.
|
||||
|
||||
bus-width:
|
||||
type: int
|
||||
default: 1
|
||||
description: |
|
||||
Bus width for SDMMC access, defaults to the minimum necessary
|
||||
number of bus lines
|
||||
enum:
|
||||
- 1
|
||||
- 4
|
||||
- 8
|
||||
Loading…
Reference in a new issue