drivers: cc13xx_cc26xx: pwm: introduce pwm driver
This change introduces a new PWM driver for all CC13/26xx SoC. See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed usage instructions. Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
This commit is contained in:
Florian Grandel
Fabio Baltieri
parent
f997dc3842
commit
b954ce4903
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@ -5,6 +5,7 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/pwm.h)
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_PWM_TELINK_B91 pwm_b91.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_CC13XX_CC26XX_TIMER pwm_cc13xx_cc26xx_timer.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_STM32 pwm_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_SIFIVE pwm_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PWM_NRF5_SW pwm_nrf5_sw.c)
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@ -35,6 +35,8 @@ config PWM_CAPTURE
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source "drivers/pwm/Kconfig.b91"
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source "drivers/pwm/Kconfig.cc13xx_cc26xx_timer"
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source "drivers/pwm/Kconfig.stm32"
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source "drivers/pwm/Kconfig.sifive"
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9
drivers/pwm/Kconfig.cc13xx_cc26xx_timer
Normal file
9
drivers/pwm/Kconfig.cc13xx_cc26xx_timer
Normal file
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@ -0,0 +1,9 @@
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# Copyright (c) 2023 Zephyr Project
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# SPDX-License-Identifier: Apache-2.0
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config PWM_CC13XX_CC26XX_TIMER
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bool "TI SimpleLink CC13xx/CC26xx GPT timer PWM driver"
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default y
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depends on DT_HAS_TI_CC13XX_CC26XX_TIMER_PWM_ENABLED
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help
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Enables TI SimpleLink CC13xx/CC26xx GPT timer PWM driver.
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241
drivers/pwm/pwm_cc13xx_cc26xx_timer.c
Normal file
241
drivers/pwm/pwm_cc13xx_cc26xx_timer.c
Normal file
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@ -0,0 +1,241 @@
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/*
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* Copyright (c) 2023 Zephyr Project
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc13xx_cc26xx_timer_pwm
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/drivers/pwm.h>
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#include <driverlib/gpio.h>
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#include <driverlib/prcm.h>
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#include <driverlib/timer.h>
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#include <inc/hw_memmap.h>
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#include <inc/hw_types.h>
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#include <ti/drivers/Power.h>
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#include <ti/drivers/power/PowerCC26XX.h>
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#include <zephyr/logging/log.h>
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#define LOG_MODULE_NAME pwm_cc13xx_cc26xx_timer
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LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
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/* TODO: Clock frequency can be settable via KConfig, see TOP:PRCM:GPTCLKDIV */
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#define CPU_FREQ ((uint32_t)DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency))
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/* GPT peripherals in 16 bit mode have maximum 24 counter bits incl. the
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* prescaler. Count is set to (2^24 - 2) to allow for a glitch free 100% duty
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* cycle at max. period count.
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*/
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#define PWM_COUNT_MAX 0xFFFFFE
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#define PWM_INITIAL_PERIOD PWM_COUNT_MAX
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#define PWM_INITIAL_DUTY 0U /* initially off */
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struct pwm_cc13xx_cc26xx_data {
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};
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struct pwm_cc13xx_cc26xx_config {
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const uint32_t gpt_base; /* GPT register base address */
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const struct pinctrl_dev_config *pcfg;
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LOG_INSTANCE_PTR_DECLARE(log);
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};
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static void write_value(const struct pwm_cc13xx_cc26xx_config *config, uint32_t value,
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uint32_t prescale_register, uint32_t value_register)
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{
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/* Upper byte represents the prescaler value. */
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uint8_t prescaleValue = 0xff & (value >> 16);
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HWREG(config->gpt_base + prescale_register) = prescaleValue;
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/* The remaining bytes represent the load / match value. */
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HWREG(config->gpt_base + value_register) = value & 0xffff;
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}
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static int set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config *config, uint32_t period,
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uint32_t pulse)
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{
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uint32_t match_value = pulse;
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if (pulse == 0U) {
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TimerDisable(config->gpt_base, TIMER_B);
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#ifdef CONFIG_PM
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Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY);
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#endif
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match_value = period + 1;
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}
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/* Fail if period is out of range */
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if ((period > PWM_COUNT_MAX) || (period == 0)) {
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LOG_ERR("Period (%d) is out of range.", period);
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return -EINVAL;
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}
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/* Compare to new period and fail if invalid */
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if (period < (match_value - 1) || (match_value < 0)) {
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LOG_ERR("Period (%d) is shorter than pulse (%d).", period, pulse);
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return -EINVAL;
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}
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/* Store new period and update timer */
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write_value(config, period, GPT_O_TBPR, GPT_O_TBILR);
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write_value(config, match_value, GPT_O_TBPMR, GPT_O_TBMATCHR);
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if (pulse > 0U) {
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#ifdef CONFIG_PM
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Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY);
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#endif
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TimerEnable(config->gpt_base, TIMER_B);
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}
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LOG_DBG("Period and pulse successfully set.");
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return 0;
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}
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static int set_cycles(const struct device *dev, uint32_t channel, uint32_t period, uint32_t pulse,
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pwm_flags_t flags)
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{
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const struct pwm_cc13xx_cc26xx_config *config = dev->config;
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if (channel != 0) {
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return -EIO;
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}
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set_period_and_pulse(config, period, pulse);
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return 0;
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}
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static int get_cycles_per_sec(const struct device *dev, uint32_t channel, uint64_t *cycles)
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{
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if (channel > 0) {
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return -EIO;
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}
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if (cycles) {
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*cycles = CPU_FREQ;
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}
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return 0;
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}
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static const struct pwm_driver_api pwm_driver_api = {
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.set_cycles = set_cycles,
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.get_cycles_per_sec = get_cycles_per_sec,
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};
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#ifdef CONFIG_PM
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static int get_timer_inst_number(const struct pwm_cc13xx_cc26xx_config *config)
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{
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switch (config->gpt_base) {
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case GPT0_BASE:
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return 0;
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case GPT1_BASE:
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return 1;
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case GPT2_BASE:
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return 2;
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case GPT3_BASE:
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return 3;
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default:
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__ASSERT_UNREACHABLE;
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}
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}
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#else
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static int get_timer_peripheral(const struct pwm_cc13xx_cc26xx_config *config)
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{
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switch (config->gpt_base) {
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case GPT0_BASE:
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return PRCM_PERIPH_TIMER0;
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case GPT1_BASE:
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return PRCM_PERIPH_TIMER1;
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case GPT2_BASE:
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return PRCM_PERIPH_TIMER2;
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case GPT3_BASE:
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return PRCM_PERIPH_TIMER3;
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default:
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__ASSERT_UNREACHABLE;
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}
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}
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#endif /* CONFIG_PM */
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static int init_pwm(const struct device *dev)
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{
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const struct pwm_cc13xx_cc26xx_config *config = dev->config;
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pinctrl_soc_pin_t pin = config->pcfg->states[0].pins[0];
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int ret;
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#ifdef CONFIG_PM
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/* Set dependency on gpio resource to turn on power domains */
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Power_setDependency(get_timer_inst_number(config));
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#else
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/* Enable peripheral power domain. */
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PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
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/* Enable GPIO peripheral. */
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PRCMPeripheralRunEnable(get_timer_peripheral(config));
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/* Load PRCM settings. */
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PRCMLoadSet();
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while (!PRCMLoadGet()) {
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continue;
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}
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#endif /* CONFIG_PM */
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("failed to setup PWM pinctrl");
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return ret;
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}
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/* Configures the PWM idle output level.
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*
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* TODO: Make PWM idle high/low configurable via custom DT PWM flag.
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*/
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GPIO_writeDio(pin.pin, 0);
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GPIO_setOutputEnableDio(pin.pin, GPIO_OUTPUT_ENABLE);
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/* Peripheral should not be accessed until power domain is on. */
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while (PRCMPowerDomainsAllOn(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON) {
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continue;
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}
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TimerDisable(config->gpt_base, TIMER_B);
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HWREG(config->gpt_base + GPT_O_CFG) = GPT_CFG_CFG_16BIT_TIMER;
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/* Stall timer when debugging.
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*
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* TODO: Make debug stall configurable via custom DT prop.
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*/
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HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBSTALL;
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/* TODO: Make PWM polarity configurable via DT PWM flag. */
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HWREG(config->gpt_base + GPT_O_TBMR) = GPT_TBMR_TBAMS_PWM | GPT_TBMR_TBMRSU_TOUPDATE |
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GPT_TBMR_TBPWMIE_EN | GPT_TBMR_TBMR_PERIODIC;
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set_period_and_pulse(config, PWM_INITIAL_PERIOD, PWM_INITIAL_DUTY);
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return 0;
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}
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#define DT_TIMER(idx) DT_INST_PARENT(idx)
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#define DT_TIMER_BASE_ADDR(idx) (DT_REG_ADDR(DT_TIMER(idx)))
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#define PWM_DEVICE_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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LOG_INSTANCE_REGISTER(LOG_MODULE_NAME, idx, CONFIG_PWM_LOG_LEVEL); \
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static const struct pwm_cc13xx_cc26xx_config pwm_cc13xx_cc26xx_##idx##_config = { \
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.gpt_base = DT_TIMER_BASE_ADDR(idx), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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LOG_INSTANCE_PTR_INIT(log, LOG_MODULE_NAME, idx)}; \
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\
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static struct pwm_cc13xx_cc26xx_data pwm_cc13xx_cc26xx_##idx##_data; \
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\
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DEVICE_DT_INST_DEFINE(idx, init_pwm, NULL, &pwm_cc13xx_cc26xx_##idx##_data, \
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&pwm_cc13xx_cc26xx_##idx##_config, POST_KERNEL, \
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CONFIG_PWM_INIT_PRIORITY, &pwm_driver_api)
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DT_INST_FOREACH_STATUS_OKAY(PWM_DEVICE_INIT);
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@ -8,6 +8,7 @@
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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chosen {
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@ -95,6 +96,62 @@
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};
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};
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gpt0: timer@40010000 {
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compatible = "ti,cc13xx-cc26xx-timer";
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reg = <0x40010000 0x1000>;
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interrupts = <15 0 16 0>;
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interrupt-names = "gpt0a", "gpt0b";
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status = "disabled";
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pwm0: pwm {
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compatible = "ti,cc13xx-cc26xx-timer-pwm";
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#pwm-cells = <1>;
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status = "disabled";
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};
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};
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gpt1: timer@40011000 {
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compatible = "ti,cc13xx-cc26xx-timer";
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reg = <0x40011000 0x1000>;
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interrupts = <17 0 18 0>;
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interrupt-names = "gpt1a", "gpt1b";
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status = "disabled";
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pwm1: pwm {
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compatible = "ti,cc13xx-cc26xx-timer-pwm";
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#pwm-cells = <1>;
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status = "disabled";
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};
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};
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gpt2: timer@40012000 {
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compatible = "ti,cc13xx-cc26xx-timer";
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reg = <0x40012000 0x1000>;
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interrupts = <19 0 20 0>;
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interrupt-names = "gpt2a", "gpt2b";
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status = "disabled";
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pwm2: pwm {
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compatible = "ti,cc13xx-cc26xx-timer-pwm";
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#pwm-cells = <1>;
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status = "disabled";
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};
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};
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gpt3: timer@40013000 {
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compatible = "ti,cc13xx-cc26xx-timer";
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reg = <0x40013000 0x1000>;
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interrupts = <21 0 22 0>;
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interrupt-names = "gpt3a", "gpt3b";
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status = "disabled";
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pwm3: pwm {
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compatible = "ti,cc13xx-cc26xx-timer-pwm";
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#pwm-cells = <1>;
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status = "disabled";
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};
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};
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uart0: uart@40001000 {
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compatible = "ti,cc13xx-cc26xx-uart";
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reg = <0x40001000 0x1000>;
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72
dts/bindings/pwm/ti,cc13xx-cc26xx-timer-pwm.yaml
Normal file
72
dts/bindings/pwm/ti,cc13xx-cc26xx-timer-pwm.yaml
Normal file
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@ -0,0 +1,72 @@
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# Copyright (c) 2023, Zephyr Project
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI SimpleLink CC13xx/CC26xx GPT timer PWM Controller Node
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To configure a PWM node, you first need to define a board overlay with a
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pinctrl configuration for the pin on which the PWM signal should be present:
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&pinctrl {
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gpt0_pwm: gpt0_pwm {
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pinmux = <25 IOC_PORT_MCU_PORT_EVENT1>;
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bias-disable;
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drive-strength = <8>; /* in mA, can be 2, 4 or 8 */
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};
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};
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Please be aware that the port event depends on the GPT instance chosen. The
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following port events must be used for PWM:
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- GPT0: IOC_PORT_MCU_PORT_EVENT1
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- GPT1: IOC_PORT_MCU_PORT_EVENT3
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- GPT2: IOC_PORT_MCU_PORT_EVENT5
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- GPT3: IOC_PORT_MCU_PORT_EVENT7
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Be careful not to choose a pin that is already in use on your board, this
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might irreversible damage to your board as the given pin will be configured as
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output and actively driven by the PWM driver.
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Then enable the corresponding timer and PWM nodes and add a reference to the
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pinctrl entry:
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&gpt0 {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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pinctrl-0 = <&gpt0_pwm>;
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pinctrl-names = "default";
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};
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Now you can programmatically enable the PWM signal in your code:
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static const struct device *pwm = DEVICE_DT_GET(DT_NODELABEL(pwm0));
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int init_pwm(void)
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{
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uint32_t pwm_period_ns, pwm_pulse_ns;
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uint32_t pwm_duty_percent = 50U;
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uint32_t pwm_frequency = 1000U; /* 1kHz */
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if (!device_is_ready(pwm)) {
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LOG_ERR("Error: PWM device %s is not ready\n", pwm->name);
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return -ENODEV;
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}
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pwm_period_ns = NSEC_PER_SEC / pwm_frequency;
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pwm_pulse_ns = (pwm_duty_percent * pwm_period_ns) / 100;
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return pwm_set(pwm, 0, pwm_period_ns, pwm_pulse_ns, 0);
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}
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compatible: "ti,cc13xx-cc26xx-timer-pwm"
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include: [base.yaml, pwm-controller.yaml, pinctrl-device.yaml]
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properties:
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pinctrl-0:
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required: true
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pwm-cells:
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- period
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15
dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml
Normal file
15
dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml
Normal file
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@ -0,0 +1,15 @@
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# Copyright (c) 2023 Zephyr Project
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# SPDX-License-Identifier: Apache-2.0
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description: TI SimpleLink CC13xx/CC26xx Timer Node
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compatible: "ti,cc13xx-cc26xx-timer"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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@ -4,6 +4,9 @@ common:
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- drivers
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- pwm
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tests:
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drivers.pwm.cc13xx_cc26xx_timer.build:
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platform_allow: cc1352p1_launchxl
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tags: pwm_cc13xx_cc26xx_timer
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drivers.pwm.gecko.build:
|
||||
platform_allow: efr32_radio_brd4250b
|
||||
tags: pwm_gecko
|
||||
|
|
|
|||
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Reference in a new issue