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dts: mimx93_evk_a55: avoid conflict with Ethos-U NPU reserved memory

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The DRAM range 0xc0000000~0xcfffffff is reserved for the Ethos-U NPU,
so change the RAM base to 0xd0000000.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This commit is contained in:
Hou Zhiqiang 2024-01-18 16:50:25 +08:00 committed by Henrik Brix Andersen
parent 92a24ba4b4
commit b985442829
2 changed files with 5 additions and 5 deletions
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4
boards/arm64/mimx93_evk/doc/index.rst
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@ -86,14 +86,14 @@ Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
.. code-block:: console
fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xc0000000
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000
Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
.. code-block:: console
fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000
Use this configuration to run basic Zephyr applications and kernel tests,

6
boards/arm64/mimx93_evk/mimx93_evk_a55.dts
View file

@ -1,5 +1,5 @@
/*
* Copyright 2022 NXP
* Copyright 2022,2024 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -25,8 +25,8 @@
};
};
sram0: memory@c0000000 {
reg = <0xc0000000 DT_SIZE_M(1)>;
sram0: memory@d0000000 {
reg = <0xd0000000 DT_SIZE_M(1)>;
};
aliases {