drivers/gpio: stm32: Use gpio device as gpio_stm32_configure arg
Now that pinmux driver holds a table of GPIO device pointers, use gpio device as the single source of trust for gpio_base and remove use of port_base and related code. This way, gpio_stm32_configure could directly take gpio device pointer as argument. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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@ -112,9 +112,10 @@ static inline uint32_t stm32_pinval_get(int pin)
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/**
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* @brief Configure the hardware.
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*/
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int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf)
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int gpio_stm32_configure(const struct device *dev, int pin, int conf, int altf)
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{
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GPIO_TypeDef *gpio = (GPIO_TypeDef *)base_addr;
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const struct gpio_stm32_config *cfg = dev->config;
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GPIO_TypeDef *gpio = (GPIO_TypeDef *)cfg->base;
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int pin_ll = stm32_pinval_get(pin);
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@ -457,7 +458,6 @@ static int gpio_stm32_port_toggle_bits(const struct device *dev,
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static int gpio_stm32_config(const struct device *dev,
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gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_stm32_config *cfg = dev->config;
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int err = 0;
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int pincfg;
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@ -477,7 +477,7 @@ static int gpio_stm32_config(const struct device *dev,
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}
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}
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gpio_stm32_configure(cfg->base, pin, pincfg, 0);
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gpio_stm32_configure(dev, pin, pincfg, 0);
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exit:
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return err;
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@ -233,12 +233,12 @@ struct gpio_stm32_data {
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/**
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* @brief helper for configuration of GPIO pin
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*
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* @param base_addr GPIO port base address
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* @param dev GPIO port device pointer
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* @param pin IO pin
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* @param func GPIO mode
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* @param conf GPIO mode
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* @param altf Alternate function
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*/
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int gpio_stm32_configure(uint32_t *base_addr, int pin, int conf, int altf);
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int gpio_stm32_configure(const struct device *dev, int pin, int conf, int altf);
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/**
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* @brief Enable / disable GPIO port clock.
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2021 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -7,8 +8,7 @@
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/**
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* @brief
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*
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* A common driver for STM32 pinmux. Each SoC must implement a SoC
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* specific part of the driver.
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* A common driver for STM32 pinmux.
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*/
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#include <errno.h>
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@ -23,14 +23,6 @@
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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#ifdef CONFIG_SOC_SERIES_STM32MP1X
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#define GPIO_REG_SIZE 0x1000
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/* 0x1000 between each port, 0x400 gpio registry 0xC00 reserved */
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#else
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#define GPIO_REG_SIZE 0x400
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#endif /* CONFIG_SOC_SERIES_STM32MP1X */
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/* base address for where GPIO registers start */
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#define GPIO_PORTS_BASE (GPIOA_BASE)
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#define GPIO_DEVICE(gpio_port) \
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COND_CODE_1(DT_NODE_HAS_STATUS(DT_NODELABEL(gpio_port), okay), \
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(DEVICE_DT_GET(DT_NODELABEL(gpio_port))), \
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@ -52,15 +44,16 @@ const struct device * const gpio_ports[STM32_PORTS_MAX] = {
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static int stm32_pin_configure(uint32_t pin, uint32_t func, uint32_t altf)
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{
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/* determine IO port registers location */
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uint32_t offset = STM32_PORT(pin) * GPIO_REG_SIZE;
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uint8_t *port_base = (uint8_t *)(GPIO_PORTS_BASE + offset);
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const struct device *port_device = gpio_ports[STM32_PORT(pin)];
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/* not much here, on STM32F10x the alternate function is
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* controller by setting up GPIO pins in specific mode.
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*/
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return gpio_stm32_configure((uint32_t *)port_base,
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STM32_PIN(pin), func, altf);
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if (port_device == NULL) {
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return -ENODEV;
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}
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return gpio_stm32_configure(port_device, STM32_PIN(pin), func, altf);
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}
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/**
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