drivers: i2c: Introduce SAM4L i2c TWIM driver
The SAM4L have a unique I2C driver. It shares simultaneously pins for both master and slave controllers. Each controller have their own instance. This introduces the TWIM controller that handles only the master part. The TWIM controller uses no copy and the driver was prepared to work with both 7 and 10 bits address. The controller can handler up to 256 bytes for a single transfer allowing long data communication with almost no CPU intervention. The driver was wrote specifically to Zephyr. It receives a transfer list of from upper layers to a specific device on the bus. It programs the first and second transfer, if it exists, before start. At end of full read/write interrupt, will program the next data block. This process repeats until all transfers be executed. The driver uses interrupt from TWIM to check for erros or program next tranfer. Future work can enable low power mode on the driver allowing long transfers with low power consumption. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke
Kumar Gala
parent
2d3ef0c902
commit
bc00f19724
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@ -153,6 +153,7 @@
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/doc/reference/networking/can* @alexanderwachter
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/doc/reference/networking/can* @alexanderwachter
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/doc/security/ @ceolin @d3zd3z
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/doc/security/ @ceolin @d3zd3z
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/drivers/debug/ @nashif
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/drivers/debug/ @nashif
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/drivers/*/*sam4l* @nandojve
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/drivers/*/*cc13xx_cc26xx* @bwitherspoon
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/drivers/*/*cc13xx_cc26xx* @bwitherspoon
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/drivers/*/*mcux* @MaureenHelm
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/drivers/*/*mcux* @MaureenHelm
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/drivers/*/*stm32* @erwango @ABOSTM @FRASTM
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/drivers/*/*stm32* @erwango @ABOSTM @FRASTM
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@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_NRFX_TWI i2c_nrfx_twi.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_TWIM i2c_nrfx_twim.c)
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zephyr_library_sources_ifdef(CONFIG_NRFX_TWIM i2c_nrfx_twim.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWI i2c_sam_twi.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWI i2c_sam_twi.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIHS i2c_sam_twihs.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIHS i2c_sam_twihs.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWIM i2c_sam4l_twim.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SBCON i2c_sbcon.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SBCON i2c_sbcon.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SIFIVE i2c_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_SIFIVE i2c_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_NIOS2 i2c_nios2.c)
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zephyr_library_sources_ifdef(CONFIG_I2C_NIOS2 i2c_nios2.c)
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@ -63,6 +63,12 @@ config I2C_SAM_TWIHS
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help
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help
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Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.
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Enable Atmel SAM MCU Family (TWIHS) I2C bus driver.
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config I2C_SAM_TWIM
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bool "Atmel SAM (TWIM) I2C driver"
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depends on SOC_SERIES_SAM4L
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help
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Enable Atmel SAM MCU Family (TWIM) I2C bus driver.
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config I2C_SAM_TWI
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config I2C_SAM_TWI
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bool "Atmel SAM (TWI) I2C driver"
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bool "Atmel SAM (TWI) I2C driver"
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depends on SOC_FAMILY_SAM
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depends on SOC_FAMILY_SAM
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642
drivers/i2c/i2c_sam4l_twim.c
Normal file
642
drivers/i2c/i2c_sam4l_twim.c
Normal file
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@ -0,0 +1,642 @@
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/*
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* Copyright (c) 2017 Piotr Mienkowski
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* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam_i2c_twim
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/** @file
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* @brief I2C bus (TWIM) driver for Atmel SAM4L MCU family.
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*
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* I2C Master Mode with 7/10 bit addressing is currently supported.
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* Very long transfers are allowed using NCMDR register. DMA is not
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* yet supported.
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*/
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#include <errno.h>
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#include <sys/__assert.h>
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <drivers/i2c.h>
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#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_sam_twim);
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#include "i2c-priv.h"
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/** I2C bus speed [Hz] in Standard Mode */
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#define BUS_SPEED_STANDARD_HZ 100000U
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/** I2C bus speed [Hz] in Fast Mode */
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#define BUS_SPEED_FAST_HZ 400000U
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/** I2C bus speed [Hz] in Fast Plus Mode */
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#define BUS_SPEED_PLUS_HZ 1000000U
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/** I2C bus speed [Hz] in High Speed Mode */
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#define BUS_SPEED_HIGH_HZ 3400000U
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/* Maximum value of Clock Divider (CKDIV) */
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#define CKDIV_MAX 7
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/* Maximum Frequency prescaled */
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#define F_PRESCALED_MAX 255
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/** Status Clear Register Mask for No Acknowledgements */
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#define TWIM_SCR_NAK_MASK (TWIM_SCR_ANAK | TWIM_SCR_DNAK)
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/** Status Register Mask for No Acknowledgements */
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#define TWIM_SR_NAK_MASK (TWIM_SR_ANAK | TWIM_SR_DNAK)
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/** Interrupt Enable Register Mask for No Acknowledgements */
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#define TWIM_IER_NAK_MASK (TWIM_IER_ANAK | TWIM_IER_DNAK)
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/** Frequently used Interrupt Enable Register Mask */
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#define TWIM_IER_STD_MASK (TWIM_IER_ANAK | TWIM_IER_ARBLST)
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/** Frequently used Status Clear Register Mask */
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#define TWIM_SR_STD_MASK (TWIM_SR_ANAK | TWIM_SR_ARBLST)
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/** \internal Max value of NBYTES per transfer by hardware */
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#define TWIM_MAX_NBYTES_PER_XFER \
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(TWIM_CMDR_NBYTES_Msk >> TWIM_CMDR_NBYTES_Pos)
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#define TWIM_NCMDR_FREE_WAIT 2000
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/* Device constant configuration parameters */
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struct i2c_sam_twim_dev_cfg {
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Twim *regs;
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void (*irq_config)(void);
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uint32_t bitrate;
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const struct soc_gpio_pin *pin_list;
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uint8_t pin_list_size;
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uint8_t periph_id;
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uint8_t irq_id;
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uint8_t std_clk_slew_lim;
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uint8_t std_clk_strength_low;
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uint8_t std_data_slew_lim;
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uint8_t std_data_strength_low;
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uint8_t hs_clk_slew_lim;
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uint8_t hs_clk_strength_high;
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uint8_t hs_clk_strength_low;
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uint8_t hs_data_slew_lim;
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uint8_t hs_data_strength_low;
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uint8_t hs_master_code;
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};
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/* Device run time data */
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struct i2c_sam_twim_dev_data {
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struct k_mutex bus_mutex;
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struct k_sem sem;
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struct i2c_msg *msgs;
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uint32_t msg_cur_idx;
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uint32_t msg_next_idx;
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uint32_t msg_max_idx;
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uint32_t cur_remaining;
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uint32_t cur_idx;
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uint32_t cur_sr;
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uint32_t next_nb_bytes;
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bool next_is_valid;
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bool next_need_rs;
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bool cur_need_rs;
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};
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#define DEV_NAME(dev) ((dev)->name)
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#define DEV_CFG(dev) \
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((const struct i2c_sam_twim_dev_cfg *const)(dev)->config)
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#define DEV_DATA(dev) \
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((struct i2c_sam_twim_dev_data *const)(dev)->data)
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static int i2c_clk_set(const struct device *dev, uint32_t speed)
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{
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const struct i2c_sam_twim_dev_cfg *const cfg = DEV_CFG(dev);
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Twim *const twim = cfg->regs;
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uint32_t per_clk = SOC_ATMEL_SAM_MCK_FREQ_HZ;
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uint32_t f_prescaled = (per_clk / speed / 2);
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uint32_t cwgr_reg_val = 0;
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uint8_t cwgr_exp = 0;
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/* f_prescaled must fit in 8 bits, cwgr_exp must fit in 3 bits */
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while ((f_prescaled > F_PRESCALED_MAX) && (cwgr_exp <= CKDIV_MAX)) {
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/* increase clock divider */
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cwgr_exp++;
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/* divide f_prescaled value */
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f_prescaled /= 2;
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}
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if (cwgr_exp > CKDIV_MAX) {
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LOG_ERR("Failed to configure I2C clock");
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return -EIO;
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}
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cwgr_reg_val = TWIM_HSCWGR_LOW(f_prescaled / 2) |
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TWIM_HSCWGR_HIGH(f_prescaled -
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(f_prescaled / 2)) |
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TWIM_HSCWGR_EXP(cwgr_exp) |
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TWIM_HSCWGR_DATA(0) |
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TWIM_HSCWGR_STASTO(f_prescaled);
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/* This configuration should be applied after a TWIM_CR_SWRST
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* Set clock waveform generator register
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*/
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if (speed == BUS_SPEED_HIGH_HZ) {
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twim->HSCWGR = cwgr_reg_val;
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} else {
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twim->CWGR = cwgr_reg_val;
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}
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LOG_DBG("per_clk: %d, f_prescaled: %d, cwgr_exp: 0x%02x,"
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"cwgr_reg_val: 0x%08x", per_clk, f_prescaled,
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cwgr_exp, cwgr_reg_val);
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/* Set clock and data slew rate */
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twim->SRR = ((speed == BUS_SPEED_PLUS_HZ) ? TWIM_SRR_FILTER(2) :
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TWIM_SRR_FILTER(3)) |
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TWIM_SRR_CLSLEW(cfg->std_clk_slew_lim) |
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TWIM_SRR_CLDRIVEL(cfg->std_clk_strength_low) |
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TWIM_SRR_DASLEW(cfg->std_data_slew_lim) |
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TWIM_SRR_DADRIVEL(cfg->std_data_strength_low);
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twim->HSSRR = TWIM_HSSRR_FILTER(1) |
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TWIM_HSSRR_CLSLEW(cfg->hs_clk_slew_lim) |
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TWIM_HSSRR_CLDRIVEH(cfg->hs_clk_strength_high) |
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TWIM_HSSRR_CLDRIVEL(cfg->hs_clk_strength_low) |
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TWIM_HSSRR_DASLEW(cfg->hs_data_slew_lim) |
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TWIM_HSSRR_DADRIVEL(cfg->hs_data_strength_low);
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return 0;
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}
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static int i2c_sam_twim_configure(const struct device *dev, uint32_t config)
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{
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uint32_t bitrate;
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int ret;
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if (!(config & I2C_MODE_MASTER)) {
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LOG_ERR("Master Mode is not enabled");
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return -EIO;
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}
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if (config & I2C_ADDR_10_BITS) {
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LOG_ERR("I2C 10-bit addressing is currently not supported");
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LOG_ERR("Please submit a patch");
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return -EIO;
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}
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/* Configure clock */
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switch (I2C_SPEED_GET(config)) {
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case I2C_SPEED_STANDARD:
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bitrate = BUS_SPEED_STANDARD_HZ;
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break;
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case I2C_SPEED_FAST:
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bitrate = BUS_SPEED_FAST_HZ;
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break;
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case I2C_SPEED_FAST_PLUS:
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bitrate = BUS_SPEED_PLUS_HZ;
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break;
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case I2C_SPEED_HIGH:
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bitrate = BUS_SPEED_HIGH_HZ;
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break;
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default:
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LOG_ERR("Unsupported I2C speed value");
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return -EIO;
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}
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/* Setup clock waveform */
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ret = i2c_clk_set(dev, bitrate);
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if (ret < 0) {
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return ret;
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}
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return 0;
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}
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static void i2c_prepare_xfer_data(struct i2c_sam_twim_dev_data *data)
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{
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struct i2c_msg *next_msg = NULL;
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if (data->next_nb_bytes > TWIM_MAX_NBYTES_PER_XFER) {
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data->cur_remaining = TWIM_MAX_NBYTES_PER_XFER;
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data->next_nb_bytes -= TWIM_MAX_NBYTES_PER_XFER;
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data->next_is_valid = true;
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data->next_need_rs = false;
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} else {
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data->cur_remaining = data->next_nb_bytes;
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if ((data->msg_next_idx + 1) < data->msg_max_idx) {
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next_msg = &data->msgs[++data->msg_next_idx];
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data->next_nb_bytes = next_msg->len;
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data->next_is_valid = true;
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data->next_need_rs = true;
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} else {
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data->next_nb_bytes = 0;
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data->next_is_valid = false;
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data->next_need_rs = false;
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}
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}
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}
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static uint32_t i2c_prepare_xfer_cmd(struct i2c_sam_twim_dev_data *data,
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uint32_t *cmdr_reg,
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uint32_t next_msg_idx)
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{
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struct i2c_msg *next_msg = &data->msgs[next_msg_idx];
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bool next_msg_is_read;
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uint32_t next_nb_remaining;
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*cmdr_reg &= ~(TWIM_CMDR_NBYTES_Msk |
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TWIM_CMDR_ACKLAST |
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TWIM_CMDR_START |
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TWIM_CMDR_READ);
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next_msg_is_read = ((next_msg->flags & I2C_MSG_RW_MASK) ==
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I2C_MSG_READ);
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if (next_msg_is_read) {
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*cmdr_reg |= TWIM_CMDR_READ;
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}
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if (data->next_need_rs) {
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/* TODO: evaluate 10 bits repeat start read
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* because of blank cmd
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*/
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*cmdr_reg |= TWIM_CMDR_START;
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}
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if (data->next_nb_bytes > TWIM_MAX_NBYTES_PER_XFER) {
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next_nb_remaining = TWIM_MAX_NBYTES_PER_XFER;
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if (next_msg_is_read) {
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*cmdr_reg |= TWIM_CMDR_ACKLAST;
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}
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} else {
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next_nb_remaining = data->next_nb_bytes;
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/* Is there any more messages ? */
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if ((next_msg_idx + 1) >= data->msg_max_idx) {
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*cmdr_reg |= TWIM_CMDR_STOP;
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}
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}
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return next_nb_remaining;
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}
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static void i2c_start_xfer(const struct device *dev, uint16_t daddr)
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{
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const struct i2c_sam_twim_dev_cfg *const cfg = DEV_CFG(dev);
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struct i2c_sam_twim_dev_data *data = DEV_DATA(dev);
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struct i2c_msg *msg = &data->msgs[0];
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||||||
|
Twim *const twim = cfg->regs;
|
||||||
|
uint32_t cmdr_reg;
|
||||||
|
uint32_t data_size;
|
||||||
|
uint32_t cur_is_read;
|
||||||
|
|
||||||
|
/* Reset the TWIM module */
|
||||||
|
twim->CR = TWIM_CR_MEN;
|
||||||
|
twim->CR = TWIM_CR_SWRST;
|
||||||
|
twim->CR = TWIM_CR_MDIS;
|
||||||
|
twim->IDR = ~0UL; /* Clear the interrupt flags */
|
||||||
|
twim->SCR = ~0UL; /* Clear the status flags */
|
||||||
|
|
||||||
|
/* Reset indexes */
|
||||||
|
data->msg_cur_idx = 0;
|
||||||
|
data->msg_next_idx = 0;
|
||||||
|
|
||||||
|
/* pre-load current message to infer next */
|
||||||
|
data->next_nb_bytes = data->msgs[data->msg_next_idx].len;
|
||||||
|
data->next_is_valid = false;
|
||||||
|
data->next_need_rs = false;
|
||||||
|
data->cur_remaining = 0;
|
||||||
|
data->cur_idx = 0;
|
||||||
|
|
||||||
|
LOG_DBG("Config first/next Transfer: msgs: %d", data->msg_max_idx);
|
||||||
|
|
||||||
|
cmdr_reg = TWIM_CMDR_SADR(daddr) |
|
||||||
|
TWIM_CMDR_VALID;
|
||||||
|
|
||||||
|
if (I2C_SPEED_GET(msg->flags) >= I2C_SPEED_HIGH) {
|
||||||
|
cmdr_reg |= TWIM_CMDR_HS |
|
||||||
|
TWIM_CMDR_HSMCODE(cfg->hs_master_code);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (msg->flags & I2C_MSG_ADDR_10_BITS) {
|
||||||
|
cmdr_reg |= TWIM_CMDR_TENBIT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ &&
|
||||||
|
(msg->flags & I2C_MSG_ADDR_10_BITS)) {
|
||||||
|
|
||||||
|
/* Fill transfer command (empty)
|
||||||
|
* It must be a write xfer with NBYTES = 0
|
||||||
|
*/
|
||||||
|
twim->CMDR = cmdr_reg | TWIM_CMDR_START;
|
||||||
|
|
||||||
|
/* Fill next transfer command. REPSAME performs a repeated
|
||||||
|
* start to the same slave address as addressed in the
|
||||||
|
* previous transfer in order to enter master receiver mode.
|
||||||
|
*/
|
||||||
|
cmdr_reg |= TWIM_CMDR_REPSAME;
|
||||||
|
|
||||||
|
i2c_prepare_xfer_data(data);
|
||||||
|
|
||||||
|
/* Special condition: reset msg_next_idx */
|
||||||
|
data->msg_next_idx = 0;
|
||||||
|
|
||||||
|
data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, 0);
|
||||||
|
cmdr_reg |= TWIM_CMDR_NBYTES(data->cur_remaining);
|
||||||
|
twim->NCMDR = cmdr_reg | TWIM_CMDR_START;
|
||||||
|
} else {
|
||||||
|
/* Fill transfer command */
|
||||||
|
i2c_prepare_xfer_data(data);
|
||||||
|
|
||||||
|
data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, 0);
|
||||||
|
cmdr_reg |= TWIM_CMDR_NBYTES(data->cur_remaining);
|
||||||
|
twim->CMDR = cmdr_reg | TWIM_CMDR_START;
|
||||||
|
|
||||||
|
/* Fill next transfer command */
|
||||||
|
if (data->next_is_valid) {
|
||||||
|
data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg,
|
||||||
|
data->msg_next_idx);
|
||||||
|
cmdr_reg |= TWIM_CMDR_NBYTES(data_size);
|
||||||
|
twim->NCMDR = cmdr_reg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_DBG("Start Transfer: CMDR: 0x%08x, NCMDR: 0x%08x",
|
||||||
|
twim->CMDR, twim->NCMDR);
|
||||||
|
|
||||||
|
/* Extract Read/Write start operation */
|
||||||
|
cmdr_reg = twim->CMDR;
|
||||||
|
cur_is_read = (cmdr_reg & TWIM_CMDR_READ);
|
||||||
|
|
||||||
|
/* Enable master transfer */
|
||||||
|
twim->CR = TWIM_CR_MEN;
|
||||||
|
|
||||||
|
twim->IER = TWIM_IER_STD_MASK |
|
||||||
|
(cur_is_read ? TWIM_IER_RXRDY : TWIM_IER_TXRDY) |
|
||||||
|
TWIM_IER_IDLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i2c_prepare_next(struct i2c_sam_twim_dev_data *data,
|
||||||
|
Twim *const twim)
|
||||||
|
{
|
||||||
|
struct i2c_msg *msg = &data->msgs[data->msg_cur_idx];
|
||||||
|
volatile uint32_t ncmdr_wait;
|
||||||
|
uint32_t cmdr_reg;
|
||||||
|
uint32_t data_size;
|
||||||
|
uint32_t cur_is_read;
|
||||||
|
|
||||||
|
if (data->cur_idx == msg->len) {
|
||||||
|
data->cur_idx = 0;
|
||||||
|
data->msg_cur_idx++;
|
||||||
|
}
|
||||||
|
|
||||||
|
i2c_prepare_xfer_data(data);
|
||||||
|
|
||||||
|
/* Sync CMDR with NCMDR before apply changes */
|
||||||
|
ncmdr_wait = TWIM_NCMDR_FREE_WAIT;
|
||||||
|
while ((twim->NCMDR & TWIM_NCMDR_VALID) && (ncmdr_wait--)) {
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
cmdr_reg = twim->CMDR;
|
||||||
|
cur_is_read = (cmdr_reg & TWIM_CMDR_READ);
|
||||||
|
twim->IER |= (cur_is_read ? TWIM_IER_RXRDY : TWIM_IER_TXRDY);
|
||||||
|
|
||||||
|
/* Is there any more transfer? */
|
||||||
|
if (data->next_nb_bytes == 0) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
data_size = i2c_prepare_xfer_cmd(data, &cmdr_reg, data->msg_next_idx);
|
||||||
|
cmdr_reg |= TWIM_CMDR_NBYTES(data_size);
|
||||||
|
twim->NCMDR = cmdr_reg;
|
||||||
|
|
||||||
|
LOG_DBG("ld xfer: NCMDR: 0x%08x", twim->NCMDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void i2c_sam_twim_isr(const struct device *dev)
|
||||||
|
{
|
||||||
|
const struct i2c_sam_twim_dev_cfg *const cfg = DEV_CFG(dev);
|
||||||
|
struct i2c_sam_twim_dev_data *const data = DEV_DATA(dev);
|
||||||
|
Twim *const twim = cfg->regs;
|
||||||
|
struct i2c_msg *msg = &data->msgs[data->msg_cur_idx];
|
||||||
|
uint32_t isr_status;
|
||||||
|
|
||||||
|
/* Retrieve interrupt status */
|
||||||
|
isr_status = twim->SR & twim->IMR;
|
||||||
|
|
||||||
|
LOG_DBG("ISR: IMR: 0x%08x", isr_status);
|
||||||
|
|
||||||
|
/* Not Acknowledged */
|
||||||
|
if (isr_status & TWIM_SR_STD_MASK) {
|
||||||
|
/*
|
||||||
|
* If we get a NACK, clear the valid bit in CMDR,
|
||||||
|
* otherwise the command will be re-sent.
|
||||||
|
*/
|
||||||
|
twim->NCMDR &= ~TWIM_NCMDR_VALID;
|
||||||
|
twim->CMDR &= ~TWIM_CMDR_VALID;
|
||||||
|
|
||||||
|
data->cur_sr = isr_status;
|
||||||
|
goto xfer_comp;
|
||||||
|
}
|
||||||
|
|
||||||
|
data->cur_sr = 0;
|
||||||
|
|
||||||
|
/* Byte received */
|
||||||
|
if (isr_status & TWIM_SR_RXRDY) {
|
||||||
|
msg->buf[data->cur_idx++] = twim->RHR;
|
||||||
|
data->cur_remaining--;
|
||||||
|
|
||||||
|
if (data->cur_remaining > 0) {
|
||||||
|
goto check_xfer;
|
||||||
|
}
|
||||||
|
|
||||||
|
twim->IDR = TWIM_IDR_RXRDY;
|
||||||
|
|
||||||
|
/* Check for next transfer */
|
||||||
|
if (data->next_is_valid && data->next_nb_bytes > 0) {
|
||||||
|
i2c_prepare_next(data, twim);
|
||||||
|
} else {
|
||||||
|
data->next_nb_bytes = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Byte sent */
|
||||||
|
if (isr_status & TWIM_SR_TXRDY) {
|
||||||
|
|
||||||
|
if (data->cur_idx < msg->len) {
|
||||||
|
twim->THR = msg->buf[data->cur_idx++];
|
||||||
|
data->cur_remaining--;
|
||||||
|
|
||||||
|
goto check_xfer;
|
||||||
|
}
|
||||||
|
|
||||||
|
twim->IDR = TWIM_IDR_TXRDY;
|
||||||
|
|
||||||
|
/* Check for next transfer */
|
||||||
|
if (data->next_is_valid && data->next_nb_bytes > 0) {
|
||||||
|
i2c_prepare_next(data, twim);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
check_xfer:
|
||||||
|
|
||||||
|
/* Is transaction finished ? */
|
||||||
|
if (!(isr_status & TWIM_SR_IDLE)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_DBG("ISR: TWIM_SR_IDLE");
|
||||||
|
|
||||||
|
xfer_comp:
|
||||||
|
/* Disable all enabled interrupts */
|
||||||
|
twim->IDR = ~0UL;
|
||||||
|
|
||||||
|
/* Clear all status */
|
||||||
|
twim->SCR = ~0UL;
|
||||||
|
|
||||||
|
/* We are done */
|
||||||
|
k_sem_give(&data->sem);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int i2c_sam_twim_transfer(const struct device *dev,
|
||||||
|
struct i2c_msg *msgs,
|
||||||
|
uint8_t num_msgs, uint16_t addr)
|
||||||
|
{
|
||||||
|
struct i2c_sam_twim_dev_data *data = DEV_DATA(dev);
|
||||||
|
int ret = 0;
|
||||||
|
|
||||||
|
/* Send out messages */
|
||||||
|
k_mutex_lock(&data->bus_mutex, K_FOREVER);
|
||||||
|
|
||||||
|
/* Load messages */
|
||||||
|
data->msgs = msgs;
|
||||||
|
data->msg_max_idx = num_msgs;
|
||||||
|
|
||||||
|
i2c_start_xfer(dev, addr);
|
||||||
|
|
||||||
|
/* Wait for the message transfer to complete */
|
||||||
|
k_sem_take(&data->sem, K_FOREVER);
|
||||||
|
|
||||||
|
if (data->cur_sr & TWIM_SR_STD_MASK) {
|
||||||
|
ret = -EIO;
|
||||||
|
|
||||||
|
LOG_INF("MSG: %d, ANAK: %d, ARBLST: %d",
|
||||||
|
data->msg_cur_idx,
|
||||||
|
(data->cur_sr & TWIM_SR_ANAK) > 0,
|
||||||
|
(data->cur_sr & TWIM_SR_ARBLST) > 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
k_mutex_unlock(&data->bus_mutex);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int i2c_sam_twim_initialize(const struct device *dev)
|
||||||
|
{
|
||||||
|
const struct i2c_sam_twim_dev_cfg *const cfg = DEV_CFG(dev);
|
||||||
|
struct i2c_sam_twim_dev_data *data = DEV_DATA(dev);
|
||||||
|
Twim *const twim = cfg->regs;
|
||||||
|
uint32_t bitrate_cfg;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
/* Configure interrupts */
|
||||||
|
cfg->irq_config();
|
||||||
|
|
||||||
|
/*
|
||||||
|
* initialize mutex. it is used when multiple transfers are taking
|
||||||
|
* place to guarantee that each one is atomic and has exclusive access
|
||||||
|
* to the I2C bus.
|
||||||
|
*/
|
||||||
|
k_mutex_init(&data->bus_mutex);
|
||||||
|
|
||||||
|
/* Initialize semaphore */
|
||||||
|
k_sem_init(&data->sem, 0, 1);
|
||||||
|
|
||||||
|
/* Connect pins to the peripheral */
|
||||||
|
soc_gpio_list_configure(cfg->pin_list, cfg->pin_list_size);
|
||||||
|
|
||||||
|
/* Enable module's clock */
|
||||||
|
soc_pmc_peripheral_enable(cfg->periph_id);
|
||||||
|
|
||||||
|
/* Enable the module*/
|
||||||
|
twim->CR = TWIM_CR_MEN;
|
||||||
|
|
||||||
|
/* Reset the module */
|
||||||
|
twim->CR |= TWIM_CR_SWRST;
|
||||||
|
|
||||||
|
/* Clear SR */
|
||||||
|
twim->SCR = ~0UL;
|
||||||
|
|
||||||
|
bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
|
||||||
|
|
||||||
|
ret = i2c_sam_twim_configure(dev, I2C_MODE_MASTER | bitrate_cfg);
|
||||||
|
if (ret < 0) {
|
||||||
|
LOG_ERR("Failed to initialize %s device", DEV_NAME(dev));
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable module's IRQ */
|
||||||
|
irq_enable(cfg->irq_id);
|
||||||
|
|
||||||
|
LOG_INF("Device %s initialized", DEV_NAME(dev));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct i2c_driver_api i2c_sam_twim_driver_api = {
|
||||||
|
.configure = i2c_sam_twim_configure,
|
||||||
|
.transfer = i2c_sam_twim_transfer,
|
||||||
|
};
|
||||||
|
|
||||||
|
#define DT_INST_ENUM_IDX(inst, prop) DT_ENUM_IDX(DT_DRV_INST(inst), prop)
|
||||||
|
|
||||||
|
#define I2C_TWIM_SAM_SLEW_REGS(n) \
|
||||||
|
.std_clk_slew_lim = DT_INST_ENUM_IDX(n, std_clk_slew_lim), \
|
||||||
|
.std_clk_strength_low = DT_INST_ENUM_IDX(n, std_clk_strength_low),\
|
||||||
|
.std_data_slew_lim = DT_INST_ENUM_IDX(n, std_data_slew_lim), \
|
||||||
|
.std_data_strength_low = DT_INST_ENUM_IDX(n, std_data_strength_low),\
|
||||||
|
.hs_clk_slew_lim = DT_INST_ENUM_IDX(n, hs_clk_slew_lim), \
|
||||||
|
.hs_clk_strength_high = DT_INST_ENUM_IDX(n, hs_clk_strength_high),\
|
||||||
|
.hs_clk_strength_low = DT_INST_ENUM_IDX(n, hs_clk_strength_low),\
|
||||||
|
.hs_data_slew_lim = DT_INST_ENUM_IDX(n, hs_data_slew_lim), \
|
||||||
|
.hs_data_strength_low = DT_INST_ENUM_IDX(n, hs_data_strength_low)
|
||||||
|
|
||||||
|
#define I2C_TWIM_SAM_INIT(n) \
|
||||||
|
static const struct device DEVICE_NAME_GET(i2c##n##_sam); \
|
||||||
|
\
|
||||||
|
static void i2c##n##_sam_irq_config(void) \
|
||||||
|
{ \
|
||||||
|
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
|
||||||
|
i2c_sam_twim_isr, \
|
||||||
|
DEVICE_GET(i2c##n##_sam), 0); \
|
||||||
|
} \
|
||||||
|
\
|
||||||
|
static const struct soc_gpio_pin pins_twim##n[] = \
|
||||||
|
{ATMEL_SAM_DT_PIN(n, 0), ATMEL_SAM_DT_PIN(n, 1)}; \
|
||||||
|
\
|
||||||
|
static const struct i2c_sam_twim_dev_cfg i2c##n##_sam_config = {\
|
||||||
|
.regs = (Twim *)DT_INST_REG_ADDR(n), \
|
||||||
|
.irq_config = i2c##n##_sam_irq_config, \
|
||||||
|
.periph_id = DT_INST_PROP(n, peripheral_id), \
|
||||||
|
.irq_id = DT_INST_IRQN(n), \
|
||||||
|
.pin_list = pins_twim##n, \
|
||||||
|
.pin_list_size = ARRAY_SIZE(pins_twim##n), \
|
||||||
|
.bitrate = DT_INST_PROP(n, clock_frequency), \
|
||||||
|
.hs_master_code = DT_INST_ENUM_IDX(n, hs_master_code), \
|
||||||
|
I2C_TWIM_SAM_SLEW_REGS(n), \
|
||||||
|
}; \
|
||||||
|
\
|
||||||
|
static struct i2c_sam_twim_dev_data i2c##n##_sam_data; \
|
||||||
|
\
|
||||||
|
DEVICE_AND_API_INIT(i2c##n##_sam, DT_INST_LABEL(n), \
|
||||||
|
&i2c_sam_twim_initialize, \
|
||||||
|
&i2c##n##_sam_data, &i2c##n##_sam_config, \
|
||||||
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
||||||
|
&i2c_sam_twim_driver_api)
|
||||||
|
|
||||||
|
DT_INST_FOREACH_STATUS_OKAY(I2C_TWIM_SAM_INIT);
|
||||||
|
|
@ -44,6 +44,10 @@ config ENTROPY_SAM_RNG
|
||||||
default y
|
default y
|
||||||
depends on ENTROPY_GENERATOR
|
depends on ENTROPY_GENERATOR
|
||||||
|
|
||||||
|
config I2C_SAM_TWIM
|
||||||
|
default y
|
||||||
|
depends on I2C
|
||||||
|
|
||||||
config SPI_SAM
|
config SPI_SAM
|
||||||
default y
|
default y
|
||||||
depends on SPI
|
depends on SPI
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue