boards: arc: emsdp: add basic emsdp board support

* add basic emsdp board support

Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This commit is contained in:
Watson Zeng 2019-06-20 15:04:33 +08:00 committed by Carles Cufí
parent f71a0f4097
commit bcba284e8f
30 changed files with 1165 additions and 0 deletions

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@ -171,6 +171,7 @@
/drivers/*/*xec* @franciscomunoz @albertofloyd @scottwcpg
/drivers/wifi/ @jukkar @tbursztyka @pfalcon
/drivers/wifi/eswifi/ @loicpoulain
/dts/arc/ @vonhust @ruuddw @iriszzw
/dts/arm/atmel/samr21.dtsi @benpicco
/dts/arm/st/ @erwango
/dts/arm/ti/cc13?2* @bwitherspoon

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# SPDX-License-Identifier: Apache-2.0
zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c)

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# Kconfig - DesignWare ARC EM Software Development Platform board configuration
#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
config BOARD_EMSDP
bool "EM Software Development Platform"
depends on SOC_ARC_EMSDP
help
The ARC EM Software Development Platform (emsdp) is an FPGA based
development platform intended to support ARC licenses in developing
their software for the ARC EM processor family and ARC EM Subsystems.
It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D
processors. ARC EM Enhanced Security Package (ESP) and ARC EM
Subsystems (DFSS, SCSS, DSS) are also supported.

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# Kconfig - DesignWare ARC EM Software Development Platform board configuration
#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if BOARD_EMSDP
config BOARD
default "emsdp"
config CPU_ARCEM
default y
if GPIO
config GPIO_DW
default y
if GPIO_DW
config GPIO_DW_0
default y
config GPIO_DW_1
default y
endif # GPIO_DW
endif # GPIO
if SERIAL
config UART_NS16550
default y
endif # SERIAL
if UART_CONSOLE
config UART_NS16550_PORT_0
default y
endif # UART_CONSOLE
endif # BOARD_EMSDP

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/*
* Copyright (c) 2019 Synopsys
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <generated_dts_board.h>
#include <soc.h>
#include <arch/arc/v2/mpu/arc_mpu.h>
#include <linker/linker-defs.h>
static struct arc_mpu_region mpu_regions[] = {
/* Region ICCM */
MPU_REGION_ENTRY("ICCM",
DT_ICCM_BASE_ADDRESS,
DT_ICCM_SIZE * 1024,
REGION_ROM_ATTR),
/* Region DCCM */
MPU_REGION_ENTRY("DCCM",
DT_DCCM_BASE_ADDRESS,
DT_DCCM_SIZE * 1024,
REGION_KERNEL_RAM_ATTR | REGION_DYNAMIC),
/* Region DDR RAM */
MPU_REGION_ENTRY("SRAM",
DT_INST_0_MMIO_SRAM_BASE_ADDRESS,
DT_INST_0_MMIO_SRAM_SIZE,
REGION_KERNEL_RAM_ATTR |
AUX_MPU_ATTR_KW | AUX_MPU_ATTR_KR | AUX_MPU_ATTR_UR |
AUX_MPU_ATTR_KE | AUX_MPU_ATTR_UE | REGION_DYNAMIC),
/* Region Peripheral */
MPU_REGION_ENTRY("PERIPHERAL",
0xF0000000,
64 * 1024,
REGION_KERNEL_RAM_ATTR),
};
struct arc_mpu_config mpu_config = {
.num_regions = ARRAY_SIZE(mpu_regions),
.mpu_regions = mpu_regions,
};

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# SPDX-License-Identifier: Apache-2.0
# TODO: can this board just use the usual openocd runner?
set(BOARD_FLASH_RUNNER em-starterkit)
set(BOARD_DEBUG_RUNNER em-starterkit)
board_finalize_runner_args(em-starterkit)

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/* SPDX-License-Identifier: Apache-2.0 */
/ {
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
led3 = &led3;
led4 = &led4;
led5 = &led5;
led6 = &led6;
led7 = &led7;
led8 = &led8;
sw0 = &switch0;
sw1 = &switch1;
sw2 = &switch2;
sw2 = &switch3;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio1 0 0>;
label = "LED 0";
};
led1: led_1 {
gpios = <&gpio1 1 0>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio1 2 0>;
label = "LED 2";
};
led3: led_3 {
gpios = <&gpio1 3 0>;
label = "LED 3";
};
led4: led_4 {
gpios = <&gpio1 4 0>;
label = "LED 4";
};
led5: led_5 {
gpios = <&gpio1 5 0>;
label = "LED 1";
};
led6: led_6 {
gpios = <&gpio1 6 0>;
label = "LED 2";
};
led7: led_7 {
gpios = <&gpio1 7 0>;
label = "LED 3";
};
led8: led_8 {
gpios = <&gpio1 8 0>;
label = "LED 4";
};
};
buttons {
compatible = "gpio-keys";
switch0: switch_0 {
/* gpio flags need validation */
gpios = <&gpio0 0 GPIO_INT_ACTIVE_LOW>;
label = "DIP SW1 - Switch 1";
};
switch1: switch_1 {
/* gpio flags need validation */
gpios = <&gpio0 1 GPIO_INT_ACTIVE_LOW>;
label = "DIP SW1 - Switch 2";
};
switch2: switch_2 {
/* gpio flags need validation */
gpios = <&gpio0 2 GPIO_INT_ACTIVE_LOW>;
label = "DIP SW1 - Switch 3";
};
switch3: switch_3 {
/* gpio flags need validation */
gpios = <&gpio0 3 GPIO_INT_ACTIVE_LOW>;
label = "DIP SW1 - Switch 4";
};
};
};

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.. _emsdp:
DesignWare(R) ARC(R) EM Software Development Platform
#####################################################
Overview
********
The DesignWare® ARC® EM Software Development Platform (SDP) is a flexible platform
for rapid software development on ARC EM processor-based subsystems. It is intended
to accelerate software development and debug of ARC EM processors and subsystems for
a wide range of ultra-low power embedded applications such as IoT, sensor fusion,
and voice applications.
.. image:: ./emsdp.jpg
:width: 442px
:align: center
:alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com)
For details about the board, see: `DesignWare ARC EM Software Development Platform
(EM SDP) <https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform>`__
Hardware
********
For hardware feature details, refer to : `ARC EM Software Development Platform
<https://embarc.org/embarc_osp/doc/build/html/board/emsdp.html>`__
Programming and Debugging
*************************
Required Hardware and Software
==============================
To use Zephyr RTOS applications on the EM Software Development Platform board,
a few additional pieces of hardware are required.
* A micro USB cable to connect the computer.
* A universal switching power adaptor (110-240V AC to 12 DC),
provided in the package, which used to power the board.
* :ref:`The Zephyr SDK <zephyr_sdk>`
* Terminal emulator software for use with the USB-UART. Suggestion:
`Putty Website`_.
* (optional) A collection of Pmods, Arduino modules, or Mikro modules.
See `Digilent Pmod Modules`_ or develop your custom interfaces to attach
to the Pmod connector.
Set up the EM Software Development Platform
===========================================
To run Zephyr application on EM Software Development Platform, you need to
setup the board correctly.
* Connect the 12V DC power supply to your board.
* Connect the digilent usb cable from your host to the board.
Set up Zephyr Software
======================
Building Sample Applications
==============================
You can try many of the sample applications or tests, but let us discuss
the one called :ref:`hello_world`.
It is found in :zephyr_file:`samples/hello_world`.
Configuring
-----------
You may need to write a prj_arc.conf file if the sample doesn't have one.
Next, you can use the menuconfig rule to configure the target. By specifying
``emsdp`` as the board configuration, you can select the ARC EM Software
Development Platform board support for Zephyr.
.. zephyr-app-commands::
:board: emsdp
:zephyr-app: samples/hello_world
:goals: menuconfig
Building
--------
You can build an application in the usual way. Refer to
:ref:`build_an_application` for more details. Here is an example for
:ref:`hello_world`.
.. zephyr-app-commands::
:board: emsdp
:zephyr-app: samples/hello_world
:maybe-skip-config:
:goals: build
Connecting Serial Output
=========================
In the default configuration, Zephyr's EM Software Development Platform images
support serial output via the USB-UART on the board. To enable serial output:
* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc)
* Specify the tty driver name, for example, on Linux this may be
:file:`/dev/ttyUSB0`
* Set the communication settings to:
========= =====
Parameter Value
========= =====
Baud: 115200
Data: 8 bits
Parity: None
Stopbits: 1
========= =====
Debugging
==========
Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT
Development Kit directly.
One option is to build and debug the application using the usual
Zephyr build system commands.
.. zephyr-app-commands::
:board: emsdp
:app: <my app>
:goals: debug
At this point you can do your normal debug session. Set breakpoints and then
'c' to continue into the program.
The other option is to launch a debug server, as follows.
.. zephyr-app-commands::
:board: emsdp
:app: <my app>
:goals: debugserver
Then connect to the debug server at the EM Software Development Platform from a
second console, from the build directory containing the output :file:`zephyr.elf`.
.. code-block:: console
$ cd <my app>
$ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \
arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf
(gdb) target remote localhost:3333
(gdb) load
(gdb) b main
(gdb) c
Flashing
========
If you just want to download the application to the EM Software Development
Platform's CCM and run, you can do so in the usual way.
.. zephyr-app-commands::
:board: emsdp
:app: <my app>
:goals: flash
This command still uses openocd and gdb to load the application elf file to EM
Software Development Platform, but it will load the application and immediately run.
If power is removed, the application will be lost since it wasn't written to flash.
Most of the time you will not be flashing your program but will instead debug
it using openocd and gdb. The program can be download via the USB cable into
the code and data memories.
Release Notes
*************
References
**********
.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules
.. _Putty website: http://www.putty.org

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/*
* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <emsdp.dtsi>
#include "board.dtsi"
/ {
model = "emsdp";
compatible = "snps,emsdp", "snps,emsdp";
aliases {
uart-0 = &uart0;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
&uart0 {
status = "ok";
current-speed = <115200>;
};

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identifier: emsdp
name: EM Software Development Platform
type: mcu
arch: arc
toolchain:
- zephyr
- xtools
ram: 128
testing:
ignore_tags:
- net
- bluetooth

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# SPDX-License-Identifier: Apache-2.0
CONFIG_ARC=y
CONFIG_SOC_ARC_EMSDP=y
CONFIG_SOC_EMSDP_EM11D=y
CONFIG_BOARD_EMSDP=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_XIP=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_PRINTK=y
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_ARC_MPU_ENABLE=y
CONFIG_GPIO=y

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# Copyright (C) 2019 Synopsys, Inc.
# SPDX-License-Identifier: Apache-2.0
#
#
# Synopsys DesignWare ARC EM Software Development Platform
#
# Configure JTAG cable
# EM SDP has built-in FT2232 chip, which is similiar to Digilent HS-1.
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0088 0x008b
ftdi_channel 0
# EM11D requires 10 MHz.
adapter_khz 10000
# ARCs support only JTAG.
transport select jtag
source [find cpu/arc/em.tcl]
set _CHIPNAME arc-em
set _TARGETNAME $_CHIPNAME.cpu
# EM SDP IDENTITY is 0x200444b1
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1
set _coreid 0
set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
-coreid 0 -dbgbase $_dbgbase -endian little
# There is no SRST, so do a software reset
$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
arc_em_init_regs

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@ -34,5 +34,9 @@ elseif("${ARCH}" STREQUAL "arc")
set(GCC_M_CPU em4_fpuda)
elseif(CONFIG_CPU_ARCHS)
set(GCC_M_CPU hs)
elseif(CONFIG_CPU_EM4)
set(GCC_M_CPU arcem)
elseif(CONFIG_CPU_EM6)
set(GCC_M_CPU arcem)
endif()
endif()

90
dts/arc/emsdp.dtsi Normal file
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/*
* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
//#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#define DT_APB_CLK_HZ 100000000
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem";
reg = <1>;
};
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@60000000 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x60000000 0x20000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x20000>;
};
sram0: memory@10000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x10000000 0x1000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@f0004000 {
compatible = "ns16550";
clock-frequency = <DT_APB_CLK_HZ>;
reg = <0xf0004000 0x1000>;
label = "UART_0";
interrupt-parent = <&intc>;
interrupts = <107 1>;
};
gpio0: gpio@f0002000 {
compatible = "snps,designware-gpio";
reg = <0xf0002000 0xc>;
bits = <4>;
label = "GPIO_0";
interrupt-parent = <&intc>;
interrupts = <85 1>;
gpio-controller;
#gpio-cells = <2>;
};
gpio1: gpio@f000200c {
compatible = "snps,designware-gpio";
reg = <0xf000200c 0xc>;
bits = <8>;
label = "GPIO_1";
interrupt-parent = <&intc>;
interrupts = <0 1>;
gpio-controller;
#gpio-cells = <2>;
};
};
};

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# SPDX-License-Identifier: Apache-2.0
zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata)
if(CONFIG_SOC_EMSDP_EM4)
zephyr_compile_options(-mmpy-option=3 -mno-div-rem)
elseif(CONFIG_SOC_EMSDP_EM6)
zephyr_compile_options(-mmpy-option=3 -mno-div-rem)
elseif(CONFIG_SOC_EMSDP_EM5D)
zephyr_compile_options(-mmpy-option=6)
elseif(CONFIG_SOC_EMSDP_EM7D)
zephyr_compile_options(-mmpy-option=6)
elseif(CONFIG_SOC_EMSDP_EM7D_ESP)
zephyr_compile_options(-mmpy-option=6)
elseif(CONFIG_SOC_EMSDP_EM9D)
zephyr_compile_options(-mmpy-option=6)
zephyr_compile_options_ifdef(CONFIG_FLOAT -mfpu=fpus_all)
elseif(CONFIG_SOC_EMSDP_EM11D)
zephyr_compile_options(-mmpy-option=6)
zephyr_compile_options_ifdef(CONFIG_FLOAT -mfpu=fpuda_all)
endif()
zephyr_sources(
soc.c
)

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_ARC_EMSDP
choice
prompt "ARC EM Software Development Platform Core Selection"
default SOC_EMSDP_EM11D
config SOC_EMSDP_EM4
bool "Synopsys ARC EM4 of EMSDP"
select CPU_HAS_MPU
config SOC_EMSDP_EM6
bool "Synopsys ARC EM6 of EMSDP"
select CPU_HAS_MPU
config SOC_EMSDP_EM5D
bool "Synopsys ARC EM5D of EMSDP"
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_EMSDP_EM7D
bool "Synopsys ARC EM7D of EMSDP"
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_EMSDP_EM7D_ESP
bool "Synopsys ARC EM7D+ESP of EMSDP"
select CPU_HAS_MPU
select CPU_HAS_FPU
select ARC_HAS_SECURE
config SOC_EMSDP_EM9D
bool "Synopsys ARC EM9D of EMSDP"
select CPU_HAS_MPU
select CPU_HAS_FPU
config SOC_EMSDP_EM11D
bool "Synopsys ARC EM11D of EMSDP"
select CPU_HAS_MPU
select CPU_HAS_FPU
endchoice
endif #SOC_ARC_EMSDP

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_ARC_EMSDP
config SOC
string
default "snps_emsdp"
config NUM_IRQ_PRIO_LEVELS
# This processor supports 4 priority levels:
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
default 4
config NUM_IRQS
# must be > the highest interrupt number used
default 128
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
source "soc/arc/snps_emsdp/Kconfig.defconfig.em4"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em5d"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em6"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em9d"
source "soc/arc/snps_emsdp/Kconfig.defconfig.em11d"
endif # SOC_ARC_EMSDP

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM11D
config CPU_EM4_FPUDA
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default y
config FP_FPU_DA
def_bool y
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM11D

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM4
config CPU_EM4
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default n
config FP_FPU_DA
def_bool n
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM4

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM5D
config CPU_EM4_FPUDA
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default n
config FP_FPU_DA
def_bool y
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM5D

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM6
config CPU_EM6
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default y
config FP_FPU_DA
def_bool n
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM6

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM7D
config CPU_EM4_FPUDA
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default y
config FP_FPU_DA
def_bool y
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM7D

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM7D_ESP
config CPU_EM4_FPUDA
def_bool y
config ARC_MPU_VER
default 3
config RGF_NUM_BANKS
default 1
config HARVARD
default y
config ARC_FIRQ
default n
config CACHE_FLUSHING
default y
config FP_FPU_DA
def_bool y
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM7D_ESP

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_EMSDP_EM9D
config CPU_EM4_FPUDA
def_bool y
config ARC_MPU_VER
default 2
config RGF_NUM_BANKS
default 2
config HARVARD
default y
config ARC_FIRQ
default y
config CACHE_FLUSHING
default n
config FP_FPU_DA
def_bool y
if (ARC_MPU_VER = 2)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 2048
if ZTEST
config ZTEST_STACKSIZE
default 2048
endif # ZTEST
endif # ARC_MPU_VER
endif #SOC_EMSDP_EM9D

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#
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_ARC_EMSDP
bool "Synopsys ARC EM Software Development Platform"

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/*
* Copyright (c) 2018 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
/* CCM configuration */
#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_60000000_BASE_ADDRESS
#define DT_ICCM_SIZE (DT_ARC_ICCM_60000000_SIZE >> 10)
/*
* UART configuration
*/
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0004000_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0004000_IRQ_0
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0004000_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0004000_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0004000_LABEL
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0004000_IRQ_0_PRIORITY
/*
* GPIO configuration
*/
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
#define DT_GPIO_DW_1_IRQ_FLAGS 0
/* End of SoC Level DTS fixup file */

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/*
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Linker script for the Synopsys ARC IoT Development Kit
*/
#include <generated_dts_board.h>
#include <autoconf.h>
/*
* SRAM base address and size
*
*/
#if defined(CONFIG_SRAM_BASE_ADDRESS) && (CONFIG_SRAM_SIZE > 0)
#define SRAM_START CONFIG_SRAM_BASE_ADDRESS
#define SRAM_SIZE CONFIG_SRAM_SIZE
#endif
/* Instruction Closely Coupled Memory (ICCM) base address and size */
#if defined(DT_ICCM_BASE_ADDRESS) && (DT_ICCM_SIZE > 0)
#define ICCM_START DT_ICCM_BASE_ADDRESS
#define ICCM_SIZE DT_ICCM_SIZE
#endif
/*
* DCCM base address and size. DCCM is the data memory.
*/
/* Data Closely Coupled Memory (DCCM) base address and size */
#if defined(DT_DCCM_BASE_ADDRESS) && (DT_DCCM_SIZE > 0)
#define DCCM_START DT_DCCM_BASE_ADDRESS
#define DCCM_SIZE DT_DCCM_SIZE
#endif
#include <arch/arc/v2/linker.ld>

12
soc/arc/snps_emsdp/soc.c Normal file
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/*
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* This module provides routines to initialize and support soc-level hardware
* for the IoT Development Kit board.
*
*/

47
soc/arc/snps_emsdp/soc.h Normal file
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/*
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Board configuration macros for EM Starter kit board
*
* This header file is used to specify and describe board-level
* aspects for the target.
*/
#ifndef _SOC_H_
#define _SOC_H_
#include <misc/util.h>
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(100)
/*
* UART: use lr and sr to access subsystem uart IP
*/
// #define UART_NS16550_ACCESS_IOPORT
// #define UART_REG_ADDR_INTERVAL 4
/* ARC EM Core IRQs */
#define IRQ_TIMER0 16
#ifndef _ASMLANGUAGE
#include <misc/util.h>
#include <random/rand32.h>
/*
* UARTs: UART0 & UART1 & UART2
*/
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
#endif /* !_ASMLANGUAGE */
#endif /* _SOC_H_ */