drivers: dma: dma_stm32: add stm32c0-series support
Add support for dma on the stm32c0-series. Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
This commit is contained in:
Benjamin Björnsson
Anas Nashif
parent
65bbca4a07
commit
bd7929ce1a
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@ -54,7 +54,8 @@ config DMAMUX_STM32
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config DMA_STM32_SHARED_IRQS
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bool
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default y
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32G0X || SOC_SERIES_STM32L0X
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depends on SOC_SERIES_STM32C0X || SOC_SERIES_STM32F0X || \
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SOC_SERIES_STM32G0X || SOC_SERIES_STM32L0X
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help
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Enable shared IRQ support on devices where channels share 1 IRQ.
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@ -36,8 +36,10 @@ LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL);
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#define DMA_STM32_0_STREAM_COUNT 7
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#elif DT_INST_IRQ_HAS_IDX(0, 5)
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#define DMA_STM32_0_STREAM_COUNT 6
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#else
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#elif DT_INST_IRQ_HAS_IDX(0, 4)
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#define DMA_STM32_0_STREAM_COUNT 5
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#else
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#define DMA_STM32_0_STREAM_COUNT 3
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#endif
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#endif /* DT_NODE_HAS_STATUS(DT_DRV_INST(0), okay) */
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@ -765,6 +767,7 @@ static void dma_stm32_irq_##dma##_##chan(const struct device *dev) \
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 0);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 1);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 2);
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 3);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 4);
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#if DT_INST_IRQ_HAS_IDX(0, 5)
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@ -773,6 +776,7 @@ DMA_STM32_DEFINE_IRQ_HANDLER(0, 5);
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 6);
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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DMA_STM32_DEFINE_IRQ_HANDLER(0, 7);
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#endif /* DT_INST_IRQ_HAS_IDX(0, 3) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
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@ -786,6 +790,7 @@ static void dma_stm32_config_irq_0(const struct device *dev)
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#ifndef CONFIG_DMA_STM32_SHARED_IRQS
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DMA_STM32_IRQ_CONNECT(0, 2);
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#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
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#if DT_INST_IRQ_HAS_IDX(0, 3)
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DMA_STM32_IRQ_CONNECT(0, 3);
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#ifndef CONFIG_DMA_STM32_SHARED_IRQS
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DMA_STM32_IRQ_CONNECT(0, 4);
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@ -795,11 +800,12 @@ static void dma_stm32_config_irq_0(const struct device *dev)
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DMA_STM32_IRQ_CONNECT(0, 6);
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#if DT_INST_IRQ_HAS_IDX(0, 7)
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DMA_STM32_IRQ_CONNECT(0, 7);
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#endif /* DT_INST_IRQ_HAS_IDX(0, 3) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 5) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 6) */
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#endif /* DT_INST_IRQ_HAS_IDX(0, 7) */
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#endif /* CONFIG_DMA_STM32_SHARED_IRQS */
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/* Either 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
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/* Either 3 or 5 or 6 or 7 or 8 channels for DMA across all stm32 series. */
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}
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DMA_STM32_INIT_DEV(0);
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@ -21,6 +21,7 @@ uint32_t dma_stm32_id_to_stream(uint32_t id)
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LL_DMA_CHANNEL_1,
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LL_DMA_CHANNEL_2,
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LL_DMA_CHANNEL_3,
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#if defined(LL_DMA_CHANNEL_4)
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LL_DMA_CHANNEL_4,
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LL_DMA_CHANNEL_5,
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#if defined(LL_DMA_CHANNEL_6)
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@ -32,6 +33,7 @@ uint32_t dma_stm32_id_to_stream(uint32_t id)
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#endif /* LL_DMA_CHANNEL_8 */
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#endif /* LL_DMA_CHANNEL_7 */
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#endif /* LL_DMA_CHANNEL_6 */
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#endif /* LL_DMA_CHANNEL_4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(stream_nr));
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@ -45,6 +47,7 @@ void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_HT1,
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LL_DMA_ClearFlag_HT2,
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LL_DMA_ClearFlag_HT3,
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#if defined(LL_DMA_IFCR_CHTIF4)
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LL_DMA_ClearFlag_HT4,
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LL_DMA_ClearFlag_HT5,
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#if defined(LL_DMA_IFCR_CHTIF6)
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@ -56,6 +59,7 @@ void dma_stm32_clear_ht(DMA_TypeDef *DMAx, uint32_t id)
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#endif /* LL_DMA_IFCR_CHTIF8 */
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#endif /* LL_DMA_IFCR_CHTIF7 */
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#endif /* LL_DMA_IFCR_CHTIF6 */
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#endif /* LL_DMA_IFCR_CHTIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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@ -69,6 +73,7 @@ void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_TC1,
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LL_DMA_ClearFlag_TC2,
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LL_DMA_ClearFlag_TC3,
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#if defined(LL_DMA_IFCR_CTCIF4)
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LL_DMA_ClearFlag_TC4,
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LL_DMA_ClearFlag_TC5,
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#if defined(LL_DMA_IFCR_CTCIF6)
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@ -80,6 +85,7 @@ void dma_stm32_clear_tc(DMA_TypeDef *DMAx, uint32_t id)
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#endif /* LL_DMA_IFCR_CTCIF8 */
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#endif /* LL_DMA_IFCR_CTCIF7 */
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#endif /* LL_DMA_IFCR_CTCIF6 */
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#endif /* LL_DMA_IFCR_CTCIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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@ -93,6 +99,7 @@ bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_HT1,
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LL_DMA_IsActiveFlag_HT2,
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LL_DMA_IsActiveFlag_HT3,
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#if defined(LL_DMA_IFCR_CHTIF4)
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LL_DMA_IsActiveFlag_HT4,
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LL_DMA_IsActiveFlag_HT5,
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#if defined(LL_DMA_IFCR_CHTIF6)
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@ -104,6 +111,7 @@ bool dma_stm32_is_ht_active(DMA_TypeDef *DMAx, uint32_t id)
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#endif /* LL_DMA_IFCR_CHTIF8 */
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#endif /* LL_DMA_IFCR_CHTIF7 */
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#endif /* LL_DMA_IFCR_CHTIF6 */
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#endif /* LL_DMA_IFCR_CHTIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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@ -117,6 +125,7 @@ bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_TC1,
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LL_DMA_IsActiveFlag_TC2,
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LL_DMA_IsActiveFlag_TC3,
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#if defined(LL_DMA_IFCR_CTCIF4)
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LL_DMA_IsActiveFlag_TC4,
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LL_DMA_IsActiveFlag_TC5,
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#if defined(LL_DMA_IFCR_CTCIF6)
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@ -128,6 +137,7 @@ bool dma_stm32_is_tc_active(DMA_TypeDef *DMAx, uint32_t id)
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#endif /* LL_DMA_IFCR_CTCIF8 */
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#endif /* LL_DMA_IFCR_CTCIF7 */
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#endif /* LL_DMA_IFCR_CTCIF6 */
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#endif /* LL_DMA_IFCR_CTCIF4 */
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};
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__ASSERT_NO_MSG(id < ARRAY_SIZE(func));
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@ -142,6 +152,7 @@ void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_TE1,
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LL_DMA_ClearFlag_TE2,
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LL_DMA_ClearFlag_TE3,
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#if defined(LL_DMA_IFCR_CTEIF4)
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LL_DMA_ClearFlag_TE4,
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LL_DMA_ClearFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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@ -150,6 +161,7 @@ void dma_stm32_clear_te(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_TE7,
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_ClearFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF4 */
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#endif /* LL_DMA_IFCR_CTEIF8 */
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@ -166,6 +178,7 @@ void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_GI1,
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LL_DMA_ClearFlag_GI2,
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LL_DMA_ClearFlag_GI3,
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#if defined(LL_DMA_IFCR_CGIF4)
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LL_DMA_ClearFlag_GI4,
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LL_DMA_ClearFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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@ -174,6 +187,7 @@ void dma_stm32_clear_gi(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_ClearFlag_GI7,
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_ClearFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF4 */
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#endif /* LL_DMA_IFCR_CGIF6 */
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#endif /* LL_DMA_IFCR_CGIF7 */
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#endif /* LL_DMA_IFCR_CGIF8 */
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@ -190,6 +204,7 @@ bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_TE1,
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LL_DMA_IsActiveFlag_TE2,
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LL_DMA_IsActiveFlag_TE3,
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#if defined(LL_DMA_IFCR_CTEIF4)
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LL_DMA_IsActiveFlag_TE4,
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LL_DMA_IsActiveFlag_TE5,
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#if defined(LL_DMA_IFCR_CTEIF6)
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@ -198,6 +213,7 @@ bool dma_stm32_is_te_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_TE7,
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#if defined(LL_DMA_IFCR_CTEIF8)
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LL_DMA_IsActiveFlag_TE8,
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#endif /* LL_DMA_IFCR_CTEIF4 */
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#endif /* LL_DMA_IFCR_CTEIF6 */
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#endif /* LL_DMA_IFCR_CTEIF7 */
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#endif /* LL_DMA_IFCR_CTEIF8 */
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@ -214,6 +230,7 @@ bool dma_stm32_is_gi_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_GI1,
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LL_DMA_IsActiveFlag_GI2,
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LL_DMA_IsActiveFlag_GI3,
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#if defined(LL_DMA_IFCR_CGIF4)
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LL_DMA_IsActiveFlag_GI4,
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LL_DMA_IsActiveFlag_GI5,
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#if defined(LL_DMA_IFCR_CGIF6)
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@ -222,6 +239,7 @@ bool dma_stm32_is_gi_active(DMA_TypeDef *DMAx, uint32_t id)
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LL_DMA_IsActiveFlag_GI7,
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#if defined(LL_DMA_IFCR_CGIF8)
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LL_DMA_IsActiveFlag_GI8,
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#endif /* LL_DMA_IFCR_CGIF4 */
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#endif /* LL_DMA_IFCR_CGIF6 */
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#endif /* LL_DMA_IFCR_CGIF7 */
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#endif /* LL_DMA_IFCR_CGIF8 */
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