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dts: atmel sam: Add pinctrl support for SAM UART and USART

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Add pinctl support for the SAM UART and SAM USART devices.  We update
the UART and USART bindings to have pinctrl-0 bindings that are expected
to have 2 phandles to the RX & TX pinctrl nodes.

The pinctrl nodes will have an 'atmel,pins' property that describes the
GPIO port, pin and periphal configuration for that pin.

We add sam*-pinctrl.dtsi files with all the various pin ctrl
configuration operations supported by the given SoC family.  These
files are based on data extracted from the Atmel ASF HAL
(in include/sam<FAMILY>/pio/*.h).

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-04-07 08:19:32 -05:00 committed by Kumar Gala
parent ebbb92d330
commit bdf58d11f0
13 changed files with 248 additions and 0 deletions
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1
CODEOWNERS
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@ -242,6 +242,7 @@
/dts/arm/atmel/sam*5*.dtsi @benpicco
/dts/arm/atmel/same70* @nandojve
/dts/arm/atmel/samv71* @nandojve
/dts/arm/atmel/ @galak
/dts/arm/broadcom/ @sbranden
/dts/arm/qemu-virt/ @carlocaione
/dts/arm/st/ @erwango

43
dts/arm/atmel/pinctrl_atmel_sam.h Normal file
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@ -0,0 +1,43 @@
/*
* Copyright (c) 2020 Linaro Limited
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef PINCTRL_ATMEL_SAM_H_
#define PINCTRL_ATMEL_SAM_H_
#define PERIPH_a 0
#define PERIPH_b 1
#define PERIPH_c 2
#define PERIPH_d 3
#define PERIPH_e 4
#define PERIPH_f 5
#define PERIPH_g 6
/* Create a pincfg device tree node:
*
* The node name and nodelabel will be of the form:
*
* NODE = p<port><pin><periph>_<inst>_<signal>
*
* NODE: NODE {
* atmel,pins = < &pio<port> <pin> PERIPH_<perip> >;
* }
*
* So for example:
*
* DT_ATMEL_PIN(uart, urxd, a, 8, a);
*
* Will become:
*
* pa8a_uart_urxd: pa8a_uart_urxd {
* atmel,pins = <&pioa 8 PERIPH_a>;
* }
*
*/
#define DT_ATMEL_PIN(inst, signal, port, pin, periph) \
p##port##pin##periph##_##inst##_##signal: \
p##port##pin##periph##_##inst##_##signal { \
atmel,pins = < &pio##port pin PERIPH_##periph >; }
#endif /* PINCTRL_ATMEL_SAM_H_ */

32
dts/arm/atmel/sam3x-pinctrl.dtsi Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "pinctrl_atmel_sam.h"
/ {
soc {
pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(uart, urxd, a, 8, a);
DT_ATMEL_PIN(uart, utxd, a, 9, a);
DT_ATMEL_PIN(usart0, cts0, b, 26, a);
DT_ATMEL_PIN(usart0, rts0, b, 25, a);
DT_ATMEL_PIN(usart0, rxd0, a, 10, a);
DT_ATMEL_PIN(usart0, sck0, a, 17, b);
DT_ATMEL_PIN(usart0, txd0, a, 11, a);
DT_ATMEL_PIN(usart1, cts1, a, 15, a);
DT_ATMEL_PIN(usart1, rts1, a, 14, a);
DT_ATMEL_PIN(usart1, rxd1, a, 12, a);
DT_ATMEL_PIN(usart1, sck1, a, 16, a);
DT_ATMEL_PIN(usart1, txd1, a, 13, a);
DT_ATMEL_PIN(usart2, cts2, b, 23, a);
DT_ATMEL_PIN(usart2, rts2, b, 22, a);
DT_ATMEL_PIN(usart2, rxd2, b, 21, a);
DT_ATMEL_PIN(usart2, sck2, b, 24, a);
DT_ATMEL_PIN(usart2, txd2, b, 20, a);
};
};
};

3
dts/arm/atmel/sam3x.dtsi
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@ -7,6 +7,8 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include "sam3x-pinctrl.dtsi"
/ {
aliases {
watchdog0 = &wdt;
@ -86,6 +88,7 @@
peripheral-id = <8>;
status = "disabled";
label = "UART_0";
pinctrl-0 = <&pa8a_uart_urxd &pa9a_uart_utxd>;
};
usart0: usart@40098000 {

33
dts/arm/atmel/sam4e-pinctrl.dtsi Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "pinctrl_atmel_sam.h"
/ {
soc {
pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, a, 5, c);
DT_ATMEL_PIN(uart1, utxd1, a, 6, c);
DT_ATMEL_PIN(usart0, cts0, b, 2, c);
DT_ATMEL_PIN(usart0, rts0, b, 3, c);
DT_ATMEL_PIN(usart0, rxd0, b, 0, c);
DT_ATMEL_PIN(usart0, sck0, b, 13, c);
DT_ATMEL_PIN(usart0, txd0, b, 1, c);
DT_ATMEL_PIN(usart1, cts1, a, 25, a);
DT_ATMEL_PIN(usart1, dcd1, a, 26, a);
DT_ATMEL_PIN(usart1, dsr1, a, 28, a);
DT_ATMEL_PIN(usart1, dtr1, a, 27, a);
DT_ATMEL_PIN(usart1, ri1, a, 29, a);
DT_ATMEL_PIN(usart1, rts1, a, 24, a);
DT_ATMEL_PIN(usart1, rxd1, a, 21, a);
DT_ATMEL_PIN(usart1, sck1, a, 23, a);
DT_ATMEL_PIN(usart1, txd1, a, 22, a);
};
};
};

4
dts/arm/atmel/sam4e.dtsi
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@ -8,6 +8,8 @@
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include "sam4e-pinctrl.dtsi"
/ {
aliases {
watchdog0 = &wdt;
@ -96,6 +98,7 @@
peripheral-id = <7>;
status = "disabled";
label = "UART_0";
pinctrl-0 = <&pa9a_uart0_urxd0 &pa10a_uart0_utxd0>;
};
uart1: uart@40060600 {
@ -105,6 +108,7 @@
peripheral-id = <45>;
status = "disabled";
label = "UART_1";
pinctrl-0 = <&pa5c_uart1_urxd1 &pa6c_uart1_utxd1>;
};
usart0: usart@400a0000 {

33
dts/arm/atmel/sam4s-pinctrl.dtsi Normal file
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@ -0,0 +1,33 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "pinctrl_atmel_sam.h"
/ {
soc {
pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, b, 2, a);
DT_ATMEL_PIN(uart1, utxd1, b, 3, a);
DT_ATMEL_PIN(usart0, cts0, a, 8, a);
DT_ATMEL_PIN(usart0, rts0, a, 7, a);
DT_ATMEL_PIN(usart0, rxd0, a, 5, a);
DT_ATMEL_PIN(usart0, sck0, a, 2, b);
DT_ATMEL_PIN(usart0, txd0, a, 6, a);
DT_ATMEL_PIN(usart1, cts1, a, 25, a);
DT_ATMEL_PIN(usart1, dcd1, a, 26, a);
DT_ATMEL_PIN(usart1, dsr1, a, 28, a);
DT_ATMEL_PIN(usart1, dtr1, a, 27, a);
DT_ATMEL_PIN(usart1, ri1, a, 29, a);
DT_ATMEL_PIN(usart1, rts1, a, 24, a);
DT_ATMEL_PIN(usart1, rxd1, a, 21, a);
DT_ATMEL_PIN(usart1, sck1, a, 23, a);
DT_ATMEL_PIN(usart1, txd1, a, 22, a);
};
};
};

4
dts/arm/atmel/sam4s.dtsi
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@ -9,6 +9,8 @@
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include "sam4s-pinctrl.dtsi"
/ {
aliases {
watchdog0 = &wdt;
@ -97,6 +99,7 @@
peripheral-id = <8>;
status = "disabled";
label = "UART_0";
pinctrl-0 = <&pa9a_uart0_urxd0 &pa10a_uart0_utxd0>;
};
uart1: uart@400e0800 {
@ -106,6 +109,7 @@
peripheral-id = <9>;
status = "disabled";
label = "UART_1";
pinctrl-0 = <&pb2a_uart1_urxd1 &pb3a_uart1_utxd1>;
};
usart0: usart@40024000 {

57
dts/arm/atmel/same70-pinctrl.dtsi Normal file
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@ -0,0 +1,57 @@
/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "pinctrl_atmel_sam.h"
/ {
soc {
pinctrl@400e0e00 {
/* instance, signal, pio, pin, peripheral */
DT_ATMEL_PIN(uart0, urxd0, a, 9, a);
DT_ATMEL_PIN(uart0, utxd0, a, 10, a);
DT_ATMEL_PIN(uart1, urxd1, a, 5, c);
DT_ATMEL_PIN(uart1, utxd1, a, 4, c);
DT_ATMEL_PIN(uart1, utxd1, a, 6, c);
DT_ATMEL_PIN(uart1, utxd1, d, 26, d);
DT_ATMEL_PIN(uart2, urxd2, d, 25, c);
DT_ATMEL_PIN(uart2, utxd2, d, 26, c);
DT_ATMEL_PIN(uart3, urxd3, d, 28, a);
DT_ATMEL_PIN(uart3, utxd3, d, 30, a);
DT_ATMEL_PIN(uart3, utxd3, d, 31, b);
DT_ATMEL_PIN(uart4, urxd4, d, 18, c);
DT_ATMEL_PIN(uart4, utxd4, d, 3, c);
DT_ATMEL_PIN(uart4, utxd4, d, 19, c);
DT_ATMEL_PIN(usart0, cts0, b, 2, c);
DT_ATMEL_PIN(usart0, dcd0, d, 0, d);
DT_ATMEL_PIN(usart0, dsr0, d, 2, d);
DT_ATMEL_PIN(usart0, dtr0, d, 1, d);
DT_ATMEL_PIN(usart0, ri0, d, 3, d);
DT_ATMEL_PIN(usart0, rts0, b, 3, c);
DT_ATMEL_PIN(usart0, rxd0, b, 0, c);
DT_ATMEL_PIN(usart0, sck0, b, 13, c);
DT_ATMEL_PIN(usart0, txd0, b, 1, c);
DT_ATMEL_PIN(usart1, cts1, a, 25, a);
DT_ATMEL_PIN(usart1, dcd1, a, 26, a);
DT_ATMEL_PIN(usart1, dsr1, a, 28, a);
DT_ATMEL_PIN(usart1, dtr1, a, 27, a);
DT_ATMEL_PIN(usart1, loncol1, a, 3, b);
DT_ATMEL_PIN(usart1, ri1, a, 29, a);
DT_ATMEL_PIN(usart1, rts1, a, 24, a);
DT_ATMEL_PIN(usart1, rxd1, a, 21, a);
DT_ATMEL_PIN(usart1, sck1, a, 23, a);
DT_ATMEL_PIN(usart1, txd1, b, 4, d);
DT_ATMEL_PIN(usart2, cts2, d, 19, b);
DT_ATMEL_PIN(usart2, dcd2, d, 4, d);
DT_ATMEL_PIN(usart2, dsr2, d, 6, d);
DT_ATMEL_PIN(usart2, dtr2, d, 5, d);
DT_ATMEL_PIN(usart2, ri2, d, 7, d);
DT_ATMEL_PIN(usart2, rts2, d, 18, b);
DT_ATMEL_PIN(usart2, rxd2, d, 15, b);
DT_ATMEL_PIN(usart2, sck2, d, 17, b);
DT_ATMEL_PIN(usart2, txd2, d, 16, b);
};
};
};

6
dts/arm/atmel/same70.dtsi
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@ -9,6 +9,8 @@
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include "same70-pinctrl.dtsi"
/ {
aliases {
watchdog0 = &wdt;
@ -136,6 +138,7 @@
peripheral-id = <7>;
status = "disabled";
label = "UART_0";
pinctrl-0 = <&pa9a_uart0_urxd0 &pa10a_uart0_utxd0>;
};
uart1: uart@400e0a00 {
@ -181,6 +184,7 @@
peripheral-id = <13>;
status = "disabled";
label = "USART_0";
pinctrl-0 = <&pb0c_usart0_rxd0 &pb1c_usart0_txd0>;
};
usart1: usart@40028000 {
@ -190,6 +194,7 @@
peripheral-id = <14>;
status = "disabled";
label = "USART_1";
pinctrl-0 = <&pa21a_usart1_rxd1 &pb4d_usart1_txd1>;
};
usart2: usart@4002c000 {
@ -199,6 +204,7 @@
peripheral-id = <15>;
status = "disabled";
label = "USART_2";
pinctrl-0 = <&pd15b_usart2_rxd2 &pd16b_usart2_txd2>;
};
afec0: adc@4003c000 {

6
dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
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@ -14,3 +14,9 @@ properties:
"#size-cells":
required: true
const: 1
child-binding:
description: atmel pins
properties:
"atmel,pins":
type: phandle-array

13
dts/bindings/serial/atmel,sam-uart.yaml
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@ -15,3 +15,16 @@ properties:
type: int
description: peripheral ID
required: true
pinctrl-0:
type: phandles
description: |
PIO pin configuration for URXD & UTRD signals. We expect that
the phandles will reference pinctrl nodes. These nodes will
have a nodelabel that matches the Atmel SoC HAL defines and
be of the form p<port><pin><periph>_<inst>_<signal>.
For example the UART on SAM3x would be
pinctrl-0 = <&pa8a_uart_urxd &pa9a_uart_utxd>;
required: true

13
dts/bindings/serial/atmel,sam-usart.yaml
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@ -15,3 +15,16 @@ properties:
type: int
description: peripheral ID
required: true
pinctrl-0:
type: phandles
description: |
PIO pin configuration for RXD & TRD signals. We expect that
the phandles will reference pinctrl nodes. These nodes will
have a nodelabel that matches the Atmel SoC HAL defines and
be of the form p<port><pin><periph>_<inst>_<signal>.
For example the USART0 on SAME7x would be
pinctrl-0 = <&pb0c_usart0_rxd0 &pb1c_usart0_txd0>;
required: true