drivers: eth: Update sam/sam0 eth drivers to use pinctrl

This update Atmel sam and sam0 ethernet gmac and mdio drivers to use
pinctrl driver and API. It updates all boards with new pinctrl groups
format.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>

boards/arm/atsame54_xpro/atsame54_xpro-pinctrl.dtsi

@@ -12,6 +12,26 @@
 		};
 	};
 
+	gmac_rmii: gmac_rmii {
+		group1 {
+			pinmux = <PA14L_GMAC_GTXCK>,
+				 <PA17L_GMAC_GTXEN>,
+				 <PA18L_GMAC_GTX0>,
+				 <PA19L_GMAC_GTX1>,
+				 <PC20L_GMAC_GRXDV>,
+				 <PA13L_GMAC_GRX0>,
+				 <PA12L_GMAC_GRX1>,
+				 <PA15L_GMAC_GRXER>;
+		};
+	};
+
+	mdio_default: mdio_default {
+		group1 {
+			pinmux = <PC11L_GMAC_GMDC>,
+				 <PC12L_GMAC_GMDIO>;
+		};
+	};
+
 	sercom7_i2c_default: sercom7_i2c_default {
 		group1 {
 			pinmux = <PD8C_SERCOM7_PAD0>,

boards/arm/atsame54_xpro/atsame54_xpro.dts

@@ -119,6 +119,9 @@ zephyr_udc0: &usb0 {
 	status = "okay";
 	zephyr,random-mac-address;
 
+	pinctrl-0 = <&gmac_rmii>;
+	pinctrl-names = "default";
+
 	phy: phy {
 		compatible = "ethernet-phy";
 		status = "okay";
@@ -129,4 +132,7 @@ zephyr_udc0: &usb0 {
 
 &mdio {
 	status = "okay";
+
+	pinctrl-0 = <&mdio_default>;
+	pinctrl-names = "default";
 };

boards/arm/atsame54_xpro/pinmux.c

@@ -30,19 +30,6 @@ static int board_pinmux_init(const struct device *dev)
 		return -ENXIO;
 	}
 
-#if (DT_NODE_HAS_STATUS(DT_NODELABEL(gmac), okay) && CONFIG_ETH_SAM_GMAC)
-	pinmux_pin_set(muxa, 14, PINMUX_FUNC_L);	/* PA14 = GTXCK */
-	pinmux_pin_set(muxa, 17, PINMUX_FUNC_L);	/* PA17 = GTXEN */
-	pinmux_pin_set(muxa, 18, PINMUX_FUNC_L);	/* PA18 = GTX0 */
-	pinmux_pin_set(muxa, 19, PINMUX_FUNC_L);	/* PA19 = GTX1 */
-	pinmux_pin_set(muxc, 20, PINMUX_FUNC_L);	/* PC20 = GRXDV */
-	pinmux_pin_set(muxa, 13, PINMUX_FUNC_L);	/* PA13 = GRX0 */
-	pinmux_pin_set(muxa, 12, PINMUX_FUNC_L);	/* PA12 = GRX1 */
-	pinmux_pin_set(muxa, 15, PINMUX_FUNC_L);	/* PA15 = GRXER */
-	pinmux_pin_set(muxc, 11, PINMUX_FUNC_L);	/* PC11 = GMDC */
-	pinmux_pin_set(muxc, 12, PINMUX_FUNC_L);	/* PC12 = GMDIO */
-#endif
-
 	return 0;
 }
 

boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi

@@ -6,6 +6,33 @@
 #include <dt-bindings/pinctrl/sam4eXe-pinctrl.h>
 
 &pinctrl {
+	gmac_mii: gmac_mii {
+		group1 {
+			pinmux = <PD0A_GMAC_GTXCK>,
+				 <PD1A_GMAC_GTXEN>,
+				 <PD2A_GMAC_GTX0>,
+				 <PD3A_GMAC_GTX1>,
+				 <PD15A_GMAC_GTX2>,
+				 <PD16A_GMAC_GTX3>,
+				 <PD4A_GMAC_GRXDV>,
+				 <PD5A_GMAC_GRX0>,
+				 <PD6A_GMAC_GRX1>,
+				 <PD11A_GMAC_GRX2>,
+				 <PD12A_GMAC_GRX3>,
+				 <PD7A_GMAC_GRXER>,
+				 <PD14A_GMAC_GRXCK>,
+				 <PD13A_GMAC_GCOL>,
+				 <PD10A_GMAC_GCRS>;
+		};
+	};
+
+	mdio_default: mdio_default {
+		group1 {
+			pinmux = <PD8A_GMAC_GMDC>,
+				 <PD9A_GMAC_GMDIO>;
+		};
+	};
+
 	spi0_default: spi0_default {
 		group1 {
 			pinmux = <PA12A_SPI_MISO>,

boards/arm/sam4e_xpro/sam4e_xpro.dts

@@ -165,6 +165,10 @@
 
 &gmac {
 	status = "okay";
+
+	pinctrl-0 = <&gmac_mii>;
+	pinctrl-names = "default";
+
 	zephyr,random-mac-address;
 
 	phy: phy {
@@ -177,6 +181,9 @@
 
 &mdio {
 	status = "okay";
+
+	pinctrl-0 = <&mdio_default>;
+	pinctrl-names = "default";
 };
 
 &wdt {

boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi

@@ -112,6 +112,9 @@ zephyr_udc0: &usbhs {
 &gmac {
 	status = "okay";
 
+	pinctrl-0 = <&gmac_rmii>;
+	pinctrl-names = "default";
+
 	phy: phy {
 		compatible = "ethernet-phy";
 		status = "okay";
@@ -122,6 +125,9 @@ zephyr_udc0: &usbhs {
 
 &mdio {
 	status = "okay";
+
+	pinctrl-0 = <&mdio_default>;
+	pinctrl-names = "default";
 };
 
 &pwm0 {

boards/arm/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi

@@ -27,6 +27,26 @@
 		};
 	};
 
+	gmac_rmii: gmac_rmii {
+		group1 {
+			pinmux = <PD0A_GMAC_GTXCK>,
+				 <PD1A_GMAC_GTXEN>,
+				 <PD2A_GMAC_GTX0>,
+				 <PD3A_GMAC_GTX1>,
+				 <PD4A_GMAC_GRXDV>,
+				 <PD5A_GMAC_GRX0>,
+				 <PD6A_GMAC_GRX1>,
+				 <PD7A_GMAC_GRXER>;
+		};
+	};
+
+	mdio_default: mdio_default {
+		group1 {
+			pinmux = <PD8A_GMAC_GMDC>,
+				 <PD9A_GMAC_GMDIO>;
+		};
+	};
+
 	pwm_default: pwm_default {
 		group1 {
 			pinmux = <PA0A_PWMC0_PWMH0>,

boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi

@@ -220,6 +220,9 @@ zephyr_udc0: &usbhs {
 &gmac {
 	status = "okay";
 
+	pinctrl-0 = <&gmac_rmii>;
+	pinctrl-names = "default";
+
 	phy: phy {
 		compatible = "ethernet-phy";
 		status = "okay";
@@ -230,6 +233,9 @@ zephyr_udc0: &usbhs {
 
 &mdio {
 	status = "okay";
+
+	pinctrl-0 = <&mdio_default>;
+	pinctrl-names = "default";
 };
 
 &pwm0 {

boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi

@@ -27,6 +27,26 @@
 		};
 	};
 
+	gmac_rmii: gmac_rmii {
+		group1 {
+			pinmux = <PD0A_GMAC_GTXCK>,
+				 <PD1A_GMAC_GTXEN>,
+				 <PD2A_GMAC_GTX0>,
+				 <PD3A_GMAC_GTX1>,
+				 <PD4A_GMAC_GRXDV>,
+				 <PD5A_GMAC_GRX0>,
+				 <PD6A_GMAC_GRX1>,
+				 <PD7A_GMAC_GRXER>;
+		};
+	};
+
+	mdio_default: mdio_default {
+		group1 {
+			pinmux = <PD8A_GMAC_GMDC>,
+				 <PD9A_GMAC_GMDIO>;
+		};
+	};
+
 	pwm_default: pwm_default {
 		group1 {
 			pinmux = <PA0A_PWMC0_PWMH0>,

drivers/ethernet/eth_sam_gmac.c

@@ -42,6 +42,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #include <net/ethernet.h>
 #include <ethernet/eth_stats.h>
 #include <drivers/i2c.h>
+#include <drivers/pinctrl.h>
 #include <soc.h>
 #include "eth_sam_gmac_priv.h"
 
@@ -1767,6 +1768,7 @@ static void queue5_isr(const struct device *dev)
 static int eth_initialize(const struct device *dev)
 {
 	const struct eth_sam_dev_cfg *const cfg = dev->config;
+	int retval;
 
 	cfg->config_func();
 
@@ -1774,15 +1776,15 @@ static int eth_initialize(const struct device *dev)
 	/* Enable GMAC module's clock */
 	soc_pmc_peripheral_enable(cfg->periph_id);
 
-	/* Connect pins to the peripheral */
-	soc_gpio_list_configure(cfg->pin_list, cfg->pin_list_size);
 #else
 	/* Enable MCLK clock on GMAC */
 	MCLK->AHBMASK.reg |= MCLK_AHBMASK_GMAC;
 	*MCLK_GMAC |= MCLK_GMAC_MASK;
 #endif
+	/* Connect pins to the peripheral */
+	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 
-	return 0;
+	return retval;
 }
 
 #ifdef CONFIG_ETH_SAM_GMAC_MAC_I2C_EEPROM
@@ -2203,16 +2205,13 @@ static void eth0_irq_config(void)
 #endif
 }
 
-#ifdef CONFIG_SOC_FAMILY_SAM
+PINCTRL_DT_INST_DEFINE(0);
-static const struct soc_gpio_pin pins_eth0[] = ATMEL_SAM_DT_INST_PINS(0);
-#endif
 
 static const struct eth_sam_dev_cfg eth0_config = {
 	.regs = (Gmac *)DT_INST_REG_ADDR(0),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 #ifdef CONFIG_SOC_FAMILY_SAM
 	.periph_id = DT_INST_PROP_OR(0, peripheral_id, 0),
-	.pin_list = pins_eth0,
-	.pin_list_size = ARRAY_SIZE(pins_eth0),
 #endif
 	.config_func = eth0_irq_config,
 #if DT_NODE_EXISTS(DT_CHILD(DT_DRV_INST(0), phy))

drivers/ethernet/eth_sam_gmac_priv.h

@@ -261,10 +261,9 @@ struct gmac_queue {
 /* Device constant configuration parameters */
 struct eth_sam_dev_cfg {
 	Gmac *regs;
+	const struct pinctrl_dev_config *pcfg;
 #ifdef CONFIG_SOC_FAMILY_SAM
 	uint32_t periph_id;
-	const struct soc_gpio_pin *pin_list;
-	uint32_t pin_list_size;
 #endif
 	void (*config_func)(void);
 	const struct device *phy_dev;

drivers/mdio/mdio_sam.c

@@ -11,6 +11,7 @@
 #include <init.h>
 #include <soc.h>
 #include <drivers/mdio.h>
+#include <drivers/pinctrl.h>
 
 #include <logging/log.h>
 LOG_MODULE_REGISTER(mdio_sam, CONFIG_MDIO_LOG_LEVEL);
@@ -28,6 +29,7 @@ struct mdio_sam_dev_data {
 
 struct mdio_sam_dev_config {
 	Gmac * const regs;
+	const struct pinctrl_dev_config *pcfg;
 	int protocol;
 };
 
@@ -109,11 +111,15 @@ static void mdio_sam_bus_disable(const struct device *dev)
 
 static int mdio_sam_initialize(const struct device *dev)
 {
+	const struct mdio_sam_dev_config *const cfg = dev->config;
 	struct mdio_sam_dev_data *const data = dev->data;
+	int retval;
 
 	k_sem_init(&data->sem, 1, 1);
 
-	return 0;
+	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+
+	return retval;
 }
 
 static const struct mdio_driver_api mdio_sam_driver_api = {
@@ -126,10 +132,12 @@ static const struct mdio_driver_api mdio_sam_driver_api = {
 #define MDIO_SAM_CONFIG(n)						\
 static const struct mdio_sam_dev_config mdio_sam_dev_config_##n = {	\
 	.regs = (Gmac *)DT_REG_ADDR(DT_INST_PARENT(n)),			\
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	.protocol = DT_INST_ENUM_IDX(n, protocol),			\
 };
 
 #define MDIO_SAM_DEVICE(n)						\
+	PINCTRL_DT_INST_DEFINE(n);					\
 	MDIO_SAM_CONFIG(n);						\
 	static struct mdio_sam_dev_data mdio_sam_dev_data##n;		\
 	DEVICE_DT_INST_DEFINE(n,					\

dts/arm/atmel/sam4e.dtsi

@@ -151,16 +151,6 @@
 			phy-connection-type = "mii";
 			label = "GMAC";
 			status = "disabled";
-			/* Default to MII config */
-			pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
-				     &pd2a_gmac_gtx0 &pd3a_gmac_gtx1
-				     &pd15a_gmac_gtx2 &pd16a_gmac_gtx3
-				     &pd4a_gmac_grxdv &pd7a_gmac_grxer
-				     &pd14a_gmac_grxck &pd5a_gmac_grx0
-				     &pd6a_gmac_grx1 &pd11a_gmac_grx2
-				     &pd12a_gmac_grx3 &pd13a_gmac_gcol
-				     &pd10a_gmac_gcrs &pd8a_gmac_gmdc
-				     &pd9a_gmac_gmdio>;
 
 			mdio: mdio {
 				compatible = "atmel,sam-mdio";

dts/arm/atmel/same70.dtsi

@@ -347,17 +347,11 @@
 			local-mac-address = [00 00 00 00 00 00];
 			label = "GMAC";
 			status = "disabled";
-			/* Default to RMII config */
-			pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
-				     &pd2a_gmac_gtx0 &pd3a_gmac_gtx1
-				     &pd4a_gmac_grxdv &pd5a_gmac_grx0
-				     &pd6a_gmac_grx1 &pd7a_gmac_grxer>;
 
 			mdio: mdio {
 				compatible = "atmel,sam-mdio";
 				label = "MDIO";
 				status = "disabled";
-				pinctrl-0 = <&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
 			};
 		};
 

dts/bindings/ethernet/atmel,gmac-common.yaml

@@ -2,7 +2,9 @@
 # Copyright (c) 2020-2021 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-include: ethernet.yaml
+include:
+    - name: ethernet.yaml
+    - name: pinctrl-device.yaml
 
 properties:
     reg:
@@ -50,24 +52,3 @@ properties:
         represents Reduced Media-Independent Interface (RMII) mode.
 
         This property must be used with pinctrl-0.
-
-    pinctrl-0:
-      type: phandles
-      required: false
-      description: |
-        PIO pin configuration for the various GMAC signals that include GTXCK,
-        GTXEN, GTX[3..0], GTXER, GRXCK, GRXDV, GRX[3..0], GRXER, GCRS, GCOL,
-        GMDC, and GMDIO.  Which signals are used vary based on if the PHY
-        connection is MII or RMII (see datasheet for more details).  We expect
-        that the phandles will reference pinctrl nodes.  These nodes will have
-        a nodelabel that matches the Atmel SoC HAL defines and be of the form
-        p<port><pin><periph>_<inst>_<signal>.
-
-        For example the GMAC on SAME7x would be for RMII
-          pinctrl-0 = <&pd0a_gmac_gtxck &pd1a_gmac_gtxen
-                       &pd2a_gmac_gtx0 &pd3a_gmac_gtx1
-                       &pd4a_gmac_grxdv &pd5a_gmac_grx0
-                       &pd6a_gmac_grx1 &pd7a_gmac_grxer
-                       &pd8a_gmac_gmdc &pd9a_gmac_gmdio>;
-
-        This property must be used with phy-connection-type.

dts/bindings/mdio/atmel,sam-mdio.yaml

@@ -5,14 +5,6 @@ description: Atmel SAM Family MDIO Driver node
 
 compatible: "atmel,sam-mdio"
 
-include: mdio-controller.yaml
+include:
-
+    - name: mdio-controller.yaml
-properties:
+    - name: pinctrl-device.yaml
-    pinctrl-0:
-      type: phandles
-      required: false
-      description: |
-        PIO pin configuration for MDC, and MDIO signals.
-
-        For example the GMAC on SAME7x would be
-          pinctrl-0 = <&pd8a_gmac_gmdc &pd9a_gmac_gmdio>;