drivers: pinctrl: add TI CC32XX driver
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been tested, just implemented following datasheet specs and checked that it compiles. Consider this as a best-effort driver to remove custom pinmux code in board files. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
c37deeb0c4
commit
c0bc9f974f
|
|
@ -31,3 +31,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
|
|||
zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
|
||||
zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_CC32XX pinctrl_ti_cc32xx.c)
|
||||
|
|
|
|||
|
|
@ -60,5 +60,6 @@ source "drivers/pinctrl/Kconfig.nxp_s32"
|
|||
source "drivers/pinctrl/Kconfig.gecko"
|
||||
source "drivers/pinctrl/Kconfig.ti_k3"
|
||||
source "drivers/pinctrl/Kconfig.emsdp"
|
||||
source "drivers/pinctrl/Kconfig.ti_cc32xx"
|
||||
|
||||
endif # PINCTRL
|
||||
|
|
|
|||
9
drivers/pinctrl/Kconfig.ti_cc32xx
Normal file
9
drivers/pinctrl/Kconfig.ti_cc32xx
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config PINCTRL_TI_CC32XX
|
||||
bool "TI CC32XX pinctrl driver"
|
||||
default y
|
||||
depends on DT_HAS_TI_CC32XX_PINCTRL_ENABLED
|
||||
help
|
||||
Enable the TI CC32XX pinctrl driver
|
||||
52
drivers/pinctrl/pinctrl_ti_cc32xx.c
Normal file
52
drivers/pinctrl/pinctrl_ti_cc32xx.c
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT ti_cc32xx_pinctrl
|
||||
|
||||
#include <zephyr/arch/cpu.h>
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/drivers/pinctrl.h>
|
||||
#include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
|
||||
|
||||
#define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU
|
||||
|
||||
/* pin to pad mapping (255 indicates invalid pin) */
|
||||
static const uint8_t pin2pad[] = {
|
||||
10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 255U, 255U, 18U, 19U, 20U,
|
||||
21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
|
||||
255U, 255U, 26U, 27U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U,
|
||||
255U, 255U, 255U, 255U, 255U, 31U, 255U, 255U, 255U, 255U, 0U, 255U, 32U,
|
||||
30U, 255U, 1U, 255U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
|
||||
};
|
||||
|
||||
static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg)
|
||||
{
|
||||
uint8_t pin;
|
||||
|
||||
pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK;
|
||||
if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
|
||||
{
|
||||
ARG_UNUSED(reg);
|
||||
|
||||
for (uint8_t i = 0U; i < pin_cnt; i++) {
|
||||
int ret;
|
||||
|
||||
ret = pinctrl_configure_pin(pins[i]);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -130,6 +130,11 @@
|
|||
interrupts = <EXP_WDT 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@4402e0a0 {
|
||||
compatible = "ti,cc32xx-pinctrl";
|
||||
reg = <0x4402e0a0 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
110
dts/bindings/pinctrl/ti,cc32xx-pinctrl.yaml
Normal file
110
dts/bindings/pinctrl/ti,cc32xx-pinctrl.yaml
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
# Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
The TI CC32XX pin controller is a singleton node responsible for controlling
|
||||
pin function selection and pin properties. For example, you can
|
||||
use this node to route UART0 RX to pin 55 and enable the pull-up resistor
|
||||
on the pin.
|
||||
|
||||
The node has the 'pinctrl' node label set in your SoC's devicetree,
|
||||
so you can modify it like this:
|
||||
|
||||
&pinctrl {
|
||||
/* your modifications go here */
|
||||
};
|
||||
|
||||
All device pin configurations should be placed in child nodes of the
|
||||
'pinctrl' node, as shown in this example:
|
||||
|
||||
/* You can put this in places like a board-pinctrl.dtsi file in
|
||||
* your board directory, or a devicetree overlay in your application.
|
||||
*/
|
||||
|
||||
/* include pre-defined combinations for the SoC variant used by the board */
|
||||
#include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
|
||||
|
||||
&pinctrl {
|
||||
/* configuration for the uart0 "default" state */
|
||||
uart0_default: uart0_default {
|
||||
/* group 1 */
|
||||
group1 {
|
||||
/* configure pin 55 as UART0 TX and pin 61 as UART0 CTS */
|
||||
pinmux = <UART0_TX_P55>, <UART0_CTS_P61>;
|
||||
};
|
||||
/* group 2 */
|
||||
group2 {
|
||||
/* configure pin 57 as UART0 RX and pin 62 as UART0 RTS */
|
||||
pinmux = <UART0_RX_P57>, <UART0_RTS_P62>;
|
||||
/* both pin 57 and 62 have pull-up enabled */
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
The 'uart0_default' child node encodes the pin configurations for a
|
||||
particular state of a device; in this case, the default (that is, active)
|
||||
state.
|
||||
|
||||
As shown, pin configurations are organized in groups within each child node.
|
||||
Each group can specify a list of pin function selections in the 'pinmux'
|
||||
property.
|
||||
|
||||
A group can also specify shared pin properties common to all the specified
|
||||
pins, such as the 'bias-pull-up' property in group 2. Here is a list of
|
||||
supported standard pin properties:
|
||||
|
||||
- drive-push-pull: Push-pull drive mode (default, not required).
|
||||
- drive-open-drain: Open-drain drive mode.
|
||||
- bias-disable: Disable pull-up/down (default, not required).
|
||||
- bias-pull-up: Enable pull-up resistor.
|
||||
- bias-pull-down: Enable pull-down resistor.
|
||||
- drive-strength: Configure drive strength in mA (defaults to 6mA, IC default).
|
||||
|
||||
Note that drive and bias options are mutually exclusive.
|
||||
|
||||
To link pin configurations with a device, use a pinctrl-N property for some
|
||||
number N, like this example you could place in your board's DTS file:
|
||||
|
||||
#include "board-pinctrl.dtsi"
|
||||
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_default>
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
compatible: "ti,cc32xx-pinctrl"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
child-binding:
|
||||
child-binding:
|
||||
include:
|
||||
- name: pincfg-node.yaml
|
||||
property-allowlist:
|
||||
- drive-push-pull
|
||||
- drive-open-drain
|
||||
- bias-disable
|
||||
- bias-pull-down
|
||||
- bias-pull-up
|
||||
- drive-strength
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
required: true
|
||||
type: array
|
||||
description: |
|
||||
An array of pins sharing the same group properties. The pins should
|
||||
be defined using pre-defined macros or, alternatively, using the
|
||||
TI_CC32XX_PINMUX helper macro.
|
||||
|
||||
drive-strength:
|
||||
default: 6
|
||||
enum:
|
||||
- 0
|
||||
- 2
|
||||
- 4
|
||||
- 6
|
||||
- 8
|
||||
- 10
|
||||
- 12
|
||||
- 14
|
||||
220
include/zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h
Normal file
220
include/zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h
Normal file
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright (c) 2021 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_
|
||||
|
||||
/*
|
||||
* The whole TI CC32XX pin configuration information is encoded in a 32-bit
|
||||
* bitfield organized as follows:
|
||||
*
|
||||
* - 31..22: Reserved
|
||||
* - 21..16: Pin.
|
||||
* - 15..10: Reserved.
|
||||
* - 9: Pull-down flag.
|
||||
* - 8: Pull-up flag.
|
||||
* - 7..5: Drive strength.
|
||||
* - 4: Enable open-drain flag.
|
||||
* - 3..0: Configuration mode
|
||||
*
|
||||
* Note that the lower bits (11..0) map directly to the MEM_GPIO_PAD_CONFIG
|
||||
* register.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @name TI CC32XX pin configuration bit field positions and masks.
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TI_CC32XX_PIN_MSK 0x3FU
|
||||
#define TI_CC32XX_PIN_POS 16U
|
||||
#define TI_CC32XX_MUX_MSK 0xFU
|
||||
#define TI_CC32XX_MUX_POS 0U
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Utility macro to build TI CC32XX pinmux property entry.
|
||||
*
|
||||
* @param pin Pin
|
||||
* @param mux Multiplexer choice
|
||||
*/
|
||||
#define TI_CC32XX_PINMUX(pin, mux) \
|
||||
((((pin)&TI_CC32XX_PIN_MSK) << TI_CC32XX_PIN_POS) | \
|
||||
(((mux)&TI_CC32XX_MUX_MSK) << TI_CC32XX_MUX_POS))
|
||||
|
||||
/**
|
||||
* @name TI CC32XX pinctrl pin functions (reference: SWRU465).
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO10_P1 TI_CC32XX_PINMUX(1U, 0U)
|
||||
#define I2C_SCL_P1 TI_CC32XX_PINMUX(1U, 1U)
|
||||
#define GT_PWM06_P1 TI_CC32XX_PINMUX(1U, 3U)
|
||||
#define UART1_TX_P1 TI_CC32XX_PINMUX(1U, 7U)
|
||||
#define SDCARD_CLK_P1 TI_CC32XX_PINMUX(1U, 6U)
|
||||
#define GT_CCP01_P1 TI_CC32XX_PINMUX(1U, 12U)
|
||||
|
||||
#define GPIO11_P2 TI_CC32XX_PINMUX(2U, 0U)
|
||||
#define I2C_SDA_P2 TI_CC32XX_PINMUX(2U, 1U)
|
||||
#define GT_PWM07_P2 TI_CC32XX_PINMUX(2U, 3U)
|
||||
#define PXCLK_P2 TI_CC32XX_PINMUX(2U, 4U)
|
||||
#define SDCARD_CMD_P2 TI_CC32XX_PINMUX(2U, 6U)
|
||||
#define UART1_RX_P2 TI_CC32XX_PINMUX(2U, 7U)
|
||||
#define GT_CCP02_P2 TI_CC32XX_PINMUX(2U, 12U)
|
||||
#define MCAFSX_P2 TI_CC32XX_PINMUX(2U, 13U)
|
||||
|
||||
#define GPIO12_P3 TI_CC32XX_PINMUX(3U, 0U)
|
||||
#define MCACLK_P3 TI_CC32XX_PINMUX(3U, 3U)
|
||||
#define PVS_P3 TI_CC32XX_PINMUX(3U, 4U)
|
||||
#define I2C_SCL_P3 TI_CC32XX_PINMUX(3U, 5U)
|
||||
#define UART0_TX_P3 TI_CC32XX_PINMUX(3U, 7U)
|
||||
#define GT_CCP03_P3 TI_CC32XX_PINMUX(3U, 12U)
|
||||
|
||||
#define GPIO13_P4 TI_CC32XX_PINMUX(4U, 0U)
|
||||
#define I2C_SDA_P4 TI_CC32XX_PINMUX(4U, 5U)
|
||||
#define PHS_P4 TI_CC32XX_PINMUX(4U, 4U)
|
||||
#define UART0_RX_P4 TI_CC32XX_PINMUX(4U, 7U)
|
||||
#define GT_CCP04_P4 TI_CC32XX_PINMUX(4U, 12U)
|
||||
|
||||
#define GPIO14_P5 TI_CC32XX_PINMUX(5U, 0U)
|
||||
#define I2C_SCL_P5 TI_CC32XX_PINMUX(5U, 5U)
|
||||
#define GSPI_CLK_P5 TI_CC32XX_PINMUX(5U, 7U)
|
||||
#define PDATA8_P5 TI_CC32XX_PINMUX(5U, 4U)
|
||||
#define GT_CCP05_P5 TI_CC32XX_PINMUX(5U, 12U)
|
||||
|
||||
#define GPIO15_P6 TI_CC32XX_PINMUX(6U, 0U)
|
||||
#define I2C_SDA_P6 TI_CC32XX_PINMUX(6U, 5U)
|
||||
#define GSPI_MISO_P6 TI_CC32XX_PINMUX(6U, 7U)
|
||||
#define PDATA9_P6 TI_CC32XX_PINMUX(6U, 4U)
|
||||
#define SDCARD_DATA3_P6 TI_CC32XX_PINMUX(6U, 8U)
|
||||
#define GT_CCP06_P6 TI_CC32XX_PINMUX(6U, 13U)
|
||||
|
||||
#define GPIO16_P7 TI_CC32XX_PINMUX(7U, 0U)
|
||||
#define GSPI_MOSI_P7 TI_CC32XX_PINMUX(7U, 7U)
|
||||
#define PDATA10_P7 TI_CC32XX_PINMUX(7U, 4U)
|
||||
#define UART1_TX_P7 TI_CC32XX_PINMUX(7U, 5U)
|
||||
#define SDCARD_CLK_P7 TI_CC32XX_PINMUX(7U, 8U)
|
||||
#define GT_CCP07_P7 TI_CC32XX_PINMUX(7U, 13U)
|
||||
|
||||
#define GPIO17_P8 TI_CC32XX_PINMUX(8U, 0U)
|
||||
#define UART1_RX_P8 TI_CC32XX_PINMUX(8U, 5U)
|
||||
#define GSPI_CS_P8 TI_CC32XX_PINMUX(8U, 7U)
|
||||
#define SDCARD_CMD_P8 TI_CC32XX_PINMUX(8U, 8U)
|
||||
#define PDATA11_P8 TI_CC32XX_PINMUX(8U, 4U)
|
||||
|
||||
#define GPIO22_P15 TI_CC32XX_PINMUX(15U, 0U)
|
||||
#define MCAFSX_P15 TI_CC32XX_PINMUX(15U, 7U)
|
||||
#define GT_CCP04_P15 TI_CC32XX_PINMUX(15U, 5U)
|
||||
|
||||
#define GPIO23_P16 TI_CC32XX_PINMUX(16U, 0U)
|
||||
#define TDI_P16 TI_CC32XX_PINMUX(16U, 1U)
|
||||
#define UART1_TX_P16 TI_CC32XX_PINMUX(16U, 2U)
|
||||
#define I2C_SCL_P16 TI_CC32XX_PINMUX(16U, 9U)
|
||||
|
||||
#define GPIO24_P17 TI_CC32XX_PINMUX(17U, 0U)
|
||||
#define TDO_P17 TI_CC32XX_PINMUX(17U, 1U)
|
||||
#define PWM0_P17 TI_CC32XX_PINMUX(17U, 5U)
|
||||
#define UART1_RX_P17 TI_CC32XX_PINMUX(17U, 2U)
|
||||
#define I2C_SDA_P17 TI_CC32XX_PINMUX(17U, 9U)
|
||||
#define GT_CCP06_P17 TI_CC32XX_PINMUX(17U, 4U)
|
||||
#define MCAFSX_P17 TI_CC32XX_PINMUX(17U, 6U)
|
||||
|
||||
#define GPIO28_P18 TI_CC32XX_PINMUX(18U, 0U)
|
||||
|
||||
#define TCK_P19 TI_CC32XX_PINMUX(19U, 1U)
|
||||
#define GT_PWM03_P19 TI_CC32XX_PINMUX(19U, 8U)
|
||||
|
||||
#define GPIO29_P20 TI_CC32XX_PINMUX(20U, 0U)
|
||||
#define TMS_P20 TI_CC32XX_PINMUX(20U, 1U)
|
||||
|
||||
#define GPIO25_P21 TI_CC32XX_PINMUX(21U, 0U)
|
||||
#define GT_PWM02_P21 TI_CC32XX_PINMUX(21U, 9U)
|
||||
#define MCASFX_P21 TI_CC32XX_PINMUX(21U, 2U)
|
||||
|
||||
#define ANTSEL1_P29 TI_CC32XX_PINMUX(29U, 0U)
|
||||
|
||||
#define ANTSEL2_P30 TI_CC32XX_PINMUX(30U, 0U)
|
||||
|
||||
#define GPIO31_P45 TI_CC32XX_PINMUX(45U, 0U)
|
||||
#define UART0_RX_P45 TI_CC32XX_PINMUX(45U, 9U)
|
||||
#define MCAFSX_P45 TI_CC32XX_PINMUX(45U, 12U)
|
||||
#define UART1_RX_P45 TI_CC32XX_PINMUX(45U, 2U)
|
||||
#define MCAXR0_P45 TI_CC32XX_PINMUX(45U, 6U)
|
||||
#define GSPI_CLK_P45 TI_CC32XX_PINMUX(45U, 7U)
|
||||
|
||||
#define GPIO0_P50 TI_CC32XX_PINMUX(50U, 0U)
|
||||
#define UART0_CTSN_P50 TI_CC32XX_PINMUX(50U, 12U)
|
||||
#define MCAXR1_P50 TI_CC32XX_PINMUX(50U, 6U)
|
||||
#define GT_CCP00_P50 TI_CC32XX_PINMUX(50U, 7U)
|
||||
#define GSPI_CS_P50 TI_CC32XX_PINMUX(50U, 9U)
|
||||
#define UART1_RTS_P50 TI_CC32XX_PINMUX(50U, 10U)
|
||||
#define UART0_RTS_P50 TI_CC32XX_PINMUX(50U, 3U)
|
||||
#define MCAXR0_P50 TI_CC32XX_PINMUX(50U, 4U)
|
||||
|
||||
#define GPIO32_P52 TI_CC32XX_PINMUX(52U, 0U)
|
||||
#define MCACLK_P52 TI_CC32XX_PINMUX(52U, 2U)
|
||||
#define MCAXR0_P52 TI_CC32XX_PINMUX(52U, 4U)
|
||||
#define UART0_RTS_P52 TI_CC32XX_PINMUX(52U, 6U)
|
||||
#define GSPI_MOSI_P52 TI_CC32XX_PINMUX(52U, 8U)
|
||||
|
||||
#define GPIO30_P53 TI_CC32XX_PINMUX(53U, 0U)
|
||||
#define UART0_TX_P53 TI_CC32XX_PINMUX(53U, 9U)
|
||||
#define MCACLK_P53 TI_CC32XX_PINMUX(53U, 2U)
|
||||
#define MCAFSX_P53 TI_CC32XX_PINMUX(53U, 3U)
|
||||
#define GT_CCP05_P53 TI_CC32XX_PINMUX(53U, 4U)
|
||||
#define GSPI_MISO_P53 TI_CC32XX_PINMUX(53U, 7U)
|
||||
|
||||
#define GPIO1_P55 TI_CC32XX_PINMUX(55U, 0U)
|
||||
#define UART0_TX_P55 TI_CC32XX_PINMUX(55U, 3U)
|
||||
#define PCLK_P55 TI_CC32XX_PINMUX(55U, 4U)
|
||||
#define UART1_TX_P55 TI_CC32XX_PINMUX(55U, 6U)
|
||||
#define GT_CCP01_P55 TI_CC32XX_PINMUX(55U, 7U)
|
||||
|
||||
#define GPIO2_P57 TI_CC32XX_PINMUX(57U, 0U)
|
||||
#define UART0_RX_P57 TI_CC32XX_PINMUX(57U, 3U)
|
||||
#define UART1_RX_P57 TI_CC32XX_PINMUX(57U, 6U)
|
||||
#define GT_CCP02_P57 TI_CC32XX_PINMUX(57U, 7U)
|
||||
|
||||
#define GPIO3_P58 TI_CC32XX_PINMUX(58U, 0U)
|
||||
#define UART1_TX_P58 TI_CC32XX_PINMUX(58U, 6U)
|
||||
#define PDATA7_P58 TI_CC32XX_PINMUX(58U, 7U)
|
||||
|
||||
#define GPIO5_P59 TI_CC32XX_PINMUX(59U, 0U)
|
||||
#define UART1_RX_P59 TI_CC32XX_PINMUX(59U, 6U)
|
||||
#define PDATA6_P59 TI_CC32XX_PINMUX(59U, 4U)
|
||||
|
||||
#define GPIO5_P60 TI_CC32XX_PINMUX(60U, 0U)
|
||||
#define PDATA5_P60 TI_CC32XX_PINMUX(60U, 4U)
|
||||
#define MCAXR1_P60 TI_CC32XX_PINMUX(60U, 6U)
|
||||
#define GT_CCP05_P60 TI_CC32XX_PINMUX(60U, 7U)
|
||||
|
||||
#define GPIO6_P61 TI_CC32XX_PINMUX(61U, 0U)
|
||||
#define UART0_RTS_P61 TI_CC32XX_PINMUX(61U, 5U)
|
||||
#define PDATA4_P61 TI_CC32XX_PINMUX(61U, 4U)
|
||||
#define UART1_CTS_P61 TI_CC32XX_PINMUX(61U, 3U)
|
||||
#define UART0_CTS_P61 TI_CC32XX_PINMUX(61U, 6U)
|
||||
#define GT_CCP06_P61 TI_CC32XX_PINMUX(61U, 7U)
|
||||
|
||||
#define GPIO7_P62 TI_CC32XX_PINMUX(62U, 0U)
|
||||
#define MCACLKX_P62 TI_CC32XX_PINMUX(62U, 13U)
|
||||
#define UART1_RTS_P62 TI_CC32XX_PINMUX(62U, 3U)
|
||||
#define UART0_RTS_P62 TI_CC32XX_PINMUX(62U, 10U)
|
||||
#define UART0_TX_P62 TI_CC32XX_PINMUX(62U, 11U)
|
||||
|
||||
#define GPIO8_P63 TI_CC32XX_PINMUX(63U, 0U)
|
||||
#define SDCARD_IRQ_P63 TI_CC32XX_PINMUX(63U, 6U)
|
||||
#define MCAFSX_P63 TI_CC32XX_PINMUX(63U, 7U)
|
||||
#define GT_CCP06_P63 TI_CC32XX_PINMUX(63U, 12U)
|
||||
|
||||
#define GPIO9_P64 TI_CC32XX_PINMUX(64U, 0U)
|
||||
#define GT_PWM05_P64 TI_CC32XX_PINMUX(64U, 3U)
|
||||
#define SDCARD_DATA_P64 TI_CC32XX_PINMUX(64U, 6U)
|
||||
#define MCAXR0_P64 TI_CC32XX_PINMUX(64U, 7U)
|
||||
#define GT_CCP00_P64 TI_CC32XX_PINMUX(64U, 12U)
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_TI_CC32XX_PINCTRL_H_ */
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_sources(soc.c)
|
||||
zephyr_include_directories(.)
|
||||
|
||||
if (DEFINED CONFIG_CC3220SF_DEBUG OR DEFINED CONFIG_CC3235SF_DEBUG)
|
||||
zephyr_linker_sources(ROM_START SORT_KEY 0 cc32xx_debug.ld)
|
||||
|
|
|
|||
71
soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h
Normal file
71
soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Nordic Semiconductor ASA
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_SOC_ARM_TI_SIMPLELINK_CC32XX_PINCTRL_SOC_H_
|
||||
#define ZEPHYR_SOC_ARM_TI_SIMPLELINK_CC32XX_PINCTRL_SOC_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <zephyr/devicetree.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @cond INTERNAL_HIDDEN */
|
||||
|
||||
/** Type for TI CC32XX pin. */
|
||||
typedef uint32_t pinctrl_soc_pin_t;
|
||||
|
||||
/**
|
||||
* @name TI CC32XX pin configuration bit field positions and masks.
|
||||
*/
|
||||
|
||||
#define TI_CC32XX_OPEN_DRAIN BIT(4)
|
||||
#define TI_CC32XX_DRIVE_STRENGTH_MSK 0x7U
|
||||
#define TI_CC32XX_DRIVE_STRENGTH_POS 5U
|
||||
#define TI_CC32XX_PULL_UP BIT(8)
|
||||
#define TI_CC32XX_PULL_DOWN BIT(9)
|
||||
#define TI_CC32XX_PAD_OUT_OVERRIDE BIT(10)
|
||||
#define TI_CC32XX_PAD_OUT_BUF_OVERRIDE BIT(11)
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize each pin.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name.
|
||||
* @param idx Property entry index.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
(DT_PROP_BY_IDX(node_id, prop, idx) | \
|
||||
(TI_CC32XX_OPEN_DRAIN * DT_PROP(node_id, drive_open_drain)) | \
|
||||
(TI_CC32XX_PULL_UP * DT_PROP(node_id, bias_pull_down)) | \
|
||||
(TI_CC32XX_PULL_DOWN * DT_PROP(node_id, bias_pull_up)) | \
|
||||
((DT_ENUM_IDX(node_id, drive_strength) & TI_CC32XX_DRIVE_STRENGTH_MSK) \
|
||||
<< TI_CC32XX_DRIVE_STRENGTH_POS) | \
|
||||
TI_CC32XX_PAD_OUT_OVERRIDE | TI_CC32XX_PAD_OUT_BUF_OVERRIDE),
|
||||
|
||||
/**
|
||||
* @brief Utility macro to initialize state pins contained in a given property.
|
||||
*
|
||||
* @param node_id Node identifier.
|
||||
* @param prop Property name describing state pins.
|
||||
*/
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{ \
|
||||
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT) \
|
||||
}
|
||||
|
||||
/** @endcond */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_TI_SIMPLELINK_CC32XX_PINCTRL_SOC_H_ */
|
||||
Loading…
Reference in a new issue