From c133e357efbed7a285b25764b586c97ba3d56ef9 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Fri, 4 Mar 2022 14:31:23 -0600 Subject: [PATCH] drivers: pinctrl: Add LPC IOCON pinctrl driver Add lpc iocon pinctrl driver. Driver handles IOCON clock initialization as well as IOCON pin configuration Signed-off-by: Daniel DeGrasse --- drivers/pinctrl/CMakeLists.txt | 1 + drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Kconfig.lpc_iocon | 11 ++++++ drivers/pinctrl/pinctrl_lpc_iocon.c | 57 +++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) create mode 100644 drivers/pinctrl/Kconfig.lpc_iocon create mode 100644 drivers/pinctrl/pinctrl_lpc_iocon.c diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index a922c5ee83..e2f2843840 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -16,3 +16,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 833ac288d9..bf4ef1f954 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -41,5 +41,6 @@ source "drivers/pinctrl/Kconfig.kinetis" source "drivers/pinctrl/Kconfig.xec" source "drivers/pinctrl/Kconfig.mcux" source "drivers/pinctrl/Kconfig.sifive" +source "drivers/pinctrl/Kconfig.lpc_iocon" endif # PINCTRL diff --git a/drivers/pinctrl/Kconfig.lpc_iocon b/drivers/pinctrl/Kconfig.lpc_iocon new file mode 100644 index 0000000000..7e84792644 --- /dev/null +++ b/drivers/pinctrl/Kconfig.lpc_iocon @@ -0,0 +1,11 @@ +# Copyright (c) 2022 NXP +# SPDX-License-Identifier: Apache-2.0 + +DT_COMPAT_NXP_LPC_PINCTRL := nxp,lpc-iocon-pinctrl + +config PINCTRL_NXP_IOCON + bool "IOCON Pin controller driver for NXP LPC MCUs" + depends on SOC_FAMILY_LPC + default $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_PINCTRL)) + help + Enable pin controller driver for NXP LPC MCUs diff --git a/drivers/pinctrl/pinctrl_lpc_iocon.c b/drivers/pinctrl/pinctrl_lpc_iocon.c new file mode 100644 index 0000000000..3323571787 --- /dev/null +++ b/drivers/pinctrl/pinctrl_lpc_iocon.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2022, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#define PORT(mux) (((mux) & 0xC0000000) >> 30) +#define PIN(mux) (((mux) & 0x3F000000) >> 24) +#define TYPE(mux) (((mux) & 0xC00000) >> 22) + +#define IOCON_TYPE_D 0x0 +#define IOCON_TYPE_I 0x1 +#define IOCON_TYPE_A 0x2 + +static IOCON_Type *iocon = (IOCON_Type *)DT_REG_ADDR(DT_NODELABEL(iocon)); + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, + uintptr_t reg) +{ + for (uint8_t i = 0; i < pin_cnt; i++) { + /* Check if this is an analog or i2c type pin */ + uint32_t pin_mux = pins[i]; + uint32_t port = PORT(pin_mux); + uint32_t pin = PIN(pin_mux); + + switch (TYPE(pin_mux)) { + case IOCON_TYPE_D: + pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK; + break; + case IOCON_TYPE_I: + pin_mux &= Z_PINCTRL_IOCON_I_PIN_MASK; + break; + case IOCON_TYPE_A: + pin_mux &= Z_PINCTRL_IOCON_A_PIN_MASK; + break; + default: + /* Should not occur */ + assert(TYPE(pin_mux <= IOCON_TYPE_A)); + } + /* Set pinmux */ + iocon->PIO[port][pin] = pin_mux; + } + return 0; +} + +static int pinctrl_clock_init(const struct device *dev) +{ + ARG_UNUSED(dev); + /* Enable IOCon clock */ + CLOCK_EnableClock(kCLOCK_Iocon); + return 0; +} + +SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);