diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt index 58a4b5838a..48ab9fc771 100644 --- a/drivers/dma/CMakeLists.txt +++ b/drivers/dma/CMakeLists.txt @@ -16,9 +16,9 @@ zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_LPC dma_mcux_lpc.c) zephyr_library_sources_ifdef(CONFIG_DMA_PL330 dma_pl330.c) zephyr_library_sources_ifdef(CONFIG_DMA_IPROC_PAX dma_iproc_pax_v1.c) zephyr_library_sources_ifdef(CONFIG_DMA_IPROC_PAX_V2 dma_iproc_pax_v2.c) -zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA dma_cavs_hda.c) -zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_HOST_IN dma_cavs_hda_host_in.c) -zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_HOST_OUT dma_cavs_hda_host_out.c) -zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_LINK_IN dma_cavs_hda_link_in.c) -zephyr_library_sources_ifdef(CONFIG_DMA_CAVS_HDA_LINK_OUT dma_cavs_hda_link_out.c) +zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_HDA dma_intel_adsp_hda.c) +zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_HDA_HOST_IN dma_intel_adsp_hda_host_in.c) +zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_HDA_HOST_OUT dma_intel_adsp_hda_host_out.c) +zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_HDA_LINK_IN dma_intel_adsp_hda_link_in.c) +zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_HDA_LINK_OUT dma_intel_adsp_hda_link_out.c) zephyr_library_sources_ifdef(CONFIG_DMA_INTEL_ADSP_GPDMA dma_intel_adsp_gpdma.c dma_dw_common.c) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 4b8e711e07..0b5534205f 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -46,6 +46,6 @@ source "drivers/dma/Kconfig.iproc_pax" source "drivers/dma/Kconfig.intel_adsp_gpdma" -source "drivers/dma/Kconfig.cavs_hda" +source "drivers/dma/Kconfig.intel_adsp_hda" endif # DMA diff --git a/drivers/dma/Kconfig.cavs_hda b/drivers/dma/Kconfig.cavs_hda deleted file mode 100644 index bcdb6ea729..0000000000 --- a/drivers/dma/Kconfig.cavs_hda +++ /dev/null @@ -1,47 +0,0 @@ -# cAVS HDA configuration options - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -DT_COMPAT_INTEL_CAVS_HDA_HOST_IN := intel,cavs-hda-host-in -DT_COMPAT_INTEL_CAVS_HDA_HOST_OUT := intel,cavs-hda-host-out -DT_COMPAT_INTEL_CAVS_HDA_LINK_IN := intel,cavs-hda-link-in -DT_COMPAT_INTEL_CAVS_HDA_LINK_OUT := intel,cavs-hda-link-out - -config DMA_CAVS_HDA_HOST_IN - bool "Intel cAVS HDA Host In DMA drivers" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_CAVS_HDA_HOST_IN)) - depends on DMA - select DMA_CAVS_HDA - help - Intel cAVS Host HDA DMA driver. - -config DMA_CAVS_HDA_HOST_OUT - bool "Intel cAVS HDA Host Out DMA drivers" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_CAVS_HDA_HOST_OUT)) - depends on DMA - select DMA_CAVS_HDA - help - Intel cAVS Host HDA DMA driver. - -config DMA_CAVS_HDA_LINK_IN - bool "Intel cAVS HDA Link In DMA drivers" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_CAVS_HDA_LINK_IN)) - depends on DMA - select DMA_CAVS_HDA - help - Intel cAVS Link In HDA DMA driver. - -config DMA_CAVS_HDA_LINK_OUT - bool "Intel cAVS HDA Link Out DMA drivers" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_CAVS_HDA_LINK_OUT)) - depends on DMA - select DMA_CAVS_HDA - help - Intel cAVS Link Out HDA DMA driver. - -config DMA_CAVS_HDA - bool - depends on DMA_CAVS_HDA_LINK_OUT || DMA_CAVS_HDA_LINK_IN || DMA_CAVS_HDA_HOST_OUT || DMA_CAVS_HDA_HOST_IN - help - Intel cAVS HDA DMA driver. diff --git a/drivers/dma/Kconfig.intel_adsp_hda b/drivers/dma/Kconfig.intel_adsp_hda new file mode 100644 index 0000000000..69e140c6de --- /dev/null +++ b/drivers/dma/Kconfig.intel_adsp_hda @@ -0,0 +1,47 @@ +# Intel ADSP HDA configuration options + +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +DT_COMPAT_INTEL_ADSP_HDA_HOST_IN := intel,adsp-hda-host-in +DT_COMPAT_INTEL_ADSP_HDA_HOST_OUT := intel,adsp-hda-host-out +DT_COMPAT_INTEL_ADSP_HDA_LINK_IN := intel,adsp-hda-link-in +DT_COMPAT_INTEL_ADSP_HDA_LINK_OUT := intel,adsp-hda-link-out + +config DMA_INTEL_ADSP_HDA_HOST_IN + bool "Intel ADSP HDA Host In DMA drivers" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HDA_HOST_IN)) + depends on DMA + select DMA_INTEL_ADSP_HDA + help + Intel ADSP Host HDA DMA driver. + +config DMA_INTEL_ADSP_HDA_HOST_OUT + bool "Intel ADSP HDA Host Out DMA drivers" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HDA_HOST_OUT)) + depends on DMA + select DMA_INTEL_ADSP_HDA + help + Intel ADSP Host HDA DMA driver. + +config DMA_INTEL_ADSP_HDA_LINK_IN + bool "Intel ADSP HDA Link In DMA drivers" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HDA_LINK_IN)) + depends on DMA + select DMA_INTEL_ADSP_HDA + help + Intel ADSP Link In HDA DMA driver. + +config DMA_INTEL_ADSP_HDA_LINK_OUT + bool "Intel ADSP HDA Link Out DMA drivers" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HDA_LINK_OUT)) + depends on DMA + select DMA_INTEL_ADSP_HDA + help + Intel ADSP Link Out HDA DMA driver. + +config DMA_INTEL_ADSP_HDA + bool + depends on DMA_INTEL_ADSP_HDA_LINK_OUT || DMA_INTEL_ADSP_HDA_LINK_IN || DMA_INTEL_ADSP_HDA_HOST_OUT || DMA_INTEL_ADSP_HDA_HOST_IN + help + Intel ADSP HDA DMA driver. diff --git a/drivers/dma/dma_cavs_hda.h b/drivers/dma/dma_cavs_hda.h deleted file mode 100644 index 5a1eb86052..0000000000 --- a/drivers/dma/dma_cavs_hda.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_DRIVERS_DMA_DMA_CAVS_HDA_COMMON_H_ -#define ZEPHYR_DRIVERS_DMA_DMA_CAVS_HDA_COMMON_H_ - -#define CAVS_HDA_MAX_CHANNELS DT_PROP(DT_NODELABEL(hda_host_out), dma_channels) - -#include - -struct cavs_hda_dma_data { - struct dma_context ctx; - - ATOMIC_DEFINE(channels_atomic, CAVS_HDA_MAX_CHANNELS); -}; - -struct cavs_hda_dma_cfg { - uint32_t base; - uint32_t dma_channels; - enum dma_channel_direction direction; -}; - -int cavs_hda_dma_host_in_config(const struct device *dev, - uint32_t channel, - struct dma_config *dma_cfg); - -int cavs_hda_dma_host_out_config(const struct device *dev, - uint32_t channel, - struct dma_config *dma_cfg); - -int cavs_hda_dma_link_in_config(const struct device *dev, - uint32_t channel, - struct dma_config *dma_cfg); - -int cavs_hda_dma_link_out_config(const struct device *dev, - uint32_t channel, - struct dma_config *dma_cfg); - -int cavs_hda_dma_link_reload(const struct device *dev, uint32_t channel, - uint32_t src, uint32_t dst, size_t size); - -int cavs_hda_dma_host_reload(const struct device *dev, uint32_t channel, - uint32_t src, uint32_t dst, size_t size); - -int cavs_hda_dma_status(const struct device *dev, uint32_t channel, - struct dma_status *stat); - -bool cavs_hda_dma_chan_filter(const struct device *dev, int channel, - void *filter_param); - -int cavs_hda_dma_start(const struct device *dev, uint32_t channel); - -int cavs_hda_dma_stop(const struct device *dev, uint32_t channel); - -int cavs_hda_dma_init(const struct device *dev); - - -#endif /* ZEPHYR_DRIVERS_DMA_DMA_CAVS_HDA_COMMON_H_ */ diff --git a/drivers/dma/dma_cavs_hda_host_in.c b/drivers/dma/dma_cavs_hda_host_in.c deleted file mode 100644 index 3d27e15882..0000000000 --- a/drivers/dma/dma_cavs_hda_host_in.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT intel_cavs_hda_host_in - -#include -#include "dma_cavs_hda.h" - -static const struct dma_driver_api cavs_hda_dma_host_in_api = { - .config = cavs_hda_dma_host_in_config, - .reload = cavs_hda_dma_host_reload, - .start = cavs_hda_dma_start, - .stop = cavs_hda_dma_stop, - .get_status = cavs_hda_dma_status, - .chan_filter = cavs_hda_dma_chan_filter, -}; - -#define CAVS_HDA_DMA_HOST_IN_INIT(inst) \ - static const struct cavs_hda_dma_cfg cavs_hda_dma##inst##_config = { \ - .base = DT_INST_REG_ADDR(inst), \ - .dma_channels = DT_INST_PROP(inst, dma_channels), \ - .direction = MEMORY_TO_HOST \ - }; \ - \ - static struct cavs_hda_dma_data cavs_hda_dma##inst##_data = {}; \ - \ - DEVICE_DT_INST_DEFINE(inst, &cavs_hda_dma_init, NULL, &cavs_hda_dma##inst##_data, \ - &cavs_hda_dma##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ - &cavs_hda_dma_host_in_api); - -DT_INST_FOREACH_STATUS_OKAY(CAVS_HDA_DMA_HOST_IN_INIT) diff --git a/drivers/dma/dma_cavs_hda_host_out.c b/drivers/dma/dma_cavs_hda_host_out.c deleted file mode 100644 index a8a729b2d9..0000000000 --- a/drivers/dma/dma_cavs_hda_host_out.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT intel_cavs_hda_host_out - -#include -#include "dma_cavs_hda.h" - -#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL -#include -LOG_MODULE_REGISTER(dma_cavs_hda_dma_host_out); - -static const struct dma_driver_api cavs_hda_dma_host_out_api = { - .config = cavs_hda_dma_host_out_config, - .reload = cavs_hda_dma_host_reload, - .start = cavs_hda_dma_start, - .stop = cavs_hda_dma_stop, - .get_status = cavs_hda_dma_status, - .chan_filter = cavs_hda_dma_chan_filter, -}; - -#define CAVS_HDA_DMA_HOST_OUT_INIT(inst) \ - static const struct cavs_hda_dma_cfg cavs_hda_dma##inst##_config = { \ - .base = DT_INST_REG_ADDR(inst), \ - .dma_channels = DT_INST_PROP(inst, dma_channels), \ - .direction = HOST_TO_MEMORY \ - }; \ - \ - static struct cavs_hda_dma_data cavs_hda_dma##inst##_data = {}; \ - \ - DEVICE_DT_INST_DEFINE(inst, &cavs_hda_dma_init, NULL, &cavs_hda_dma##inst##_data, \ - &cavs_hda_dma##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ - &cavs_hda_dma_host_out_api); - -DT_INST_FOREACH_STATUS_OKAY(CAVS_HDA_DMA_HOST_OUT_INIT) diff --git a/drivers/dma/dma_cavs_hda_link_in.c b/drivers/dma/dma_cavs_hda_link_in.c deleted file mode 100644 index fae9a6dd9d..0000000000 --- a/drivers/dma/dma_cavs_hda_link_in.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT intel_cavs_hda_link_in - -#include -#include "dma_cavs_hda.h" - -#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL -#include -LOG_MODULE_REGISTER(dma_cavs_hda_dma_link_in); - -static const struct dma_driver_api cavs_hda_dma_link_in_api = { - .config = cavs_hda_dma_link_in_config, - .reload = cavs_hda_dma_link_reload, - .start = cavs_hda_dma_start, - .stop = cavs_hda_dma_stop, - .get_status = cavs_hda_dma_status, - .chan_filter = cavs_hda_dma_chan_filter, -}; - -#define CAVS_HDA_DMA_LINK_IN_INIT(inst) \ - static const struct cavs_hda_dma_cfg cavs_hda_dma##inst##_config = { \ - .base = DT_INST_REG_ADDR(inst), \ - .dma_channels = DT_INST_PROP(inst, dma_channels), \ - .direction = PERIPHERAL_TO_MEMORY \ - }; \ - \ - static struct cavs_hda_dma_data cavs_hda_dma##inst##_data = {}; \ - \ - DEVICE_DT_INST_DEFINE(inst, &cavs_hda_dma_init, NULL, &cavs_hda_dma##inst##_data, \ - &cavs_hda_dma##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ - &cavs_hda_dma_link_in_api); - -DT_INST_FOREACH_STATUS_OKAY(CAVS_HDA_DMA_LINK_IN_INIT) diff --git a/drivers/dma/dma_cavs_hda_link_out.c b/drivers/dma/dma_cavs_hda_link_out.c deleted file mode 100644 index 396dc64865..0000000000 --- a/drivers/dma/dma_cavs_hda_link_out.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define DT_DRV_COMPAT intel_cavs_hda_link_out - -#include -#include "dma_cavs_hda.h" - -#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL -#include -LOG_MODULE_REGISTER(dma_cavs_hda_dma_link_out); - -static const struct dma_driver_api cavs_hda_dma_link_out_api = { - .config = cavs_hda_dma_link_out_config, - .reload = cavs_hda_dma_link_reload, - .start = cavs_hda_dma_start, - .stop = cavs_hda_dma_stop, - .get_status = cavs_hda_dma_status, - .chan_filter = cavs_hda_dma_chan_filter, -}; - -#define CAVS_HDA_DMA_LINK_OUT_INIT(inst) \ - static const struct cavs_hda_dma_cfg cavs_hda_dma##inst##_config = { \ - .base = DT_INST_REG_ADDR(inst), \ - .dma_channels = DT_INST_PROP(inst, dma_channels), \ - .direction = MEMORY_TO_PERIPHERAL \ - }; \ - \ - static struct cavs_hda_dma_data cavs_hda_dma##inst##_data = {}; \ - \ - DEVICE_DT_INST_DEFINE(inst, &cavs_hda_dma_init, NULL, &cavs_hda_dma##inst##_data, \ - &cavs_hda_dma##inst##_config, POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, \ - &cavs_hda_dma_link_out_api); - -DT_INST_FOREACH_STATUS_OKAY(CAVS_HDA_DMA_LINK_OUT_INIT) diff --git a/drivers/dma/dma_cavs_hda.c b/drivers/dma/dma_intel_adsp_hda.c similarity index 72% rename from drivers/dma/dma_cavs_hda.c rename to drivers/dma/dma_intel_adsp_hda.c index b7e4c1b97c..382a8c7767 100644 --- a/drivers/dma/dma_cavs_hda.c +++ b/drivers/dma/dma_intel_adsp_hda.c @@ -5,7 +5,7 @@ */ /** - * @brief Intel CAVS HDA DMA (Stream) driver + * @brief Intel ADSP HDA DMA (Stream) driver * * HDA is effectively, from the DSP, a ringbuffer (fifo) where the read * and write positions are maintained by the hardware and the software may @@ -24,20 +24,20 @@ #include -#include "dma_cavs_hda.h" +#include "dma_intel_adsp_hda.h" /* Define low level driver required values */ #define HDA_HOST_IN_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_in), reg, 0) #define HDA_HOST_OUT_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 0) #define HDA_STREAM_COUNT DT_PROP(DT_NODELABEL(hda_host_out), dma_channels) #define HDA_REGBLOCK_SIZE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 1) -#include +#include -int cavs_hda_dma_host_in_config(const struct device *dev, +int intel_adsp_hda_dma_host_in_config(const struct device *dev, uint32_t channel, struct dma_config *dma_cfg) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; struct dma_block_config *blk_cfg; uint8_t *buf; int res; @@ -52,7 +52,7 @@ int cavs_hda_dma_host_in_config(const struct device *dev, blk_cfg = dma_cfg->head_block; buf = (uint8_t *)(uintptr_t)(blk_cfg->source_address); - res = cavs_hda_set_buffer(cfg->base, channel, buf, + res = intel_adsp_hda_set_buffer(cfg->base, channel, buf, blk_cfg->block_size); if (res == 0) { @@ -68,11 +68,11 @@ int cavs_hda_dma_host_in_config(const struct device *dev, } -int cavs_hda_dma_host_out_config(const struct device *dev, +int intel_adsp_hda_dma_host_out_config(const struct device *dev, uint32_t channel, struct dma_config *dma_cfg) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; struct dma_block_config *blk_cfg; uint8_t *buf; int res; @@ -88,7 +88,7 @@ int cavs_hda_dma_host_out_config(const struct device *dev, blk_cfg = dma_cfg->head_block; buf = (uint8_t *)(uintptr_t)(blk_cfg->dest_address); - res = cavs_hda_set_buffer(cfg->base, channel, buf, + res = intel_adsp_hda_set_buffer(cfg->base, channel, buf, blk_cfg->block_size); if (res == 0) { @@ -103,11 +103,11 @@ int cavs_hda_dma_host_out_config(const struct device *dev, return res; } -int cavs_hda_dma_link_in_config(const struct device *dev, +int intel_adsp_hda_dma_link_in_config(const struct device *dev, uint32_t channel, struct dma_config *dma_cfg) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; struct dma_block_config *blk_cfg; uint8_t *buf; int res; @@ -122,7 +122,7 @@ int cavs_hda_dma_link_in_config(const struct device *dev, blk_cfg = dma_cfg->head_block; buf = (uint8_t *)(uintptr_t)(blk_cfg->source_address); - res = cavs_hda_set_buffer(cfg->base, channel, buf, + res = intel_adsp_hda_set_buffer(cfg->base, channel, buf, blk_cfg->block_size); if (res == 0 && dma_cfg->source_data_size <= 3) { @@ -134,11 +134,11 @@ int cavs_hda_dma_link_in_config(const struct device *dev, } -int cavs_hda_dma_link_out_config(const struct device *dev, +int intel_adsp_hda_dma_link_out_config(const struct device *dev, uint32_t channel, struct dma_config *dma_cfg) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; struct dma_block_config *blk_cfg; uint8_t *buf; int res; @@ -154,7 +154,7 @@ int cavs_hda_dma_link_out_config(const struct device *dev, blk_cfg = dma_cfg->head_block; buf = (uint8_t *)(uintptr_t)(blk_cfg->dest_address); - res = cavs_hda_set_buffer(cfg->base, channel, buf, + res = intel_adsp_hda_set_buffer(cfg->base, channel, buf, blk_cfg->block_size); if (res == 0 && dma_cfg->dest_data_size <= 3) { @@ -166,38 +166,38 @@ int cavs_hda_dma_link_out_config(const struct device *dev, } -int cavs_hda_dma_link_reload(const struct device *dev, uint32_t channel, +int intel_adsp_hda_dma_link_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst, size_t size) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); - cavs_hda_link_commit(cfg->base, channel, size); + intel_adsp_hda_link_commit(cfg->base, channel, size); return 0; } -int cavs_hda_dma_host_reload(const struct device *dev, uint32_t channel, +int intel_adsp_hda_dma_host_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst, size_t size) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); - cavs_hda_host_commit(cfg->base, channel, size); + intel_adsp_hda_host_commit(cfg->base, channel, size); return 0; } -int cavs_hda_dma_status(const struct device *dev, uint32_t channel, +int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel, struct dma_status *stat) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); - uint32_t unused = cavs_hda_unused(cfg->base, channel); + uint32_t unused = intel_adsp_hda_unused(cfg->base, channel); uint32_t used = *DGBS(cfg->base, channel) - unused; stat->dir = cfg->direction; @@ -210,7 +210,7 @@ int cavs_hda_dma_status(const struct device *dev, uint32_t channel, return 0; } -bool cavs_hda_dma_chan_filter(const struct device *dev, int channel, void *filter_param) +bool intel_adsp_hda_dma_chan_filter(const struct device *dev, int channel, void *filter_param) { uint32_t requested_channel; @@ -227,35 +227,35 @@ bool cavs_hda_dma_chan_filter(const struct device *dev, int channel, void *filte return false; } -int cavs_hda_dma_start(const struct device *dev, uint32_t channel) +int intel_adsp_hda_dma_start(const struct device *dev, uint32_t channel) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); - cavs_hda_enable(cfg->base, channel); + intel_adsp_hda_enable(cfg->base, channel); return 0; } -int cavs_hda_dma_stop(const struct device *dev, uint32_t channel) +int intel_adsp_hda_dma_stop(const struct device *dev, uint32_t channel) { - const struct cavs_hda_dma_cfg *const cfg = dev->config; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; __ASSERT(channel < cfg->dma_channels, "Channel does not exist"); - cavs_hda_disable(cfg->base, channel); + intel_adsp_hda_disable(cfg->base, channel); return 0; } -int cavs_hda_dma_init(const struct device *dev) +int intel_adsp_hda_dma_init(const struct device *dev) { - struct cavs_hda_dma_data *data = dev->data; - const struct cavs_hda_dma_cfg *const cfg = dev->config; + struct intel_adsp_hda_dma_data *data = dev->data; + const struct intel_adsp_hda_dma_cfg *const cfg = dev->config; for (uint32_t i = 0; i < cfg->dma_channels; i++) { - cavs_hda_init(cfg->base, i); + intel_adsp_hda_init(cfg->base, i); } data->ctx.dma_channels = cfg->dma_channels; diff --git a/drivers/dma/dma_intel_adsp_hda.h b/drivers/dma/dma_intel_adsp_hda.h new file mode 100644 index 0000000000..e0ef2d4897 --- /dev/null +++ b/drivers/dma/dma_intel_adsp_hda.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_DRIVERS_DMA_INTEL_ADSP_HDA_COMMON_H_ +#define ZEPHYR_DRIVERS_DMA_INTEL_ADSP_HDA_COMMON_H_ + +#define INTEL_ADSP_HDA_MAX_CHANNELS DT_PROP(DT_NODELABEL(hda_host_out), dma_channels) + +#include + +struct intel_adsp_hda_dma_data { + struct dma_context ctx; + + ATOMIC_DEFINE(channels_atomic, INTEL_ADSP_HDA_MAX_CHANNELS); +}; + +struct intel_adsp_hda_dma_cfg { + uint32_t base; + uint32_t dma_channels; + enum dma_channel_direction direction; +}; + +int intel_adsp_hda_dma_host_in_config(const struct device *dev, + uint32_t channel, + struct dma_config *dma_cfg); + +int intel_adsp_hda_dma_host_out_config(const struct device *dev, + uint32_t channel, + struct dma_config *dma_cfg); + +int intel_adsp_hda_dma_link_in_config(const struct device *dev, + uint32_t channel, + struct dma_config *dma_cfg); + +int intel_adsp_hda_dma_link_out_config(const struct device *dev, + uint32_t channel, + struct dma_config *dma_cfg); + +int intel_adsp_hda_dma_link_reload(const struct device *dev, uint32_t channel, + uint32_t src, uint32_t dst, size_t size); + +int intel_adsp_hda_dma_host_reload(const struct device *dev, uint32_t channel, + uint32_t src, uint32_t dst, size_t size); + +int intel_adsp_hda_dma_status(const struct device *dev, uint32_t channel, + struct dma_status *stat); + +bool intel_adsp_hda_dma_chan_filter(const struct device *dev, int channel, + void *filter_param); + +int intel_adsp_hda_dma_start(const struct device *dev, uint32_t channel); + +int intel_adsp_hda_dma_stop(const struct device *dev, uint32_t channel); + +int intel_adsp_hda_dma_init(const struct device *dev); + + +#endif /* ZEPHYR_DRIVERS_DMA_INTEL_ADSP_HDA_COMMON_H_ */ diff --git a/drivers/dma/dma_intel_adsp_hda_host_in.c b/drivers/dma/dma_intel_adsp_hda_host_in.c new file mode 100644 index 0000000000..c23c77dd40 --- /dev/null +++ b/drivers/dma/dma_intel_adsp_hda_host_in.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT intel_adsp_hda_host_in + +#include +#include "dma_intel_adsp_hda.h" + +static const struct dma_driver_api intel_adsp_hda_dma_host_in_api = { + .config = intel_adsp_hda_dma_host_in_config, + .reload = intel_adsp_hda_dma_host_reload, + .start = intel_adsp_hda_dma_start, + .stop = intel_adsp_hda_dma_stop, + .get_status = intel_adsp_hda_dma_status, + .chan_filter = intel_adsp_hda_dma_chan_filter, +}; + +#define INTEL_ADSP_HDA_DMA_HOST_IN_INIT(inst) \ + static const struct intel_adsp_hda_dma_cfg intel_adsp_hda_dma##inst##_config = { \ + .base = DT_INST_REG_ADDR(inst), \ + .dma_channels = DT_INST_PROP(inst, dma_channels), \ + .direction = MEMORY_TO_HOST \ + }; \ + \ + static struct intel_adsp_hda_dma_data intel_adsp_hda_dma##inst##_data = {}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, NULL, \ + &intel_adsp_hda_dma##inst##_data, \ + &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ + CONFIG_DMA_INIT_PRIORITY, \ + &intel_adsp_hda_dma_host_in_api); + +DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_IN_INIT) diff --git a/drivers/dma/dma_intel_adsp_hda_host_out.c b/drivers/dma/dma_intel_adsp_hda_host_out.c new file mode 100644 index 0000000000..03e3034291 --- /dev/null +++ b/drivers/dma/dma_intel_adsp_hda_host_out.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT intel_adsp_hda_host_out + +#include +#include "dma_intel_adsp_hda.h" + +#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL +#include +LOG_MODULE_REGISTER(dma_intel_adsp_hda_dma_host_out); + +static const struct dma_driver_api intel_adsp_hda_dma_host_out_api = { + .config = intel_adsp_hda_dma_host_out_config, + .reload = intel_adsp_hda_dma_host_reload, + .start = intel_adsp_hda_dma_start, + .stop = intel_adsp_hda_dma_stop, + .get_status = intel_adsp_hda_dma_status, + .chan_filter = intel_adsp_hda_dma_chan_filter, +}; + +#define INTEL_ADSP_HDA_DMA_HOST_OUT_INIT(inst) \ + static const struct intel_adsp_hda_dma_cfg intel_adsp_hda_dma##inst##_config = { \ + .base = DT_INST_REG_ADDR(inst), \ + .dma_channels = DT_INST_PROP(inst, dma_channels), \ + .direction = HOST_TO_MEMORY \ + }; \ + \ + static struct intel_adsp_hda_dma_data intel_adsp_hda_dma##inst##_data = {}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, NULL, \ + &intel_adsp_hda_dma##inst##_data, \ + &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ + CONFIG_DMA_INIT_PRIORITY, \ + &intel_adsp_hda_dma_host_out_api); + +DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_OUT_INIT) diff --git a/drivers/dma/dma_intel_adsp_hda_link_in.c b/drivers/dma/dma_intel_adsp_hda_link_in.c new file mode 100644 index 0000000000..d91a7461ab --- /dev/null +++ b/drivers/dma/dma_intel_adsp_hda_link_in.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT intel_adsp_hda_link_in + +#include +#include "dma_intel_adsp_hda.h" + +#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL +#include +LOG_MODULE_REGISTER(dma_intel_adsp_hda_dma_link_in); + +static const struct dma_driver_api intel_adsp_hda_dma_link_in_api = { + .config = intel_adsp_hda_dma_link_in_config, + .reload = intel_adsp_hda_dma_link_reload, + .start = intel_adsp_hda_dma_start, + .stop = intel_adsp_hda_dma_stop, + .get_status = intel_adsp_hda_dma_status, + .chan_filter = intel_adsp_hda_dma_chan_filter, +}; + +#define INTEL_ADSP_HDA_DMA_LINK_IN_INIT(inst) \ + static const struct intel_adsp_hda_dma_cfg intel_adsp_hda_dma##inst##_config = { \ + .base = DT_INST_REG_ADDR(inst), \ + .dma_channels = DT_INST_PROP(inst, dma_channels), \ + .direction = PERIPHERAL_TO_MEMORY \ + }; \ + \ + static struct intel_adsp_hda_dma_data intel_adsp_hda_dma##inst##_data = {}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, NULL, \ + &intel_adsp_hda_dma##inst##_data, \ + &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ + CONFIG_DMA_INIT_PRIORITY, \ + &intel_adsp_hda_dma_link_in_api); + +DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_LINK_IN_INIT) diff --git a/drivers/dma/dma_intel_adsp_hda_link_out.c b/drivers/dma/dma_intel_adsp_hda_link_out.c new file mode 100644 index 0000000000..3c0ca80619 --- /dev/null +++ b/drivers/dma/dma_intel_adsp_hda_link_out.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2022 Intel Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT intel_adsp_hda_link_out + +#include +#include "dma_intel_adsp_hda.h" + +#define LOG_LEVEL CONFIG_DMA_LOG_LEVEL +#include +LOG_MODULE_REGISTER(dma_intel_adsp_hda_dma_link_out); + +static const struct dma_driver_api intel_adsp_hda_dma_link_out_api = { + .config = intel_adsp_hda_dma_link_out_config, + .reload = intel_adsp_hda_dma_link_reload, + .start = intel_adsp_hda_dma_start, + .stop = intel_adsp_hda_dma_stop, + .get_status = intel_adsp_hda_dma_status, + .chan_filter = intel_adsp_hda_dma_chan_filter, +}; + +#define INTEL_ADSP_HDA_DMA_LINK_OUT_INIT(inst) \ + static const struct intel_adsp_hda_dma_cfg intel_adsp_hda_dma##inst##_config = { \ + .base = DT_INST_REG_ADDR(inst), \ + .dma_channels = DT_INST_PROP(inst, dma_channels), \ + .direction = MEMORY_TO_PERIPHERAL \ + }; \ + \ + static struct intel_adsp_hda_dma_data intel_adsp_hda_dma##inst##_data = {}; \ + \ + DEVICE_DT_INST_DEFINE(inst, &intel_adsp_hda_dma_init, NULL, \ + &intel_adsp_hda_dma##inst##_data, \ + &intel_adsp_hda_dma##inst##_config, POST_KERNEL, \ + CONFIG_DMA_INIT_PRIORITY, \ + &intel_adsp_hda_dma_link_out_api); + +DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_LINK_OUT_INIT) diff --git a/dts/bindings/dma/intel,adsp-hda-host-in.yaml b/dts/bindings/dma/intel,adsp-hda-host-in.yaml new file mode 100644 index 0000000000..a86a10bd55 --- /dev/null +++ b/dts/bindings/dma/intel,adsp-hda-host-in.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Intel Corporation. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel ADSP HDA Host In controller + +compatible: "intel,adsp-hda-host-in" + +include: intel,adsp-hda.yaml diff --git a/dts/bindings/dma/intel,adsp-hda-host-out.yaml b/dts/bindings/dma/intel,adsp-hda-host-out.yaml new file mode 100644 index 0000000000..c9480bb4fb --- /dev/null +++ b/dts/bindings/dma/intel,adsp-hda-host-out.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Intel Corporation. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel ADSP HDA Host Out controller + +compatible: "intel,adsp-hda-host-out" + +include: intel,adsp-hda.yaml diff --git a/dts/bindings/dma/intel,adsp-hda-link-in.yaml b/dts/bindings/dma/intel,adsp-hda-link-in.yaml new file mode 100644 index 0000000000..845398e059 --- /dev/null +++ b/dts/bindings/dma/intel,adsp-hda-link-in.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Intel Corporation. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel ADSP HDA Link In controller + +compatible: "intel,adsp-hda-link-in" + +include: intel,adsp-hda.yaml diff --git a/dts/bindings/dma/intel,adsp-hda-link-out.yaml b/dts/bindings/dma/intel,adsp-hda-link-out.yaml new file mode 100644 index 0000000000..31f1140850 --- /dev/null +++ b/dts/bindings/dma/intel,adsp-hda-link-out.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Intel Corporation. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel ADSP HDA Link Out controller + +compatible: "intel,adsp-hda-link-out" + +include: intel,adsp-hda.yaml diff --git a/dts/bindings/dma/intel,cavs-hda.yaml b/dts/bindings/dma/intel,adsp-hda.yaml similarity index 85% rename from dts/bindings/dma/intel,cavs-hda.yaml rename to dts/bindings/dma/intel,adsp-hda.yaml index f08fba3cb1..bca18ef76e 100644 --- a/dts/bindings/dma/intel,cavs-hda.yaml +++ b/dts/bindings/dma/intel,adsp-hda.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Intel Corporation. All rights reserved. # SPDX-License-Identifier: Apache-2.0 -# Common fields for HDA DMA controllers +# Common fields for Intel ADSP HDA DMA controllers include: dma-controller.yaml diff --git a/dts/bindings/dma/intel,cavs-hda-host-in.yaml b/dts/bindings/dma/intel,cavs-hda-host-in.yaml deleted file mode 100644 index da50fdbc7f..0000000000 --- a/dts/bindings/dma/intel,cavs-hda-host-in.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -description: Intel cAVS HDA Host In controller - -compatible: "intel,cavs-hda-host-in" - -include: intel,cavs-hda.yaml diff --git a/dts/bindings/dma/intel,cavs-hda-host-out.yaml b/dts/bindings/dma/intel,cavs-hda-host-out.yaml deleted file mode 100644 index cb92f0fda6..0000000000 --- a/dts/bindings/dma/intel,cavs-hda-host-out.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -description: Intel cAVS HDA Host Out controller - -compatible: "intel,cavs-hda-host-out" - -include: intel,cavs-hda.yaml diff --git a/dts/bindings/dma/intel,cavs-hda-link-in.yaml b/dts/bindings/dma/intel,cavs-hda-link-in.yaml deleted file mode 100644 index c15b341c27..0000000000 --- a/dts/bindings/dma/intel,cavs-hda-link-in.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -description: Intel cAVS HDA Link In controller - -compatible: "intel,cavs-hda-link-in" - -include: intel,cavs-hda.yaml diff --git a/dts/bindings/dma/intel,cavs-hda-link-out.yaml b/dts/bindings/dma/intel,cavs-hda-link-out.yaml deleted file mode 100644 index ba31ca704e..0000000000 --- a/dts/bindings/dma/intel,cavs-hda-link-out.yaml +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -description: Intel cAVS HDA Link Out controller - -compatible: "intel,cavs-hda-link-out" - -include: intel,cavs-hda.yaml diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index 17eb533c64..347fc02d58 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -240,7 +240,7 @@ }; hda_host_out: dma@72800 { - compatible = "intel,cavs-hda-host-out"; + compatible = "intel,adsp-hda-host-out"; #dma-cells = <1>; reg = <0x00072800 0x40>; dma-channels = <9>; @@ -250,7 +250,7 @@ }; hda_host_in: dma@72c00 { - compatible = "intel,cavs-hda-host-in"; + compatible = "intel,adsp-hda-host-in"; #dma-cells = <1>; reg = <0x00072c00 0x40>; dma-channels = <10>; @@ -260,7 +260,7 @@ }; hda_link_out: dma@72400 { - compatible = "intel,cavs-hda-link-out"; + compatible = "intel,adsp-hda-link-out"; #dma-cells = <1>; reg = <0x00072400 0x40>; dma-channels = <9>; @@ -270,7 +270,7 @@ }; hda_link_in: dma@72600 { - compatible = "intel,cavs-hda-link-in"; + compatible = "intel,adsp-hda-link-in"; #dma-cells = <1>; reg = <0x00072600 0x40>; dma-channels = <10>; diff --git a/dts/xtensa/intel/intel_cavs.dtsi b/dts/xtensa/intel/intel_cavs.dtsi index 1b3ee3948f..eef270617f 100644 --- a/dts/xtensa/intel/intel_cavs.dtsi +++ b/dts/xtensa/intel/intel_cavs.dtsi @@ -33,7 +33,7 @@ }; hda_link_out: dma@72400 { - compatible = "intel,cavs-hda-link-out"; + compatible = "intel,adsp-hda-link-out"; #dma-cells = <1>; reg = <0x00072400 0x40>; dma-channels = <4>; @@ -44,7 +44,7 @@ }; hda_link_in: dma@72600 { - compatible = "intel,cavs-hda-link-in"; + compatible = "intel,adsp-hda-link-in"; #dma-cells = <1>; reg = <0x00072600 0x40>; dma-channels = <4>; @@ -55,7 +55,7 @@ }; hda_host_out: dma@72800 { - compatible = "intel,cavs-hda-host-out"; + compatible = "intel,adsp-hda-host-out"; #dma-cells = <1>; reg = <0x00072800 0x40>; dma-channels = <9>; @@ -66,7 +66,7 @@ }; hda_host_in: dma@72c00 { - compatible = "intel,cavs-hda-host-in"; + compatible = "intel,adsp-hda-host-in"; #dma-cells = <1>; reg = <0x00072c00 0x40>; dma-channels = <7>; diff --git a/dts/xtensa/intel/intel_cavs15.dtsi b/dts/xtensa/intel/intel_cavs15.dtsi index 28fdf0ec73..f7b92e5366 100644 --- a/dts/xtensa/intel/intel_cavs15.dtsi +++ b/dts/xtensa/intel/intel_cavs15.dtsi @@ -160,7 +160,7 @@ }; hda_link_out: dma@2400 { - compatible = "intel,cavs-hda-link-out"; + compatible = "intel,adsp-hda-link-out"; #dma-cells = <1>; reg = <0x00002400 0x40>; dma-channels = <2>; @@ -171,7 +171,7 @@ }; hda_link_in: dma@2600 { - compatible = "intel,cavs-hda-link-in"; + compatible = "intel,adsp-hda-link-in"; #dma-cells = <1>; reg = <0x00002600 0x40>; dma-channels = <2>; @@ -182,7 +182,7 @@ }; hda_host_out: dma@2800 { - compatible = "intel,cavs-hda-host-out"; + compatible = "intel,adsp-hda-host-out"; #dma-cells = <1>; reg = <0x00002800 0x40>; dma-channels = <6>; @@ -193,7 +193,7 @@ }; hda_host_in: dma@2c00 { - compatible = "intel,cavs-hda-host-in"; + compatible = "intel,adsp-hda-host-in"; #dma-cells = <1>; reg = <0x00002c00 0x40>; dma-channels = <7>; diff --git a/include/zephyr/logging/log_backend_cavs_hda.h b/include/zephyr/logging/log_backend_adsp_hda.h similarity index 66% rename from include/zephyr/logging/log_backend_cavs_hda.h rename to include/zephyr/logging/log_backend_adsp_hda.h index 6e4f4960d6..055225eb6b 100644 --- a/include/zephyr/logging/log_backend_cavs_hda.h +++ b/include/zephyr/logging/log_backend_adsp_hda.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_LOG_BACKEND_CAVS_HDA_H_ -#define ZEPHYR_LOG_BACKEND_CAVS_HDA_H_ +#ifndef ZEPHYR_LOG_BACKEND_ADSP_HDA_H_ +#define ZEPHYR_LOG_BACKEND_ADSP_HDA_H_ #include @@ -15,18 +15,18 @@ * When the log is flushed and written with DMA an IPC message should * be sent to inform the host. This hook function pointer allows for that */ -typedef void(*cavs_hda_log_hook_t)(uint32_t written); +typedef void(*adsp_hda_log_hook_t)(uint32_t written); /** - * @brief Initialize the cavs hda logger + * @brief Initialize the Intel ADSP HDA logger * - * @param hook Function is called after each hda flush in order to + * @param hook Function is called after each HDA flush in order to * inform the Host of DMA log data. This hook may be called * from multiple CPUs and multiple calling contexts concurrently. * It is up to the author of the hook to serialize if needed. * It is guaranteed to be called once for every flush. * @param channel HDA stream (DMA Channel) to use for logging */ -void cavs_hda_log_init(cavs_hda_log_hook_t hook, uint32_t channel); +void adsp_hda_log_init(adsp_hda_log_hook_t hook, uint32_t channel); -#endif /* ZEPHYR_LOG_BACKEND_CAVS_HDA_H_ */ +#endif /* ZEPHYR_LOG_BACKEND_ADSP_HDA_H_ */ diff --git a/soc/xtensa/intel_adsp/common/include/cavs_hda.h b/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h similarity index 88% rename from soc/xtensa/intel_adsp/common/include/cavs_hda.h rename to soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h index 2dc53bd2ce..d1ff2d340a 100644 --- a/soc/xtensa/intel_adsp/common/include/cavs_hda.h +++ b/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h @@ -2,8 +2,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#ifndef ZEPHYR_INCLUDE_CAVS_HDA_H -#define ZEPHYR_INCLUDE_CAVS_HDA_H +#ifndef ZEPHYR_INCLUDE_INTEL_ADSP_HDA_H +#define ZEPHYR_INCLUDE_INTEL_ADSP_HDA_H #include #include @@ -12,9 +12,9 @@ #include /** - * @brief HDA stream functionality for cAVS + * @brief HDA stream functionality for Intel ADSP * - * Provides low level calls to support cAVS HDA streams with + * Provides low level calls to support Intel ADSP HDA streams with * minimal abstraction that allows testing the hardware * and its demands separately from the intended DMA API * usage. The only requirement is that you define the base @@ -99,7 +99,7 @@ * @param base Base address of the IP register block * @param sid Stream ID */ -#define cavs_hda_dbg(name, base, sid) \ +#define intel_adsp_hda_dbg(name, base, sid) \ printk("%s:%u %s(%u:0x%p), dgcs: 0x%x, dgbba 0x%x, " \ "dgbs %u, dgbrp %u, dgbwp %u, dgbsp %u, " \ "dgmbs %u, dgbllpi 0x%x, dglpibi 0x%x\n", \ @@ -123,7 +123,7 @@ * @param hda Stream set to work with * @param sid Stream ID */ -static inline void cavs_hda_init(uint32_t base, uint32_t sid) +static inline void intel_adsp_hda_init(uint32_t base, uint32_t sid) { *DGCS(base, sid) |= DGCS_FWCB; } @@ -147,7 +147,7 @@ static inline void cavs_hda_init(uint32_t base, uint32_t sid) * @retval -EINVAL if the buf is not in L2, buf isn't aligned on 128 byte boundaries * @retval 0 on Success */ -static inline int cavs_hda_set_buffer(uint32_t base, uint32_t sid, +static inline int intel_adsp_hda_set_buffer(uint32_t base, uint32_t sid, uint8_t *buf, uint32_t buf_size) { /* While we don't actually care if the pointer is in the cached @@ -188,7 +188,7 @@ static inline int cavs_hda_set_buffer(uint32_t base, uint32_t sid, * @param hda HDA stream set * @param sid Stream ID */ -static inline void cavs_hda_enable(uint32_t base, uint32_t sid) +static inline void intel_adsp_hda_enable(uint32_t base, uint32_t sid) { *DGCS(base, sid) |= DGCS_GEN | DGCS_FIFORDY; } @@ -199,7 +199,7 @@ static inline void cavs_hda_enable(uint32_t base, uint32_t sid) * @param hda HDA stream set * @param sid Stream ID */ -static inline void cavs_hda_disable(uint32_t base, uint32_t sid) +static inline void intel_adsp_hda_disable(uint32_t base, uint32_t sid) { *DGCS(base, sid) &= ~(DGCS_GEN | DGCS_FIFORDY); } @@ -214,7 +214,7 @@ static inline void cavs_hda_disable(uint32_t base, uint32_t sid) * * @retval n Number of unused bytes */ -static inline uint32_t cavs_hda_unused(uint32_t base, uint32_t sid) +static inline uint32_t intel_adsp_hda_unused(uint32_t base, uint32_t sid) { uint32_t dgcs = *DGCS(base, sid); uint32_t dgbs = *DGBS(base, sid); @@ -259,7 +259,7 @@ static inline uint32_t cavs_hda_unused(uint32_t base, uint32_t sid) * @param sid Stream ID within the register block * @param len Len to increment postion by */ -static inline void cavs_hda_host_commit(uint32_t base, uint32_t sid, uint32_t len) +static inline void intel_adsp_hda_host_commit(uint32_t base, uint32_t sid, uint32_t len) { *DGBFPI(base, sid) = len; *DGLLPI(base, sid) = len; @@ -271,13 +271,13 @@ static inline void cavs_hda_host_commit(uint32_t base, uint32_t sid, uint32_t le * * Writes the length to BFPI. * - * @seealso cavs_hda_host_commit + * @seealso intel_adsp_hda_host_commit * * @param base Base address of the IP register block * @param sid Stream ID within the register block * @param len Len to increment postion by */ -static inline void cavs_hda_link_commit(uint32_t base, uint32_t sid, uint32_t len) +static inline void intel_adsp_hda_link_commit(uint32_t base, uint32_t sid, uint32_t len) { *DGBFPI(base, sid) = len; } @@ -290,7 +290,7 @@ static inline void cavs_hda_link_commit(uint32_t base, uint32_t sid, uint32_t le * * @retval true If the buffer full flag is set */ -static inline bool cavs_hda_buf_full(uint32_t base, uint32_t sid) +static inline bool intel_adsp_hda_buf_full(uint32_t base, uint32_t sid) { return *DGCS(base, sid) & DGCS_BF; } @@ -302,16 +302,16 @@ static inline bool cavs_hda_buf_full(uint32_t base, uint32_t sid) * there are bit flags for those cases. * * Useful for waiting on the hardware to catch up to - * reads or writes (e.g. after a cavs_hda_commit) + * reads or writes (e.g. after a intel_adsp_hda_commit) * * @param dev HDA Stream device - * @param sid Stream ID + * @param sid Stream D * * @retval true If the read and write positions are equal */ -static inline bool cavs_hda_wp_rp_eq(uint32_t base, uint32_t sid) +static inline bool intel_adsp_hda_wp_rp_eq(uint32_t base, uint32_t sid) { return *DGBWP(base, sid) == *DGBRP(base, sid); } -#endif /* ZEPHYR_INCLUDE_CAVS_HDA_H */ +#endif /* ZEPHYR_INCLUDE_INTEL_ADSP_HDA_H */ diff --git a/subsys/logging/CMakeLists.txt b/subsys/logging/CMakeLists.txt index 046da9433b..786be31c2f 100644 --- a/subsys/logging/CMakeLists.txt +++ b/subsys/logging/CMakeLists.txt @@ -84,8 +84,8 @@ if(NOT CONFIG_LOG_MODE_MINIMAL) ) zephyr_sources_ifdef( - CONFIG_LOG_BACKEND_CAVS_HDA - log_backend_cavs_hda.c + CONFIG_LOG_BACKEND_ADSP_HDA + log_backend_adsp_hda.c ) zephyr_sources_ifdef( diff --git a/subsys/logging/Kconfig.backends b/subsys/logging/Kconfig.backends index bc8413bb49..39724ccc42 100644 --- a/subsys/logging/Kconfig.backends +++ b/subsys/logging/Kconfig.backends @@ -333,22 +333,22 @@ source "subsys/logging/Kconfig.template.log_format_config" endif # LOG_BACKEND_ADSP -config LOG_BACKEND_CAVS_HDA - bool "cAVS HDA backend" - depends on SOC_FAMILY_INTEL_ADSP && DMA && DMA_CAVS_HDA_HOST_OUT +config LOG_BACKEND_ADSP_HDA + bool "Intel ADSP HDA backend" + depends on SOC_FAMILY_INTEL_ADSP && DMA && DMA_INTEL_ADSP_HDA_HOST_OUT select LOG_OUTPUT help Provide a logging backend which writes to a buffer and periodically flushes to hardware using ringbuffer like - semantics provided by DMA_CAVS_HDA. + semantics provided by DMA_INTEL_ADSP_HDA. -if LOG_BACKEND_CAVS_HDA +if LOG_BACKEND_ADSP_HDA -backend = CAVS_HDA -backend-str = cavs_hda +backend = ADSP_HDA +backend-str = adsp_hda source "subsys/logging/Kconfig.template.log_format_config" -config LOG_BACKEND_CAVS_HDA_SIZE +config LOG_BACKEND_ADSP_HDA_SIZE int "Size of ring buffer" range 128 8192 default 4096 @@ -358,16 +358,16 @@ config LOG_BACKEND_CAVS_HDA_SIZE The period of time is decided by how often to inform the hardware of writes to the buffer. -config LOG_BACKEND_CAVS_HDA_FLUSH_TIME +config LOG_BACKEND_ADSP_HDA_FLUSH_TIME int "Time in milliseconds to periodically flush writes to hardware" range 1 10000 default 500 help - The cAVS HDA backend periodically writes out its buffer contents + The Intel ADSP HDA backend periodically writes out its buffer contents to hardware by informing the DMA hardware the contents of the ring buffer. -endif # LOG_BACKEND_CAVS_HDA +endif # LOG_BACKEND_ADSP_HDA config LOG_BACKEND_FS bool "File system backend" diff --git a/subsys/logging/Kconfig.formatting b/subsys/logging/Kconfig.formatting index 4a52b1a2ff..1da287a8ca 100644 --- a/subsys/logging/Kconfig.formatting +++ b/subsys/logging/Kconfig.formatting @@ -143,7 +143,7 @@ config LOG_BACKEND_FORMAT_TIMESTAMP bool "Timestamp formatting in the backend" depends on LOG_BACKEND_UART || LOG_BACKEND_NATIVE_POSIX || LOG_BACKEND_RTT \ || LOG_BACKEND_SWO || LOG_BACKEND_XTENSA_SIM || LOG_BACKEND_FS \ - || LOG_BACKEND_ADSP || LOG_BACKEND_CAVS_HDA + || LOG_BACKEND_ADSP || LOG_BACKEND_ADSP_HDA default y help When enabled timestamp is formatted to hh:mm:ss:ms,us. diff --git a/subsys/logging/log_backend_cavs_hda.c b/subsys/logging/log_backend_adsp_hda.c similarity index 88% rename from subsys/logging/log_backend_cavs_hda.c rename to subsys/logging/log_backend_adsp_hda.c index c8623e1433..44a62e242a 100644 --- a/subsys/logging/log_backend_cavs_hda.c +++ b/subsys/logging/log_backend_adsp_hda.c @@ -10,11 +10,11 @@ #include #include #include -#include +#include #include #include -static uint32_t log_format_current = CONFIG_LOG_BACKEND_CAVS_HDA_OUTPUT_DEFAULT; +static uint32_t log_format_current = CONFIG_LOG_BACKEND_ADSP_HDA_OUTPUT_DEFAULT; static const struct device *hda_log_dev; static uint32_t hda_log_chan; @@ -22,11 +22,11 @@ static uint32_t hda_log_chan; * HDA requires 128 byte aligned data and 128 byte aligned transfers. */ #define ALIGNMENT DMA_BUF_ALIGNMENT(DT_NODELABEL(hda_host_in)) -static __aligned(ALIGNMENT) uint8_t hda_log_buf[CONFIG_LOG_BACKEND_CAVS_HDA_SIZE]; +static __aligned(ALIGNMENT) uint8_t hda_log_buf[CONFIG_LOG_BACKEND_ADSP_HDA_SIZE]; static volatile uint32_t hda_log_buffered; static struct k_spinlock hda_log_lock; static struct k_timer hda_log_timer; -static cavs_hda_log_hook_t hook; +static adsp_hda_log_hook_t hook; /* atomic bit flags for state */ #define HDA_LOG_DMA_READY 0 @@ -40,7 +40,7 @@ static uint32_t hda_log_flush(void) if (nearest128 > 0) { hda_log_buffered = hda_log_buffered - nearest128; #if !(IS_ENABLED(CONFIG_KERNEL_COHERENCE)) - z_xtensa_cache_flush(hda_log_buf, CONFIG_LOG_BACKEND_CAVS_HDA_SIZE); + z_xtensa_cache_flush(hda_log_buf, CONFIG_LOG_BACKEND_ADSP_HDA_SIZE); #endif dma_reload(hda_log_dev, hda_log_chan, 0, 0, nearest128); } @@ -155,7 +155,7 @@ out: */ #define LOG_BUF_SIZE 128 static uint8_t log_buf[LOG_BUF_SIZE]; -LOG_OUTPUT_DEFINE(log_output_cavs_hda, hda_log_out, log_buf, LOG_BUF_SIZE); +LOG_OUTPUT_DEFINE(log_output_adsp_hda, hda_log_out, log_buf, LOG_BUF_SIZE); static void hda_log_periodic(struct k_timer *tm) { @@ -182,9 +182,9 @@ static inline void dropped(const struct log_backend *const backend, ARG_UNUSED(backend); if (IS_ENABLED(CONFIG_LOG_DICTIONARY_SUPPORT)) { - log_dict_output_dropped_process(&log_output_cavs_hda, cnt); + log_dict_output_dropped_process(&log_output_adsp_hda, cnt); } else { - log_output_dropped_process(&log_output_cavs_hda, cnt); + log_output_dropped_process(&log_output_adsp_hda, cnt); } } @@ -196,7 +196,7 @@ static void panic(struct log_backend const *const backend) atomic_set_bit(&hda_log_flags, HDA_LOG_PANIC_MODE); /* flushes the log queue */ - log_backend_std_panic(&log_output_cavs_hda); + log_backend_std_panic(&log_output_adsp_hda); } static int format_set(const struct log_backend *const backend, uint32_t log_type) @@ -218,7 +218,7 @@ static void process(const struct log_backend *const backend, log_format_func_t log_output_func = log_format_func_t_get(log_format_current); - log_output_func(&log_output_cavs_hda, &msg->log, flags); + log_output_func(&log_output_adsp_hda, &msg->log, flags); } /** @@ -232,7 +232,7 @@ static void init(const struct log_backend *const backend) hda_log_buffered = 0; } -const struct log_backend_api log_backend_cavs_hda_api = { +const struct log_backend_api log_backend_adsp_hda_api = { .process = process, .dropped = IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE) ? NULL : dropped, .panic = panic, @@ -240,9 +240,9 @@ const struct log_backend_api log_backend_cavs_hda_api = { .init = init, }; -LOG_BACKEND_DEFINE(log_backend_cavs_hda, log_backend_cavs_hda_api, true); +LOG_BACKEND_DEFINE(log_backend_adsp_hda, log_backend_adsp_hda_api, true); -void cavs_hda_log_init(cavs_hda_log_hook_t fn, uint32_t channel) +void adsp_hda_log_init(adsp_hda_log_hook_t fn, uint32_t channel) { hook = fn; @@ -259,7 +259,7 @@ void cavs_hda_log_init(cavs_hda_log_hook_t fn, uint32_t channel) /* configure channel */ struct dma_block_config hda_log_dma_blk_cfg = { - .block_size = CONFIG_LOG_BACKEND_CAVS_HDA_SIZE, + .block_size = CONFIG_LOG_BACKEND_ADSP_HDA_SIZE, .source_address = (uint32_t)(uintptr_t)&hda_log_buf, }; @@ -280,8 +280,8 @@ void cavs_hda_log_init(cavs_hda_log_hook_t fn, uint32_t channel) k_timer_init(&hda_log_timer, hda_log_periodic, NULL); k_timer_start(&hda_log_timer, - K_MSEC(CONFIG_LOG_BACKEND_CAVS_HDA_FLUSH_TIME), - K_MSEC(CONFIG_LOG_BACKEND_CAVS_HDA_FLUSH_TIME)); + K_MSEC(CONFIG_LOG_BACKEND_ADSP_HDA_FLUSH_TIME), + K_MSEC(CONFIG_LOG_BACKEND_ADSP_HDA_FLUSH_TIME)); printk("hda log initialized\n"); } diff --git a/tests/boards/intel_adsp/hda/prj.conf b/tests/boards/intel_adsp/hda/prj.conf index 725b0da596..0d43e90cdf 100644 --- a/tests/boards/intel_adsp/hda/prj.conf +++ b/tests/boards/intel_adsp/hda/prj.conf @@ -1,8 +1,2 @@ CONFIG_ZTEST=y CONFIG_DMA=y -#CONFIG_LOG=y -#CONFIG_LOG_MODE_DEFERRED=y -#CONFIG_LOG_BACKEND_ADSP=n -#CONFIG_LOG_BACKEND_CAVS_HDA=y -#CONFIG_LOG_BACKEND_CAVS_HDA_SIZE=8192 -#CONFIG_LOG_BACKEND_CAVS_HDA_FLUSH_TIME=100 diff --git a/tests/boards/intel_adsp/hda/src/dma.c b/tests/boards/intel_adsp/hda/src/dma.c index 8b312dabe3..87e1b01732 100644 --- a/tests/boards/intel_adsp/hda/src/dma.c +++ b/tests/boards/intel_adsp/hda/src/dma.c @@ -21,7 +21,7 @@ static __aligned(ALIGNMENT) uint8_t dma_buf[DMA_BUF_SIZE]; #define HDA_HOST_OUT_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 0) #define HDA_STREAM_COUNT DT_PROP(DT_NODELABEL(hda_host_out), dma_channels) #define HDA_REGBLOCK_SIZE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 1) -#include +#include static volatile int msg_cnt; static volatile int msg_res; @@ -73,15 +73,15 @@ void test_hda_host_in_dma(void) channel = dma_request_channel(dma, NULL); zassert_true(channel >= 0, "Expected a valid DMA channel"); - printk("dma channel: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("dma channel: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, channel, IPC_TIMEOUT); - printk("host reset: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("host reset: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG, channel | (DMA_BUF_SIZE << 8), IPC_TIMEOUT); - printk("host config: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("host config: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); struct dma_block_config block_cfg = { @@ -96,21 +96,22 @@ void test_hda_host_in_dma(void) }; res = dma_config(dma, channel, &dma_cfg); - printk("dsp dma config: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("dsp dma config: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); zassert_ok(res, "Expected dma config to succeed"); res = dma_start(dma, channel); - printk("dsp dma start: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("dsp dma start: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); zassert_ok(res, "Expected dma start to succeed"); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, channel, IPC_TIMEOUT); - printk("host start: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("host start: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); for (uint32_t i = 0; i < TRANSFER_COUNT; i++) { res = dma_reload(dma, channel, 0, 0, DMA_BUF_SIZE); zassert_ok(res, "Expected dma reload to succeed"); - printk("dsp dma reload: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + printk("dsp dma reload: "); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); struct dma_status status; int j; @@ -124,7 +125,7 @@ void test_hda_host_in_dma(void) k_busy_wait(100); } printk("dsp read write equal after %d uS: ", j*100); - cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, channel); last_msg_cnt = msg_cnt; hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_VALIDATE, channel, @@ -165,17 +166,17 @@ void test_hda_host_out_dma(void) channel = dma_request_channel(dma, NULL); zassert_true(channel >= 0, "Expected a valid DMA channel"); - printk("dma channel: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("dma channel: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, (channel + 7), IPC_TIMEOUT); - printk("host reset: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("host reset: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG, (channel + 7) | (DMA_BUF_SIZE << 8), IPC_TIMEOUT); - printk("host config: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("host config: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); struct dma_block_config block_cfg = { .block_size = DMA_BUF_SIZE, @@ -189,29 +190,29 @@ void test_hda_host_out_dma(void) }; res = dma_config(dma, channel, &dma_cfg); - printk("dsp dma config: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("dsp dma config: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); zassert_ok(res, "Expected dma config to succeed"); res = dma_start(dma, channel); - printk("dsp dma start: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("dsp dma start: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); zassert_ok(res, "Expected dma start to succeed"); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, (channel + 7), IPC_TIMEOUT); printk("host start: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); for (uint32_t i = 0; i < TRANSFER_COUNT; i++) { hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_SEND, (channel + 7) | (DMA_BUF_SIZE << 8), IPC_TIMEOUT); printk("host send: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); /* TODO add a dma_poll() style call for xfer ready/complete maybe? */ - WAIT_FOR(cavs_hda_buf_full(HDA_HOST_OUT_BASE, channel), 10000, k_msleep(1)); + WAIT_FOR(intel_adsp_hda_buf_full(HDA_HOST_OUT_BASE, channel), 10000, k_msleep(1)); printk("dsp wait for full: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); #if (IS_ENABLED(CONFIG_KERNEL_COHERENCE)) zassert_true(arch_mem_coherent(dma_buf), "Buffer is unexpectedly incoherent!"); @@ -234,14 +235,15 @@ void test_hda_host_out_dma(void) res = dma_reload(dma, channel, 0, 0, DMA_BUF_SIZE); zassert_ok(res, "Expected dma reload to succeed"); - printk("dsp dma reload: "); cavs_hda_dbg("host_out", HDA_HOST_IN_BASE, channel); + printk("dsp dma reload: "); + intel_adsp_hda_dbg("host_out", HDA_HOST_IN_BASE, channel); } hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, (channel + 7), IPC_TIMEOUT); - printk("host reset: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("host reset: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); res = dma_stop(dma, channel); zassert_ok(res, "Expected dma stop to succeed"); - printk("dsp dma stop: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); + printk("dsp dma stop: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, channel); } diff --git a/tests/boards/intel_adsp/hda/src/smoke.c b/tests/boards/intel_adsp/hda/src/smoke.c index 4d7a2059c4..fad8cbf6cc 100644 --- a/tests/boards/intel_adsp/hda/src/smoke.c +++ b/tests/boards/intel_adsp/hda/src/smoke.c @@ -13,7 +13,7 @@ #define HDA_HOST_OUT_BASE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 0) #define HDA_STREAM_COUNT DT_PROP(DT_NODELABEL(hda_host_out), dma_channels) #define HDA_REGBLOCK_SIZE DT_PROP_BY_IDX(DT_NODELABEL(hda_host_out), reg, 1) -#include +#include #define IPC_TIMEOUT K_MSEC(1500) #define STREAM_ID 3U @@ -66,36 +66,37 @@ void test_hda_host_in_smoke(void) z_xtensa_cache_flush(hda_buf, HDA_BUF_SIZE); #endif - cavs_hda_init(HDA_HOST_IN_BASE, STREAM_ID); - printk("dsp init: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_init(HDA_HOST_IN_BASE, STREAM_ID); + printk("dsp init: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, STREAM_ID, IPC_TIMEOUT); printk("host reset: "); - cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG, STREAM_ID | (HDA_BUF_SIZE << 8), IPC_TIMEOUT); printk("host config: "); - cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); - res = cavs_hda_set_buffer(HDA_HOST_IN_BASE, STREAM_ID, hda_buf, HDA_BUF_SIZE); - printk("dsp set_buffer: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + res = intel_adsp_hda_set_buffer(HDA_HOST_IN_BASE, STREAM_ID, hda_buf, HDA_BUF_SIZE); + printk("dsp set_buffer: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); zassert_ok(res, "Expected set buffer to succeed"); - cavs_hda_enable(HDA_HOST_IN_BASE, STREAM_ID); - printk("dsp enable: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_enable(HDA_HOST_IN_BASE, STREAM_ID); + printk("dsp enable: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, STREAM_ID, IPC_TIMEOUT); printk("host start: "); - cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); for (uint32_t i = 0; i < TRANSFER_COUNT; i++) { - cavs_hda_host_commit(HDA_HOST_IN_BASE, STREAM_ID, HDA_BUF_SIZE); - printk("dsp inc_pos: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_host_commit(HDA_HOST_IN_BASE, STREAM_ID, HDA_BUF_SIZE); + printk("dsp inc_pos: "); intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); - WAIT_FOR(cavs_hda_wp_rp_eq(HDA_HOST_IN_BASE, STREAM_ID), 10000, k_msleep(1)); - printk("dsp wp_rp_eq: "); cavs_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); + WAIT_FOR(intel_adsp_hda_wp_rp_eq(HDA_HOST_IN_BASE, STREAM_ID), 10000, k_msleep(1)); + printk("dsp wp_rp_eq: "); + intel_adsp_hda_dbg("host_in", HDA_HOST_IN_BASE, STREAM_ID); last_msg_cnt = msg_cnt; hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_VALIDATE, STREAM_ID, @@ -107,7 +108,7 @@ void test_hda_host_in_smoke(void) } hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, STREAM_ID, IPC_TIMEOUT); - cavs_hda_disable(HDA_HOST_IN_BASE, STREAM_ID); + intel_adsp_hda_disable(HDA_HOST_IN_BASE, STREAM_ID); } /* @@ -128,30 +129,30 @@ void test_hda_host_out_smoke(void) printk("Using buffer of size %d at addr %p\n", HDA_BUF_SIZE, hda_buf); - cavs_hda_init(HDA_HOST_OUT_BASE, STREAM_ID); - printk("dsp init: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_init(HDA_HOST_OUT_BASE, STREAM_ID); + printk("dsp init: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, (STREAM_ID + 7), IPC_TIMEOUT); printk("host reset: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG, (STREAM_ID + 7) | (HDA_BUF_SIZE << 8), IPC_TIMEOUT); printk("host config: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); - res = cavs_hda_set_buffer(HDA_HOST_OUT_BASE, STREAM_ID, hda_buf, HDA_BUF_SIZE); - printk("dsp set buffer: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + res = intel_adsp_hda_set_buffer(HDA_HOST_OUT_BASE, STREAM_ID, hda_buf, HDA_BUF_SIZE); + printk("dsp set buffer: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); zassert_ok(res, "Expected set buffer to succeed"); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, (STREAM_ID + 7), IPC_TIMEOUT); printk("host start: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); - cavs_hda_enable(HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_enable(HDA_HOST_OUT_BASE, STREAM_ID); printk("dsp enable: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); for (uint32_t i = 0; i < TRANSFER_COUNT; i++) { for (int j = 0; j < HDA_BUF_SIZE; j++) { @@ -161,12 +162,12 @@ void test_hda_host_out_smoke(void) hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_SEND, (STREAM_ID + 7) | (HDA_BUF_SIZE << 8), IPC_TIMEOUT); printk("host send: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); - WAIT_FOR(cavs_hda_buf_full(HDA_HOST_OUT_BASE, STREAM_ID), 10000, k_msleep(1)); + WAIT_FOR(intel_adsp_hda_buf_full(HDA_HOST_OUT_BASE, STREAM_ID), 10000, k_msleep(1)); printk("dsp wait for full: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); #if (IS_ENABLED(CONFIG_KERNEL_COHERENCE)) zassert_true(arch_mem_coherent(hda_buf), "Buffer is unexpectedly incoherent!"); @@ -187,8 +188,9 @@ void test_hda_host_out_smoke(void) } zassert_true(is_ramp, "Expected data to be a ramp"); - cavs_hda_host_commit(HDA_HOST_OUT_BASE, STREAM_ID, HDA_BUF_SIZE); - printk("dsp inc pos: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_host_commit(HDA_HOST_OUT_BASE, STREAM_ID, HDA_BUF_SIZE); + printk("dsp inc pos: "); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); } @@ -196,8 +198,8 @@ void test_hda_host_out_smoke(void) IPC_TIMEOUT); printk("host reset: "); - cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); - cavs_hda_disable(HDA_HOST_OUT_BASE, STREAM_ID); - printk("dsp disable: "); cavs_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); + intel_adsp_hda_disable(HDA_HOST_OUT_BASE, STREAM_ID); + printk("dsp disable: "); intel_adsp_hda_dbg("host_out", HDA_HOST_OUT_BASE, STREAM_ID); } diff --git a/tests/boards/intel_adsp/hda_log/prj.conf b/tests/boards/intel_adsp/hda_log/prj.conf index 2ee5b19471..f3b282a621 100644 --- a/tests/boards/intel_adsp/hda_log/prj.conf +++ b/tests/boards/intel_adsp/hda_log/prj.conf @@ -4,7 +4,7 @@ CONFIG_ASSERT=y CONFIG_LOG=y CONFIG_LOG_MODE_DEFERRED=y CONFIG_LOG_BACKEND_ADSP=n -CONFIG_LOG_BACKEND_CAVS_HDA=y -CONFIG_LOG_BACKEND_CAVS_HDA_SIZE=512 -CONFIG_LOG_BACKEND_CAVS_HDA_FLUSH_TIME=100 +CONFIG_LOG_BACKEND_ADSP_HDA=y +CONFIG_LOG_BACKEND_ADSP_HDA_SIZE=512 +CONFIG_LOG_BACKEND_ADSP_HDA_FLUSH_TIME=100 CONFIG_XTENSA_ENABLE_BACKTRACE=n diff --git a/tests/boards/intel_adsp/hda_log/src/logger.c b/tests/boards/intel_adsp/hda_log/src/logger.c index 4ce389b528..78017fae44 100644 --- a/tests/boards/intel_adsp/hda_log/src/logger.c +++ b/tests/boards/intel_adsp/hda_log/src/logger.c @@ -2,7 +2,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include #include #include #include @@ -51,7 +51,7 @@ void test_hda_logger(void) hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_RESET, CHANNEL, IPC_TIMEOUT); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_CONFIG, CHANNEL | (HOST_BUF_SIZE << 8), IPC_TIMEOUT); - cavs_hda_log_init(hda_log_hook, CHANNEL); + adsp_hda_log_init(hda_log_hook, CHANNEL); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_START, CHANNEL, IPC_TIMEOUT); hda_ipc_msg(CAVS_HOST_DEV, IPCCMD_HDA_PRINT, ((HOST_BUF_SIZE*2) << 8) | CHANNEL, IPC_TIMEOUT);