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soc: silabs_exx32: Add support for SiLabs EFM32PG1B SoC

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This commit adds support for Silicon Labs EFM32PG1B (Pearl Gecko) SoC.

Signed-off-by: Rafael Dias Menezes <rdmeneze@gmail.com>
This commit is contained in:
Rafael Dias Menezes 2021-01-09 14:14:16 +01:00 committed by Maureen Helm
parent 086503abd5
commit c25358d68e
12 changed files with 379 additions and 1 deletions
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4
CODEOWNERS
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@ -46,6 +46,7 @@
/soc/arm/nuvoton_npcx/ @MulinChao
/soc/arm/qemu_cortex_a53/ @carlocaione
/soc/arm/quicklogic_eos_s3/ @kowalewskijan @kgugala
/soc/arm/silabs_exx32/efm32pg1b/ @rdmeneze
/soc/arm/silabs_exx32/efr32mg21/ @l-alfred
/soc/arm/st_stm32/ @erwango
/soc/arm/st_stm32/*/power.c @FRASTM
@ -83,6 +84,7 @@
/boards/arm/cc3220sf_launchxl/ @vanti
/boards/arm/cy8* @nandojve
/boards/arm/disco_l475_iot1/ @erwango
/boards/arm/efm32pg_stk3401a/ @rdmeneze
/boards/arm/faze/ @mbittan @simonguinot
/boards/arm/frdm*/ @MaureenHelm
/boards/arm/frdm*/doc/ @MaureenHelm @MeganHansen
@ -316,11 +318,13 @@
/dts/arm/nuvoton/npcx/ @MulinChao
/dts/arm/nxp/ @MaureenHelm
/dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg
/dts/arm/silabs/efm32_pg_1b.dtsi @rdmeneze
/dts/arm/silabs/efm32gg11b* @oanerer
/dts/arm/silabs/efm32_jg_pg* @chrta
/dts/arm/silabs/efr32bg13p* @mnkp
/dts/arm/silabs/efm32jg12b* @chrta
/dts/arm/silabs/efm32pg12b* @chrta
/dts/arm/silabs/efm32pg1b* @rdmeneze
/dts/arm/silabs/efr32mg21* @l-alfred
/dts/riscv/it8xxx2.dtsi @ite
/dts/riscv/microsemi-miv.dtsi @galak

170
dts/arm/silabs/efm32_pg_1b.dtsi Normal file
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@ -0,0 +1,170 @@
/*
* Copyright (c) 2021 Rafael Dias Menezes <rdmeneze@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include "gpio_gecko.h"
/ {
chosen {
zephyr,flash-controller = &msc;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
soc {
msc: flash-controller@400e0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400e0000 0x800>;
interrupts = <24 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
erase-block-size = <2048>;
};
};
usart0: usart@40010000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40010000 0x400>;
interrupts = <11 0 12 0>;
interrupt-names = "rx", "tx";
peripheral-id = <0>;
status = "disabled";
label = "USART_0";
};
usart1: usart@40010400 { /* USART1 */
compatible = "silabs,gecko-usart";
reg = <0x40010400 0x400>;
interrupts = <19 0 20 0>;
interrupt-names = "rx", "tx";
peripheral-id = <1>;
status = "disabled";
label = "USART_1";
};
leuart0: leuart@4004a000 { /* LEUART0 */
compatible = "silabs,gecko-leuart";
reg = <0x4004a000 0x400>;
interrupts = <21 0>;
peripheral-id = <0>;
status = "disabled";
label = "LEUART_0";
};
i2c0: i2c@4000c000 {
compatible = "silabs,gecko-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4000c000 0x400>;
interrupts = <16 0>;
label = "I2C_0";
status = "disabled";
};
rtcc0: rtcc@40042000 {
compatible = "silabs,gecko-rtcc";
reg = <0x40042000 0x184>;
interrupts = <29 0>;
clock-frequency = <32768>;
prescaler = <1>;
status = "disabled";
label = "RTCC_0";
};
gpio: gpio@4000a400 {
compatible = "silabs,gecko-gpio";
reg = <0x4000a400 0xf00>;
interrupts = <9 2 17 2>;
interrupt-names = "GPIO_EVEN", "GPIO_ODD";
label = "GPIO";
ranges;
#address-cells = <1>;
#size-cells = <1>;
gpioa: gpio@4000a000 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a000 0x30>;
peripheral-id = <0>;
label = "GPIO_A";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiob: gpio@4000a030 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a030 0x30>;
peripheral-id = <1>;
label = "GPIO_B";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpioc: gpio@4000a060 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a060 0x30>;
peripheral-id = <2>;
label = "GPIO_C";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiod: gpio@4000a090 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a090 0x30>;
peripheral-id = <3>;
label = "GPIO_D";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpiof: gpio@4000a0f0 {
compatible = "silabs,gecko-gpio-port";
reg = <0x4000a0f0 0x30>;
peripheral-id = <5>;
label = "GPIO_F";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
};
wdog0: wdog@40052000 {
compatible = "silabs,gecko-wdog";
reg = <0x40052000 0x400>;
peripheral-id = <0>;
label = "WDOG0";
interrupts = <2 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

16
dts/arm/silabs/efm32pg1b.dtsi Normal file
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/*
* Copyright (c) 2021 Rafael Dias Menezes <rdmeneze@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <silabs/efm32_pg_1b.dtsi>
/ {
cpus {
cpu0: cpu@0 {
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
};

25
dts/arm/silabs/efm32pg1b200f256gm48.dtsi Normal file
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@ -0,0 +1,25 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <silabs/efm32pg1b.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
compatible = "silabs,efm32pg1b200f256gm48", "silabs,efm32pg1b", "silabs,efm32", "simple-bus";
flash-controller@400e0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(256)>;
};
};
};
};

26
soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.efm32pg1b Normal file
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@ -0,0 +1,26 @@
# Silicon Labs EFM32PG-STK3401A platform configuration options
# Copyright (c) 2020 Rafael Dias Menezes
# SPDX-License-Identifier: Apache-2.0
config GPIO_GECKO
default y
depends on GPIO
if SERIAL
config UART_GECKO
default y
config LEUART_GECKO
default y
endif # SERIAL
config I2C_GECKO
default y
depends on I2C
config SOC_FLASH_GECKO
default y
depends on FLASH

20
soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series Normal file
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@ -0,0 +1,20 @@
# EFM32PG1B series configuration options
# Copyright (c) 2020 Rafael Dias Menezes <rdmeneze@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_EFM32PG1B
config SOC_SERIES
default "efm32pg1b"
config SOC_PART_NUMBER
default "EFM32PG1B200F256GM48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48
config NUM_IRQS
# must be >= the highest interrupt number used
default 34
source "soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.efm32pg1b"
endif # SOC_SERIES_EFM32PG1B

25
soc/arm/silabs_exx32/efm32pg1b/Kconfig.series Normal file
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@ -0,0 +1,25 @@
# EFM32PG1B MCU line
# Copyright (c) 2020 Rafael Dias Menezes
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_EFM32PG1B
bool "EFM32PG1B Series MCU"
select ARM
select HAS_SILABS_GECKO
select HAS_SWO
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_EXX32
select HAS_POWER_STATE_SLEEP_1
select HAS_POWER_STATE_SLEEP_2
select HAS_POWER_STATE_SLEEP_3
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS_HFRCO_FREQRANGE
select SOC_GECKO_CMU
select SOC_GECKO_EMU
select SOC_GECKO_GPIO
help
Enable support for EFM32 PearlGecko MCU series

8
soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc Normal file
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@ -0,0 +1,8 @@
# EFM32PG1B (Pearl Gecko) MCU line
# Copyright (c) 2018 Christian Taedcke
# SPDX-License-Identifier: Apache-2.0
config SOC_PART_NUMBER_EFM32PG1B200F256GM48
bool
depends on SOC_SERIES_EFM32PG1B

16
soc/arm/silabs_exx32/efm32pg1b/linker.ld Normal file
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@ -0,0 +1,16 @@
/*
* Copyright (c) 2018 Christian Taedcke
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images.
*/
#include <autoconf.h>
#include <arch/arm/aarch32/cortex_m/scripts/linker.ld>

31
soc/arm/silabs_exx32/efm32pg1b/soc.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (c) 2020 Rafael Dias Menezes <rdmeneze@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the efm32pg1b soc
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_bus.h>
#include <em_common.h>
/* Add include for DTS generated information */
#include <devicetree.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */

37
soc/arm/silabs_exx32/efm32pg1b/soc_pinmap.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2020 Rafael Dias Menezes
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Silabs EFM32PG1B MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef _SILABS_EFM32PG1B_SOC_PINMAP_H_
#define _SILABS_EFM32PG1B_SOC_PINMAP_H_
#include <soc.h>
#include <em_gpio.h>
#define GPIO_NODE DT_INST(0, silabs_gecko_gpio)
#if DT_NODE_HAS_PROP(GPIO_NODE, location_swo)
#define SWO_LOCATION DT_PROP(GPIO_NODE, location_swo)
#endif
/* Serial Wire Output (SWO) */
#if (SWO_LOCATION == 0)
#define PIN_SWO {gpioPortF, 2, gpioModePushPull, 1}
#elif (SWO_LOCATION == 1)
#define PIN_SWO {gpioPortB, 13, gpioModePushPull, 1}
#elif (SWO_LOCATION == 2)
#define PIN_SWO {gpioPortD, 15, gpioModePushPull, 1}
#elif (SWO_LOCATION == 3)
#define PIN_SWO {gpioPortC, 11, gpioModePushPull, 1}
#elif (SWO_LOCATION >= 4)
#error ("Invalid SWO pin location")
#endif
#endif /* _SILABS_EFM32PG1B_SOC_PINMAP_H_ */

2
west.yml
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@ -68,7 +68,7 @@ manifest:
revision: a1ec761014740a08699720298dd37ad4da360840
path: modules/hal/microchip
- name: hal_silabs
revision: 69c3e1e6e167767cb75aa2b468df4ade05988cdb
revision: 6bb4a17a2f94a39eba295dd55dbeae6f6c4c9b1b
path: modules/hal/silabs
- name: hal_st
revision: b52fdbf4b62439be9fab9bb4bae9690a42d2fb14