qemu_riscv32: use hifive1 configuration
Use hifive1 configuration for this qemu and set SYS_CLOCK_HW_CYCLES_PER_SEC to 10000000 Fixes #10043 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
b38fba35a3
commit
c2c6a6a245
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@ -1,4 +1,4 @@
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config BOARD_QEMU_RISCV32
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bool "QEMU RISCV32 target"
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depends on SOC_RISCV32_QEMU
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depends on SOC_RISCV32_SIFIVE_FREEDOM
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select QEMU_TARGET
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@ -3,9 +3,8 @@ set(EMU_PLATFORM qemu)
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set(QEMU_CPU_TYPE_${ARCH} riscv32)
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set(QEMU_FLAGS_${ARCH}
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-m ${CONFIG_RISCV_RAM_SIZE_MB}
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-nographic
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-machine sifive
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-machine sifive_e
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)
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set(BOARD_DEBUG_RUNNER qemu)
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@ -1,23 +1,32 @@
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/dts-v1/;
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#include <riscv32-qemu.dtsi>
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#include <riscv32-fe310.dtsi>
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/ {
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model = "qemu_riscv32";
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compatible = "qemu,riscv32";
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aliases {
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uart-0 = &uart0;
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};
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model = "SiFive HiFive 1";
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compatible = "sifive,hifive1";
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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};
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};
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&gpio0 {
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status = "ok";
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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clock-frequency = <16000000>;
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};
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&uart1 {
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clock-frequency = <16000000>;
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};
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&spi0 {
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status = "ok";
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};
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@ -3,6 +3,7 @@ name: QEMU Emulation for RISC V
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type: qemu
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simulation: qemu
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arch: riscv32
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ram: 16
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toolchain:
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- zephyr
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- xtools
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@ -1,12 +1,17 @@
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CONFIG_RISCV32=y
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CONFIG_SOC_SERIES_RISCV32_QEMU=y
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CONFIG_SOC_RISCV32_QEMU=y
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CONFIG_SOC_SERIES_RISCV32_SIFIVE_FREEDOM=y
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CONFIG_SOC_RISCV32_SIFIVE_FREEDOM=y
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CONFIG_BOARD_QEMU_RISCV32=y
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CONFIG_CONSOLE=y
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CONFIG_PRINTK=y
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CONFIG_SERIAL=y
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CONFIG_UART_RISCV_QEMU=y
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CONFIG_UART_SIFIVE=y
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CONFIG_UART_SIFIVE_PORT_0=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE_ON_DEV_NAME="uart0"
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CONFIG_PLIC=y
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CONFIG_PINMUX=y
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CONFIG_PINMUX_SIFIVE=y
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CONFIG_RISCV_MACHINE_TIMER=y
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CONFIG_BOOT_BANNER=y
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CONFIG_GPIO=y
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CONFIG_GPIO_SIFIVE=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
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@ -115,7 +115,7 @@ config ARCV2_INTERRUPT_UNIT
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config PLIC
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bool "Platform Level Interrupt Controller (PLIC)"
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default y
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depends on SOC_FAMILY_RISCV_PRIVILEGE && !QEMU_TARGET
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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select RISCV_HAS_PLIC
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help
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Platform Level Interrupt Controller provides support
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@ -17,7 +17,6 @@ zephyr_library_sources_ifdef(CONFIG_NRF_UARTE_PERIPHERAL uart_nrfx_uarte.c)
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zephyr_library_sources_if_kconfig(uart_ns16550.c)
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zephyr_library_sources_if_kconfig(uart_nsim.c)
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zephyr_library_sources_if_kconfig(uart_qmsi.c)
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zephyr_library_sources_if_kconfig(uart_riscv_qemu.c)
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zephyr_library_sources_if_kconfig(uart_sam.c)
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zephyr_library_sources_if_kconfig(usart_sam.c)
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zephyr_library_sources_if_kconfig(uart_stellaris.c)
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@ -91,8 +91,6 @@ source "drivers/serial/Kconfig.cc32xx"
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source "drivers/serial/Kconfig.cmsdk_apb"
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source "drivers/serial/Kconfig.riscv_qemu"
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source "drivers/serial/Kconfig.sifive"
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source "drivers/serial/Kconfig.esp32"
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@ -1,13 +0,0 @@
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# Kconfig.riscv_qemu - riscv-qemu UART configuration option
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#
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# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig UART_RISCV_QEMU
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bool "riscv-qemu UART driver"
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depends on SOC_RISCV32_QEMU
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select SERIAL_HAS_DRIVER
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help
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Enable the riscv-qemu UART driver.
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@ -1,51 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <uart.h>
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#include <sys_io.h>
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#define DEV_CFG(dev) \
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((const struct uart_device_config * const) \
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(dev)->config->config_info)
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static unsigned char uart_riscv_qemu_poll_out(struct device *dev,
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unsigned char c)
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{
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sys_write8(c, DEV_CFG(dev)->regs);
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return c;
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}
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static int uart_riscv_qemu_poll_in(struct device *dev, unsigned char *c)
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{
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*c = sys_read8(DEV_CFG(dev)->regs);
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return 0;
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}
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static int uart_riscv_qemu_init(struct device *dev)
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{
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/* Nothing to do */
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return 0;
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}
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static const struct uart_driver_api uart_riscv_qemu_driver_api = {
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.poll_in = uart_riscv_qemu_poll_in,
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.poll_out = uart_riscv_qemu_poll_out,
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.err_check = NULL,
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};
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static const struct uart_device_config uart_riscv_qemu_dev_cfg_0 = {
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.regs = RISCV_QEMU_UART_BASE,
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};
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DEVICE_AND_API_INIT(uart_riscv_qemu_0, "uart0",
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uart_riscv_qemu_init, NULL,
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&uart_riscv_qemu_dev_cfg_0,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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(void *)&uart_riscv_qemu_driver_api);
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@ -1,26 +0,0 @@
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---
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title: RISCV QEMU UART
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version: 0.1
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description: >
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This binding gives a base representation of the RISCV QEMU UART
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inherits:
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!include uart.yaml
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properties:
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compatible:
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constraint: "riscv,qemu-uart"
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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...
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@ -1,42 +0,0 @@
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#include "skeleton.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "qemu,riscv32";
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reg = <0>;
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};
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};
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flash0: flash@1000 {
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compatible = "soc-nv-flash";
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reg = <0x1000 0x100000>;
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};
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sram0: memory@80000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x80000000 0x2000000>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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uart0: uart@40002000 {
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compatible = "riscv,qemu-uart";
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reg = <0x40002000 0x400>;
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label = "uart0";
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status = "disabled";
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};
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};
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};
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@ -122,8 +122,6 @@ extern u32_t _timer_cycle_get_32(void);
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#if defined(CONFIG_SOC_RISCV32_PULPINO)
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#include <arch/riscv32/pulpino/asm_inline.h>
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#elif defined(CONFIG_SOC_RISCV32_QEMU)
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#include <arch/riscv32/riscv32-qemu/asm_inline.h>
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#elif defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
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#include <arch/riscv32/riscv-privilege/asm_inline.h>
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#endif
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@ -1,21 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_H_
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#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_H_
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/*
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* The file must not be included directly
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* Include arch/cpu.h instead
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*/
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#if defined(__GNUC__)
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#include <arch/riscv32/riscv32-qemu/asm_inline_gcc.h>
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#else
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#error "Supports only GNU C compiler"
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_H_ */
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@ -1,66 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_GCC_H_
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#define ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_GCC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* The file must not be included directly
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* Include arch/cpu.h instead
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* riscv32-qemu does not have bit manipulation asm opcodes.
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* Handle find_lsb_set and find_msb_set in C.
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*/
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#ifndef _ASMLANGUAGE
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#include <toolchain.h>
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/**
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*
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* @brief find least significant bit set in a 32-bit word
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*
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* This routine finds the first bit set starting from the least significant bit
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* in the argument passed in and returns the index of that bit. Bits are
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* numbered starting at 1 from the least significant bit. A return value of
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* zero indicates that the value passed is zero.
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*
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* @return least significant bit set, 0 if @a op is 0
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*/
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static ALWAYS_INLINE unsigned int find_lsb_set(u32_t op)
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{
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return __builtin_ffs(op);
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}
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/**
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*
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* @brief find most significant bit set in a 32-bit word
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*
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* This routine finds the first bit set starting from the most significant bit
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* in the argument passed in and returns the index of that bit. Bits are
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* numbered starting at 1 from the least significant bit. A return value of
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* zero indicates that the value passed is zero.
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*
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* @return most significant bit set, 0 if @a op is 0
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*/
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static ALWAYS_INLINE unsigned int find_msb_set(u32_t op)
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{
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if (!op)
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return 0;
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return 32 - __builtin_clz(op);
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}
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_INCLUDE_ARCH_RISCV32_RISCV32_QEMU_ASM_INLINE_GCC_H_ */
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@ -4,8 +4,5 @@ zephyr_sources(
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idle.c
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soc_irq.S
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soc_common_irq.c
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vector.S
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)
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if(NOT(CONFIG_SOC_SERIES_RISCV32_QEMU))
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zephyr_sources(vector.S)
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endif()
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@ -1,4 +0,0 @@
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zephyr_sources(
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qemu_irq.S
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vector.S
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)
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@ -1,27 +0,0 @@
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if SOC_SERIES_RISCV32_QEMU
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config SOC_SERIES
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string
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default "riscv32-qemu"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 10000000
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config RISCV_SOC_INTERRUPT_INIT
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bool
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default y
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config INCLUDE_RESET_VECTOR
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bool
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default y
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config NUM_IRQS
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int
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default 32
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config RISCV_RAM_SIZE_MB
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int
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default 32
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endif # SOC_SERIES_RISCV32_QEMU
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@ -1,13 +0,0 @@
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# Kconfig - riscv32 QEMU SOC implementation
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#
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# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_RISCV32_QEMU
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bool "riscv32 QEMU SOC implementation"
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depends on RISCV32
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select SOC_FAMILY_RISCV_PRIVILEGE
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help
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Enable support for riscv32 QEMU SOC implementation
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@ -1,16 +0,0 @@
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# Kconfig - RISCV32_QEMU SOC configuration options
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#
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# Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "riscv32_qemu SOC implementation"
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depends on SOC_SERIES_RISCV32_QEMU
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config SOC_RISCV32_QEMU
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bool "riscv32_qemu SOC implementation"
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select ATOMIC_OPERATIONS_C
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endchoice
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@ -1,5 +0,0 @@
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#define CONFIG_RISCV_RAM_BASE_ADDR CONFIG_SRAM_BASE_ADDRESS
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#define CONFIG_RISCV_ROM_BASE_ADDR CONFIG_FLASH_BASE_ADDRESS
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#define CONFIG_RISCV_ROM_SIZE (CONFIG_FLASH_SIZE *1024)
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@ -1,11 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Linker script for riscv32-qemu
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*/
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#include <generated_dts_board.h>
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#include <arch/riscv32/common/linker.ld>
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@ -1,45 +0,0 @@
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel_structs.h>
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#include <offsets.h>
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <soc.h>
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/* exports */
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GTEXT(__soc_is_irq)
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/*
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* riscv32-qemu does not truely follow riscv privilege specification
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* when determining if exception is the result of an interrupt or an
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* exception. Hence, reimplement __soc_is_irq here.
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*
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* return 1 (interrupt) or 0 (exception)
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*/
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SECTION_FUNC(exception.other, __soc_is_irq)
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/* Get exception number from the mcause CSR register. */
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csrr t0, mcause
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li t1, SOC_MCAUSE_EXP_MASK
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and t0, t0, t1
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/*
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* If corresponding exception bit is set in the
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* Machine Interrupt Pending register (mip),
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* the exception is an interrupt, otherwise it
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* is an unexpected exception.
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*/
|
||||
csrr t2, mip
|
||||
li t3, 1
|
||||
sll t4, t3, t0
|
||||
|
||||
addi a0, x0, 0
|
||||
bne t2, t4, not_interrupt
|
||||
addi a0, a0, 1
|
||||
|
||||
not_interrupt:
|
||||
/* return */
|
||||
jalr x0, ra
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file SoC configuration macros for the riscv-qemu
|
||||
*/
|
||||
|
||||
#ifndef __RISCV32_QEMU_SOC_H_
|
||||
#define __RISCV32_QEMU_SOC_H_
|
||||
|
||||
#include <soc_common.h>
|
||||
|
||||
#include <misc/util.h>
|
||||
|
||||
/* UART configuration */
|
||||
#define RISCV_QEMU_UART_BASE 0x40002000
|
||||
|
||||
/* Timer configuration */
|
||||
#define RISCV_MTIME_BASE 0x40000000
|
||||
#define RISCV_MTIMECMP_BASE 0x40000008
|
||||
|
||||
/* lib-c hooks required RAM defined variables */
|
||||
#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
|
||||
#define RISCV_RAM_SIZE MB(CONFIG_RISCV_RAM_SIZE_MB)
|
||||
|
||||
#endif /* __RISCV32_QEMU_SOC_H_ */
|
||||
|
|
@ -1,75 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
|
||||
* Contributors: 2018 Antmicro <www.antmicro.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <toolchain.h>
|
||||
|
||||
/* exports */
|
||||
GTEXT(__start)
|
||||
|
||||
/* imports */
|
||||
GTEXT(__reset)
|
||||
GTEXT(__irq_wrapper)
|
||||
|
||||
/*
|
||||
* following riscv32-qemu specs
|
||||
* IVT is placed at 0x000001000 and is mapped as follows:
|
||||
* 0x00001000: reset
|
||||
* 0x00001004: non-maskable interrupt (nmi) vector
|
||||
* 0x00001010: machine trap (mt) vector
|
||||
*
|
||||
* Call __irq_wrapper to handle all interrupts/exceptions/faults
|
||||
*/
|
||||
SECTION_FUNC(vectors, __start)
|
||||
.option norvc;
|
||||
|
||||
/*
|
||||
* jal instruction cannot be used to jump to address whose offset
|
||||
* is > 12-bits wide. In this case, we have to use a call or tail
|
||||
* instruction to jump to a far-away sub-routine.
|
||||
*
|
||||
* Given that IVT is found at a different address-space than the
|
||||
* RAM in riscv32-qemu, we have to use call or tail instructions
|
||||
* to jump to __reset or __isr_wrapper subroutines.
|
||||
* However, call or tail instructions are pseudo instructions,
|
||||
* which generate two base-instructions upon compilation. In this case,
|
||||
* using them at a particular entry in the IVT will overwrite the next
|
||||
* entry in the IVT. For example, using tail instruction in the
|
||||
* reset vector, will overwrite the nmi-vector entry. To prevent this,
|
||||
* perform a two-phase jump instructions to __reset or __irq_wrapper
|
||||
* subroutines. The first jump performs a jal instruction, which will
|
||||
* jump to an offset in the same vector address-space, but outside the
|
||||
* IVT. The second jump performs a tail instruction to the __reset
|
||||
* or __irq_wrapper subroutines.
|
||||
*/
|
||||
|
||||
/* Call __reset for reset vector */
|
||||
jal x0, do_reset
|
||||
|
||||
/* Call __irq_wrapper for nmi vector */
|
||||
jal x0, do_irq_wrapper
|
||||
|
||||
.org 0x10
|
||||
/* Call __irq_wrapper for mt vector */
|
||||
jal x0, do_irq_wrapper
|
||||
|
||||
.org 0x400 /* we are outside IVT */
|
||||
do_reset:
|
||||
/*
|
||||
* Set mtvec (Machine Trap-Vector Base-Address Register)
|
||||
* to __irq_wrapper, so that we jump directly to __irq_wrapper,
|
||||
* instead to the default machine trap vector address in IVT.
|
||||
* This will preserve us from performing two jump instructions upon
|
||||
* an interrupt.
|
||||
*/
|
||||
la t0, __irq_wrapper
|
||||
csrw mtvec, t0
|
||||
|
||||
/* Jump to __reset */
|
||||
tail __reset
|
||||
|
||||
do_irq_wrapper:
|
||||
tail __irq_wrapper
|
||||
Loading…
Reference in a new issue