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driver: clock control: Microchip XEC fix missing domain parameter

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The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
This commit is contained in:
Manimaran A 2023-03-07 16:37:04 +05:30 committed by Anas Nashif
parent 754920a74f
commit c42a155988
5 changed files with 10 additions and 8 deletions
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3
drivers/interrupt_controller/intc_mchp_ecia_xec.c
View file

@ -47,7 +47,8 @@
#define ECIA_XEC_PCR_INFO \
MCHP_XEC_PCR_SCR_ENCODE(DT_INST_CLOCKS_CELL(0, regidx), \
DT_INST_CLOCKS_CELL(0, bitpos))
DT_INST_CLOCKS_CELL(0, bitpos), \
DT_INST_CLOCKS_CELL(0, domain))
struct xec_girq_config {
uintptr_t base;

2
dts/arm/microchip/mec1501hsz.dtsi
View file

@ -61,7 +61,7 @@
/* pin configured only if the sources is set to PIN */
pinctrl-0 = <&clk_32khz_in_gpio165>;
pinctrl-names = "default";
#clock-cells = <2>;
#clock-cells = <3>;
};
ecia: ecia@4000e000 {
reg = <0x4000e000 0x400>;

5
dts/arm/microchip/mec172xnsz.dtsi
View file

@ -59,13 +59,13 @@
/* pin configured only if one of the sources is set to PIN */
pinctrl-0 = <&clk_32khz_in_gpio165>;
pinctrl-names = "default";
#clock-cells = <2>;
#clock-cells = <3>;
};
ecia: ecia@4000e000 {
compatible = "microchip,xec-ecia";
reg = <0x4000e000 0x400>;
direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
clocks = <&pcr 1 0>;
clocks = <&pcr 1 0 MCHP_XEC_PCR_CLK_PERIPH>;
#address-cells = <1>;
#size-cells = <1>;
@ -721,7 +721,6 @@
interrupts = <91 2>;
girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >;
pcrs = <4 8>;
clocks = <&pcr 1 0>;
clock-frequency = <12000000>;
lines = <1>;
chip-select = <0>;

3
dts/bindings/clock/microchip,xec-pcr.yaml
View file

@ -94,8 +94,9 @@ properties:
required: true
"#clock-cells":
const: 2
const: 3
clock-cells:
- regidx
- bitpos
- domain

5
soc/arm/microchip_mec/common/soc_pcr.h
View file

@ -12,8 +12,9 @@ extern "C" {
#endif
/* slp_idx = [0, 4], bitpos = [0, 31] refer above */
#define MCHP_XEC_PCR_SCR_ENCODE(slp_idx, bitpos) \
(((uint16_t)(slp_idx) & 0x7u) | (((uint16_t)bitpos & 0x1fu) << 3))
#define MCHP_XEC_PCR_SCR_ENCODE(slp_idx, bitpos, domain) \
((((uint32_t)(domain) & 0xff) << 24) | (((bitpos) & 0x1f) << 3) \
| ((uint32_t)(slp_idx) & 0x7))
#define MCHP_XEC_PCR_SCR_GET_IDX(e) ((e) & 0x7u)
#define MCHP_XEC_PCR_SCR_GET_BITPOS(e) (((e) & 0xf8u) >> 3)