diff --git a/drivers/gpio/Kconfig.imx b/drivers/gpio/Kconfig.imx index 8de6db2d7b..54f053276a 100644 --- a/drivers/gpio/Kconfig.imx +++ b/drivers/gpio/Kconfig.imx @@ -8,5 +8,6 @@ config GPIO_IMX default y depends on HAS_IMX_GPIO depends on DT_HAS_NXP_IMX_GPIO_ENABLED + select PINCTRL help Enable the IMX GPIO driver. diff --git a/drivers/gpio/gpio_imx.c b/drivers/gpio/gpio_imx.c index 0888ce8f11..bf534c064b 100644 --- a/drivers/gpio/gpio_imx.c +++ b/drivers/gpio/gpio_imx.c @@ -14,9 +14,7 @@ #include #include #include -#ifdef CONFIG_PINCTRL #include -#endif #include @@ -24,10 +22,8 @@ struct imx_gpio_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; GPIO_Type *base; -#ifdef CONFIG_PINCTRL const struct pinctrl_soc_pinmux *pin_muxes; uint8_t mux_count; -#endif }; struct imx_gpio_data { @@ -46,7 +42,6 @@ static int imx_gpio_configure(const struct device *port, gpio_pin_t pin, if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) { return -ENOTSUP; } -#ifdef CONFIG_PINCTRL __ASSERT_NO_MSG(pin < config->mux_count); struct pinctrl_soc_pin pin_cfg; @@ -92,14 +87,6 @@ static int imx_gpio_configure(const struct device *port, gpio_pin_t pin, pin_cfg.pin_ctrl_flags = reg; pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE); -#else /*CONFIG_PINCTRL */ - if ((flags & (GPIO_SINGLE_ENDED - | GPIO_PULL_UP - | GPIO_PULL_DOWN)) != 0U) { - return -ENOTSUP; - } -#endif - /* Disable interrupts for pin */ GPIO_SetPinIntMode(base, pin, false); GPIO_SetIntEdgeSelect(base, pin, false); @@ -263,7 +250,6 @@ static const struct gpio_driver_api imx_gpio_driver_api = { .manage_callback = imx_gpio_manage_callback, }; -#ifdef CONFIG_PINCTRL /* These macros will declare an array of pinctrl_soc_pinmux types */ #define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)), #define IMX_IGPIO_PIN_DECLARE(n) \ @@ -273,10 +259,6 @@ static const struct gpio_driver_api imx_gpio_driver_api = { #define IMX_IGPIO_PIN_INIT(n) \ .pin_muxes = mcux_igpio_pinmux_##n, \ .mux_count = DT_INST_PROP_LEN(n, pinmux), -#else -#define IMX_IGPIO_PIN_DECLARE(n) -#define IMX_IGPIO_PIN_INIT(n) -#endif /* CONFIG_PINCTRL */ #define GPIO_IMX_INIT(n) \ IMX_IGPIO_PIN_DECLARE(n) \ diff --git a/drivers/sdhc/Kconfig.imx b/drivers/sdhc/Kconfig.imx index 1e295f372b..48e47a1262 100644 --- a/drivers/sdhc/Kconfig.imx +++ b/drivers/sdhc/Kconfig.imx @@ -7,6 +7,7 @@ config IMX_USDHC depends on DT_HAS_NXP_IMX_USDHC_ENABLED select SDHC_SUPPORTS_UHS select SDHC_SUPPORTS_NATIVE_MODE + select PINCTRL help Enable the NXP IMX SD Host controller driver diff --git a/drivers/sdhc/imx_usdhc.c b/drivers/sdhc/imx_usdhc.c index 8be0694814..49914137ee 100644 --- a/drivers/sdhc/imx_usdhc.c +++ b/drivers/sdhc/imx_usdhc.c @@ -15,13 +15,11 @@ #include #include #include -#ifdef CONFIG_PINCTRL #include #define PINCTRL_STATE_SLOW PINCTRL_STATE_PRIV_START #define PINCTRL_STATE_MED (PINCTRL_STATE_PRIV_START + 1U) #define PINCTRL_STATE_FAST (PINCTRL_STATE_PRIV_START + 2U) #define PINCTRL_STATE_NOPULL (PINCTRL_STATE_PRIV_START + 3U) -#endif LOG_MODULE_REGISTER(usdhc, CONFIG_SDHC_LOG_LEVEL); @@ -72,9 +70,7 @@ struct usdhc_config { uint32_t max_bus_freq; bool mmc_hs200_1_8v; bool mmc_hs400_1_8v; -#ifdef CONFIG_PINCTRL const struct pinctrl_dev_config *pincfg; -#endif void (*irq_config_func)(const struct device *dev); }; @@ -115,16 +111,11 @@ static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup) { int ret = 0U; -#ifdef CONFIG_PINCTRL ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL); if (ret) { LOG_ERR("No DAT3 floating state defined, but dat3 detect selected"); return ret; } -#else - /* Call board specific function to pull down DAT3 */ - imxrt_usdhc_dat3_pull(pullup); -#endif #ifdef CONFIG_IMX_USDHC_DAT3_PWR_TOGGLE if (!pullup) { /* Power off the card to clear DAT3 legacy status */ @@ -364,18 +355,10 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios) break; case SDHC_TIMING_SDR12: case SDHC_TIMING_SDR25: -#ifdef CONFIG_PINCTRL pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW); -#else - imxrt_usdhc_pinmux(cfg->nusdhc, false, 0, 7); -#endif break; case SDHC_TIMING_SDR50: -#ifdef CONFIG_PINCTRL pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_MED); -#else - imxrt_usdhc_pinmux(cfg->nusdhc, false, 2, 7); -#endif break; case SDHC_TIMING_HS400: #if FSL_FEATURE_USDHC_HAS_HS400_MODE @@ -391,11 +374,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios) case SDHC_TIMING_DDR50: case SDHC_TIMING_DDR52: case SDHC_TIMING_HS200: -#ifdef CONFIG_PINCTRL pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_FAST); -#else - imxrt_usdhc_pinmux(cfg->nusdhc, false, 3, 7); -#endif break; default: return -ENOTSUP; @@ -823,12 +802,10 @@ static int imx_usdhc_init(const struct device *dev) return -ENODEV; } -#ifdef CONFIG_PINCTRL ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT); if (ret) { return ret; } -#endif USDHC_TransferCreateHandle(cfg->base, &data->transfer_handle, &callbacks, (void *)dev); cfg->irq_config_func(dev); @@ -872,14 +849,6 @@ static const struct sdhc_driver_api usdhc_api = { .get_host_props = imx_usdhc_get_host_props, }; -#ifdef CONFIG_PINCTRL -#define IMX_USDHC_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n); -#define IMX_USDHC_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), -#else -#define IMX_USDHC_PINCTRL_DEFINE(n) -#define IMX_USDHC_PINCTRL_INIT(n) -#endif - #ifdef CONFIG_NOCACHE_MEMORY #define IMX_USDHC_NOCACHE_TAG __attribute__((__section__(".nocache"))); #else @@ -909,7 +878,7 @@ static const struct sdhc_driver_api usdhc_api = { irq_enable(DT_INST_IRQN(n)); \ } \ \ - IMX_USDHC_PINCTRL_DEFINE(n) \ + PINCTRL_DT_INST_DEFINE(n); \ \ static const struct usdhc_config usdhc_##n##_config = { \ .base = (USDHC_Type *) DT_INST_REG_ADDR(n), \ @@ -932,7 +901,7 @@ static const struct sdhc_driver_api usdhc_api = { .mmc_hs200_1_8v = DT_INST_PROP(n, mmc_hs200_1_8v), \ .mmc_hs400_1_8v = DT_INST_PROP(n, mmc_hs400_1_8v), \ .irq_config_func = usdhc_##n##_irq_config_func, \ - IMX_USDHC_PINCTRL_INIT(n) \ + .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \ }; \ \ \