drivers: i3c: npcx: introduce NPCX I3C driver
This implements basic driver to utilize the I3C IP block on NPCX. 1. I3C mode: Main controller mode only. 2. Transfer: Support SDR only. 3. IBI: Support Hot-Join, IBI(MDB). Controller request is not supported. 4. Support 3 I3C modules: I3C1(3.3V), I3C2(1.8V, espi mode), (I3C3 1.8V or 3.3V) Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
This commit is contained in:
Alvis Sun
Fabio Baltieri
parent
a3cd76b6f2
commit
c6763bd2ca
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@ -36,6 +36,11 @@ zephyr_library_sources_ifdef(
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i3c_cdns.c
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)
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zephyr_library_sources_ifdef(
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CONFIG_I3C_NPCX
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i3c_npcx.c
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)
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zephyr_library_sources_ifdef(
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CONFIG_I3C_TEST
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i3c_test.c
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@ -109,6 +109,7 @@ comment "Device Drivers"
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rsource "Kconfig.nxp"
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rsource "Kconfig.cdns"
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rsource "Kconfig.npcx"
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rsource "Kconfig.test"
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endif # I3C
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35
drivers/i3c/Kconfig.npcx
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35
drivers/i3c/Kconfig.npcx
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@ -0,0 +1,35 @@
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# NPCX I3C driver configuration options
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# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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DT_I3C_NPCX := $(dt_nodelabel_path,i3c0)
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config I3C_NPCX
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bool "Nuvoton NPCX embedded controller (EC) I3C driver"
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depends on DT_HAS_NUVOTON_NPCX_I3C_ENABLED
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select RESET
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select I3C_IBI_WORKQUEUE if I3C_USE_IBI
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default y
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help
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This option enables the I3C driver for NPCX family of
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processors.
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Say y if you wish to use I3C channels on NPCX MCU.
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# Expose this option when the 'reg' property includes the MDMA base address
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# as the second group in the phandle-array.
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# i.e. I3C node example in dtsi file.
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# i3c0: i3c@400f0000 {
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# ....
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# /* reg[0]: I3C_1 register, reg[1]: MDMA5 register */
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# reg-names = "i3c1", "mdma5";
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# reg = <0x400f0000 0x2000>,
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# <0x40011500 0x100>;
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# ....
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# }
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config I3C_NPCX_DMA
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bool "Nuvoton NPCX embedded controller (EC) serial driver DMA support"
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depends on I3C_NPCX && "$(dt_node_reg_addr_hex,$(DT_I3C_NPCX),1)" != 0
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default y
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help
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Enable support for npcx I3C DMA mode.
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2052
drivers/i3c/i3c_npcx.c
Normal file
2052
drivers/i3c/i3c_npcx.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -14,7 +14,7 @@
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#include "npcx4/npcx4-espi-vws-map.dtsi"
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/* npcx4 series low-voltage io controls mapping table */
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#include "npcx4/npcx4-lvol-ctrl-map.dtsi"
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/* npcx4 series reset mapping table*/
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/* npcx4 series reset mapping table */
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#include "zephyr/dt-bindings/reset/npcx4_reset.h"
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/* Device tree declarations of npcx soc family */
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52
dts/bindings/i3c/nuvoton,npcx-i3c.yaml
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52
dts/bindings/i3c/nuvoton,npcx-i3c.yaml
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@ -0,0 +1,52 @@
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# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Nuvoton I3C controller
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Representation:
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/* If CONFIG_I3C_NPCX is enabled, the suggested clock configuration is as follows: */
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&pcc {
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clock-frequency = <DT_FREQ_M(90)>; /* OFMCLK runs at 90MHz */
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core-prescaler = <3>; /* CORE_CLK runs at 30MHz */
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apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */
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apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */
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apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */
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apb4-prescaler = <3>; /* APB4_CLK runs at 30MHz */
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};
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&rst {
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status = "okay";
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};
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&i3c0 {
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status = "okay";
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/* I3C clock frequency suggestion = <PP_SCL, OD_SCL> */
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* Full speed = <12500000, 4170000>
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* Normal speed = <7500000, 1500000>
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*/
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i3c-scl-hz = <12500000>;
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i3c-od-scl-hz = <4170000>;
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};
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compatible: "nuvoton,npcx-i3c"
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include: [i3c-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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resets:
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required: true
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i3c-od-scl-hz:
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type: int
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description: |
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Open Drain Frequency for the I3C controller. When undefined, use
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the controller default or as specified by the I3C specification.
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@ -78,7 +78,10 @@ struct cdcg_reg {
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volatile uint8_t reserved7;
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/* 0x014: HFCG Bus Clock Dividers */
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volatile uint8_t HFCBCD2;
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volatile uint8_t reserved8[235];
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volatile uint8_t reserved12[8];
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/* 0x01d: HFCG Bus Clock Dividers */
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volatile uint8_t HFCBCD3;
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volatile uint8_t reserved8[226];
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/* Low Frequency Clock Generator (LFCG) registers */
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/* 0x100: LFCG Control */
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@ -1764,4 +1767,223 @@ struct swrst_reg {
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volatile uint32_t SWRST_CTL[4];
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};
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/* Improved Inter Integrated Circuit (I3C) device registers */
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struct i3c_reg {
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/* 0x000: Controller Configuration */
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volatile uint32_t MCONFIG;
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/* 0x004: Target Configuration */
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volatile uint32_t CONFIG;
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volatile uint32_t reserved1[31];
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/* 0x084: Controller Control */
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volatile uint32_t MCTRL;
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/* 0x088: Controller Status */
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volatile uint32_t MSTATUS;
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/* 0x08C: IBI Registry and Rules */
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volatile uint32_t IBIRULES;
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/* 0x090: Controller Interrupt Enable Set */
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volatile uint32_t MINTSET;
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/* 0x094: Controller Interrupt Enable Clear */
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volatile uint32_t MINTCLR;
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/* 0x098: Controller Interrupt Masked */
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volatile uint32_t MINTMASKED;
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/* 0x09C: Controller Error and Warning */
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volatile uint32_t MERRWARN;
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/* 0x0A0: Controller DMA Control */
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volatile uint32_t MDMACTRL;
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volatile uint32_t reserved2[2];
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/* 0x0AC: Controller Data Control */
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volatile uint32_t MDATACTRL;
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/* 0x0B0: Controller Write Byte Data */
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volatile uint32_t MWDATAB;
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/* 0x0B4: Controller Write Byte Data as End */
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volatile uint32_t MWDATABE;
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/* 0x0B8: Controller Write Half-Word Data */
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volatile uint32_t MWDATAH;
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/* 0x0BC: Controller Write Half-Word Data as End */
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volatile uint32_t MWDATAHE;
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/* 0x0C0: Controller Read Byte Data */
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volatile uint32_t MRDATAB;
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volatile uint32_t reserved3;
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/* 0x0C8: Controller Read Half-Word Data */
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volatile uint32_t MRDATAH;
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volatile uint32_t reserved4[3];
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/* 0x0D8: Start or Continue DDR Message */
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volatile uint32_t MWMSG_DDR;
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/* 0x0DC: Read DDR Message Data */
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volatile uint32_t MRMSG_DDR;
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volatile uint32_t reserved5;
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/* 0x0E4: Controller Dynamic Address */
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volatile uint32_t MDYNADDR;
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};
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/* I3C register fields */
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#define NPCX_I3C_CONFIG_BAMATCH FIELD(16, 7)
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#define NPCX_I3C_MCONFIG_CTRENA FIELD(0, 2)
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#define NPCX_I3C_MCONFIG_DISTO 3
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#define NPCX_I3C_MCONFIG_HKEEP FIELD(4, 2) /* Must be '11' */
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#define NPCX_I3C_MCONFIG_ODSTOP 6
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#define NPCX_I3C_MCONFIG_PPBAUD FIELD(8, 4)
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#define NPCX_I3C_MCONFIG_PPLOW FIELD(12, 4)
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#define NPCX_I3C_MCONFIG_ODBAUD FIELD(16, 8)
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#define NPCX_I3C_MCONFIG_ODHPP 24
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#define NPCX_I3C_MCONFIG_SKEW FIELD(25, 3)
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#define NPCX_I3C_MCONFIG_I2CBAUD FIELD(28, 4)
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#define NPCX_I3C_MCTRL_REQUEST FIELD(0, 3)
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#define NPCX_I3C_MCTRL_TYPE FIELD(4, 2)
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#define NPCX_I3C_MCTRL_IBIRESP FIELD(6, 2)
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#define NPCX_I3C_MCTRL_DIR 8
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#define NPCX_I3C_MCTRL_ADDR FIELD(9, 7)
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#define NPCX_I3C_MCTRL_RDTERM FIELD(16, 8)
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#define NPCX_I3C_MSTATUS_STATE FIELD(0, 3)
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#define NPCX_I3C_MSTATUS_BETWEEN 4
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#define NPCX_I3C_MSTATUS_NACKED 5
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#define NPCX_I3C_MSTATUS_IBITYPE FIELD(6, 2)
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#define NPCX_I3C_MSTATUS_TGTSTART 8
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#define NPCX_I3C_MSTATUS_MCTRLDONE 9
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#define NPCX_I3C_MSTATUS_COMPLETE 10
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#define NPCX_I3C_MSTATUS_RXPEND 11
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#define NPCX_I3C_MSTATUS_TXNOTFULL 12
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#define NPCX_I3C_MSTATUS_IBIWON 13
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#define NPCX_I3C_MSTATUS_ERRWARN 15
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#define NPCX_I3C_MSTATUS_NOWCNTLR 19
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#define NPCX_I3C_MSTATUS_IBIADDR FIELD(24, 7)
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#define NPCX_I3C_IBIRULES_MSB0 30
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#define NPCX_I3C_IBIRULES_NOBYTE 31
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#define NPCX_I3C_MINTSET_TGTSTART 8
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#define NPCX_I3C_MINTSET_MCTRLDONE 9
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#define NPCX_I3C_MINTSET_COMPLETE 10
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#define NPCX_I3C_MINTSET_RXPEND 11
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#define NPCX_I3C_MINTSET_TXNOTFULL 12
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#define NPCX_I3C_MINTSET_IBIWON 13
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#define NPCX_I3C_MINTSET_ERRWARN 15
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#define NPCX_I3C_MINTSET_NOWCNTLR 19
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#define NPCX_I3C_MINTCLR_TGTSTART 8
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#define NPCX_I3C_MINTCLR_MCTRLDONE 9
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#define NPCX_I3C_MINTCLR_COMPLETE 10
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#define NPCX_I3C_MINTCLR_RXPEND 11
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#define NPCX_I3C_MINTCLR_TXNOTFULL 12
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#define NPCX_I3C_MINTCLR_IBIWON 13
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#define NPCX_I3C_MINTCLR_ERRWARN 15
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#define NPCX_I3C_MINTCLR_NOWCNTLR 19
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#define NPCX_I3C_MDATACTRL_FLUSHTB 0
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#define NPCX_I3C_MDATACTRL_FLUSHFB 1
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#define NPCX_I3C_MDATACTRL_UNLOCK 3
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#define NPCX_I3C_MDATACTRL_TXTRIG FIELD(4, 2)
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#define NPCX_I3C_MDATACTRL_RXTRIG FIELD(6, 2)
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#define NPCX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5)
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#define NPCX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5)
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#define NPCX_I3C_MDATACTRL_TXFULL 30
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#define NPCX_I3C_MDATACTRL_RXEMPTY 31
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#define NPCX_I3C_MERRWARN_NACK 2
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#define NPCX_I3C_MERRWARN_WRABT 3
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#define NPCX_I3C_MERRWARN_TERM 4
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#define NPCX_I3C_MERRWARN_HPAR 9
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#define NPCX_I3C_MERRWARN_HCRC 10
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#define NPCX_I3C_MERRWARN_OREAD 16
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#define NPCX_I3C_MERRWARN_OWRITE 17
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#define NPCX_I3C_MERRWARN_MSGERR 18
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#define NPCX_I3C_MERRWARN_INVERQ 19
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#define NPCX_I3C_MERRWARN_TIMEOUT 20
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#define NPCX_I3C_MDMACTRL_DMAFB FIELD(0, 2)
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#define NPCX_I3C_MDMACTRL_DMATB FIELD(2, 2)
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/* MCONFIG options */
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#define MCONFIG_CTRENA_OFF 0x0
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#define MCONFIG_CTRENA_ON 0x1
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#define MCONFIG_CTRENA_CAPABLE 0x2
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#define MCONFIG_HKEEP_EXT_SDA_SCL 0x3
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/* MCTRL options */
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#define MCTRL_REQUEST_NONE 0 /* None */
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#define MCTRL_REQUEST_EMITSTARTADDR 1 /* Emit a START */
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#define MCTRL_REQUEST_EMITSTOP 2 /* Emit a STOP */
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#define MCTRL_REQUEST_IBIACKNACK 3 /* Manually ACK or NACK an IBI */
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#define MCTRL_REQUEST_PROCESSDAA 4 /* Starts the DAA process */
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#define MCTRL_REQUEST_FORCEEXIT 6 /* Emit HDR Exit Pattern */
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/* Emits a START with address 7Eh when a slave pulls I3C_SDA low to request an IBI */
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#define MCTRL_REQUEST_AUTOIBI 7
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/* ACK with mandatory byte determined by IBIRULES or ACK with no mandatory byte */
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#define MCTRL_IBIRESP_ACK 0
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#define MCTRL_IBIRESP_NACK 1 /* NACK */
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#define MCTRL_IBIRESP_ACK_MANDATORY 2 /* ACK with mandatory byte */
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#define MCTRL_IBIRESP_MANUAL 3
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enum npcx_i3c_mctrl_type {
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NPCX_I3C_MCTRL_TYPE_I3C,
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NPCX_I3C_MCTRL_TYPE_I2C,
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NPCX_I3C_MCTRL_TYPE_I3C_HDR_DDR,
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};
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/* MSTATUS options */
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#define MSTATUS_STATE_IDLE 0x0
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#define MSTATUS_STATE_TGTREQ 0x1
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#define MSTATUS_STATE_NORMACT 0x3 /* SDR message mode */
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#define MSTATUS_STATE_MSGDDR 0x4
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#define MSTATUS_STATE_DAA 0x5
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#define MSTATUS_STATE_IBIACK 0x6
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#define MSTATUS_STATE_IBIRCV 0x7
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#define MSTATUS_IBITYPE_NONE 0x0
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#define MSTATUS_IBITYPE_IBI 0x1
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#define MSTATUS_IBITYPE_CR 0x2
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#define MSTATUS_IBITYPE_HJ 0x3
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/* IBIRULES */
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#define IBIRULES_ADDR_MSK 0x3F
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#define IBIRULES_ADDR_SHIFT 0x6
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/* MDMACTRL options */
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#define MDMA_DMAFB_DISABLE 0x0
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#define MDMA_DMAFB_EN_ONE_FRAME 0x1
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#define MDMA_DMAFB_EN_MANUAL 0x2
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#define MDMA_DMATB_DISABLE 0x0
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#define MDMA_DMATB_EN_ONE_FRAME 0x1
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#define MDMA_DMATB_EN_MANUAL 0x2
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/* MDMA Controller registers */
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struct mdma_reg {
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/* Channel 0 */
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/* 0x000: Channel 0 Control */
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volatile uint32_t MDMA_CTL0;
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/* 0x004: Channel 0 Source Base Address */
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volatile uint32_t MDMA_SRCB0;
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/* 0x008: Channel 0 Destination Base Address */
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volatile uint32_t MDMA_DSTB0;
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/* 0x00C: Channel 0 Transfer Count */
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volatile uint32_t MDMA_TCNT0;
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/* 0x010: reserved1 */
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volatile uint32_t reserved1;
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/* 0x014: Channel 0 Current Destination */
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volatile uint32_t MDMA_CDST0;
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/* 0x018: Channel 0 Current Transfer Count */
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volatile uint32_t MDMA_CTCNT0;
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/* 0x01C: reserved2 */
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volatile uint32_t reserved2;
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/* Channel 1 */
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/* 0x020: Channel 1 Control */
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volatile uint32_t MDMA_CTL1;
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/* 0x024: Channel 1 Source Base Address */
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volatile uint32_t MDMA_SRCB1;
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/* 0x028: Channel 1 Destination Base Address */
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volatile uint32_t MDMA_DSTB1;
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/* 0x02C: Channel 1 Transfer Count */
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volatile uint32_t MDMA_TCNT1;
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/* 0x030: Channel 1 Current Source */
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volatile uint32_t MDMA_CSRC1;
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/* 0x034: reserved3 */
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volatile uint32_t reserved3;
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/* 0x038: Channel 1 Current Transfer Count */
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volatile uint32_t MDMA_CTCNT1;
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};
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/* MDMA register fields */
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#define NPCX_MDMA_CTL_MDMAEN 0
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#define NPCX_MDMA_CTL_MPD 1
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#define NPCX_MDMA_CTL_SIEN 8
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#define NPCX_MDMA_CTL_MPS 14
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#define NPCX_MDMA_CTL_TC 18
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#define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 12)
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#endif /* _NUVOTON_NPCX_REG_DEF_H */
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@ -197,3 +197,30 @@ NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[0], 0x004);
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NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[1], 0x008);
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NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c);
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NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);
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/* I3C register structure check */
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NPCX_REG_SIZE_CHECK(i3c_reg, 0x0E8);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MCONFIG, 0x000);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MCTRL, 0x084);
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NPCX_REG_OFFSET_CHECK(i3c_reg, IBIRULES, 0x08C);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MINTSET, 0x090);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MINTCLR, 0x094);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MINTMASKED, 0x098);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MERRWARN, 0x09C);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MDATACTRL, 0x0AC);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MWDATAB, 0x0B0);
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NPCX_REG_OFFSET_CHECK(i3c_reg, MWDATABE, 0x0B4);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MWDATAH, 0x0B8);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MWDATAHE, 0x0BC);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MRDATAB, 0x0C0);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MRDATAH, 0x0C8);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MWMSG_DDR, 0x0D8);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MRMSG_DDR, 0x0DC);
|
||||
NPCX_REG_OFFSET_CHECK(i3c_reg, MDYNADDR, 0x0E4);
|
||||
|
||||
/* MDMA register structure check */
|
||||
NPCX_REG_SIZE_CHECK(mdma_reg, 0x03C);
|
||||
NPCX_REG_OFFSET_CHECK(mdma_reg, MDMA_SRCB0, 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(mdma_reg, MDMA_CTCNT0, 0x018);
|
||||
NPCX_REG_OFFSET_CHECK(mdma_reg, MDMA_CTL1, 0x020);
|
||||
NPCX_REG_OFFSET_CHECK(mdma_reg, MDMA_CTCNT1, 0x038);
|
||||
|
|
|
|||
|
|
@ -80,6 +80,20 @@
|
|||
.bit = DT_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), i, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Construct a npcx_clk_cfg structure from 'clocks' with the same clock 'name'.
|
||||
*
|
||||
* @param inst instance number for compatible defined in DT_DRV_COMPAT.
|
||||
* @param name name of the clock
|
||||
* @return npcx_clk_cfg item from 'clocks' property with the same clock 'name'
|
||||
*/
|
||||
#define NPCX_DT_CLK_CFG_ITEM_BY_NAME(inst, name) \
|
||||
{ \
|
||||
.bus = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, bus), \
|
||||
.ctrl = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, ctl), \
|
||||
.bit = DT_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, bit), \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Length of 'clocks' property which type is 'phandle-array'
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in a new issue