arch: riscv: define RISC_IRQ_MSOFT/MEXT

Instead of relying on spread definitions within SoC files.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>

arch/riscv/core/irq_manage.c

@@ -24,7 +24,7 @@ FUNC_NORETURN void z_irq_spurious(const void *unused)
 
 	LOG_ERR("Spurious interrupt detected! IRQ: %ld", mcause);
 #if defined(CONFIG_RISCV_HAS_PLIC)
-	if (mcause == RISCV_MACHINE_EXT_IRQ) {
+	if (mcause == RISCV_IRQ_MEXT) {
 		unsigned int save_irq = riscv_plic_get_irq();
 		const struct device *save_dev = riscv_plic_get_dev();
 

arch/riscv/core/smp.c

@@ -9,6 +9,7 @@
 #include <ksched.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/atomic.h>
+#include <zephyr/arch/riscv/irq.h>
 #include <zephyr/drivers/pm_cpu_ops.h>
 
 volatile struct {
@@ -67,7 +68,7 @@ void arch_secondary_cpu_init(int hartid)
 	z_riscv_pmp_init();
 #endif
 #ifdef CONFIG_SMP
-	irq_enable(RISCV_MACHINE_SOFT_IRQ);
+	irq_enable(RISCV_IRQ_MSOFT);
 #endif
 	riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
 }
@@ -154,8 +155,8 @@ void arch_spin_relax(void)
 int arch_smp_init(void)
 {
 
-	IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 0, sched_ipi_handler, NULL, 0);
-	irq_enable(RISCV_MACHINE_SOFT_IRQ);
+	IRQ_CONNECT(RISCV_IRQ_MSOFT, 0, sched_ipi_handler, NULL, 0);
+	irq_enable(RISCV_IRQ_MSOFT);
 
 	return 0;
 }

drivers/interrupt_controller/intc_swerv_pic.c

@@ -15,6 +15,7 @@
 #include <zephyr/device.h>
 #include <zephyr/sw_isr_table.h>
 #include <zephyr/irq.h>
+#include <zephyr/arch/riscv/irq.h>
 
 #define SWERV_PIC_MAX_NUM	CONFIG_NUM_IRQS
 #define SWERV_PIC_MAX_ID	(SWERV_PIC_MAX_NUM + RISCV_MAX_GENERIC_IRQ)
@@ -176,14 +177,14 @@ static int swerv_pic_init(const struct device *dev)
 	__asm__ swerv_pic_writecsr(meicurpl, 0);
 
 	/* Setup IRQ handler for SweRV PIC driver */
-	IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
+	IRQ_CONNECT(RISCV_IRQ_MEXT,
 		    0,
 		    swerv_pic_irq_handler,
 		    NULL,
 		    0);
 
 	/* Enable IRQ for SweRV PIC driver */
-	irq_enable(RISCV_MACHINE_EXT_IRQ);
+	irq_enable(RISCV_IRQ_MEXT);
 
 	return 0;
 }

drivers/interrupt_controller/intc_vexriscv_litex.c

@@ -11,6 +11,7 @@
 #include <zephyr/irq.h>
 #include <zephyr/device.h>
 #include <zephyr/types.h>
+#include <zephyr/arch/riscv/irq.h>
 
 #define IRQ_MASK		DT_INST_REG_ADDR_BY_NAME(0, irq_mask)
 #define IRQ_PENDING		DT_INST_REG_ADDR_BY_NAME(0, irq_pending)
@@ -122,9 +123,9 @@ int arch_irq_is_enabled(unsigned int irq)
 static int vexriscv_litex_irq_init(const struct device *dev)
 {
 	__asm__ volatile ("csrrs x0, mie, %0"
-			:: "r"(1 << RISCV_MACHINE_EXT_IRQ));
+			:: "r"(1 << RISCV_IRQ_MEXT));
 	vexriscv_litex_irq_setie(1);
-	IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ, 0, vexriscv_litex_irq_handler,
+	IRQ_CONNECT(RISCV_IRQ_MEXT, 0, vexriscv_litex_irq_handler,
 			NULL, 0);
 
 	return 0;

drivers/mbox/mbox_andes_plic_sw.c

@@ -199,11 +199,11 @@ static void andes_plic_sw_irq_handler(const struct device *dev)
 static int mbox_andes_init(const struct device *dev)
 {
 	/* Setup IRQ handler for PLIC SW driver */
-	IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 1,
+	IRQ_CONNECT(RISCV_IRQ_MSOFT, 1,
 		    andes_plic_sw_irq_handler, DEVICE_DT_INST_GET(0), 0);
 
 #ifndef CONFIG_SMP
-	irq_enable(RISCV_MACHINE_SOFT_IRQ);
+	irq_enable(RISCV_IRQ_MSOFT);
 #endif
 	return 0;
 }

include/zephyr/arch/riscv/irq.h

@@ -32,6 +32,13 @@ extern "C" {
 /** Environment Call from M-mode */
 #define RISCV_EXC_ECALLM 11
 
+/* IRQs 0-15 (MCAUSE interrupt=1) */
+
+/** Machine Software Interrupt */
+#define RISCV_IRQ_MSOFT 3
+/** Machine External Interrupt */
+#define RISCV_IRQ_MEXT  11
+
 #ifdef CONFIG_64BIT
 #define RISCV_MCAUSE_IRQ_BIT          (1 << 63)
 #else

soc/riscv/common/riscv-privileged/soc_common.h

@@ -12,10 +12,6 @@
 #ifndef __SOC_COMMON_H_
 #define __SOC_COMMON_H_
 
-/* IRQ numbers */
-#define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
-#define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
-
 #ifndef _ASMLANGUAGE
 
 #include <zephyr/drivers/interrupt_controller/riscv_clic.h>

soc/riscv/espressif_esp32/esp32c3/soc.h

@@ -16,11 +16,6 @@
 #include "esp32c3/clk.h"
 #endif
 
-/* IRQ numbers */
-#define RISCV_MACHINE_SOFT_IRQ 3 /* Machine Software Interrupt */
-#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
-#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
-
 #ifndef _ASMLANGUAGE
 
 void __esp_platform_start(void);