soc: st: stm32: adding option to enable prefetch buffer
For more effective code execution on STM32 devices is convenient to enable flash prefetch buffer. To be enabled by default, possible to disable using kconfig. Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
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@ -47,6 +47,9 @@ config SWJ_ANALOG_PRIORITY
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This priority must be greater than GPIO_INIT_PRIORITY and lower than
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This priority must be greater than GPIO_INIT_PRIORITY and lower than
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UART_INIT_PRIORITY.
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UART_INIT_PRIORITY.
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config STM32_FLASH_PREFETCH
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bool "Flash prefetch buffer"
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choice POWER_SUPPLY_CHOICE
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choice POWER_SUPPLY_CHOICE
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prompt "STM32 power supply configuration"
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prompt "STM32 power supply configuration"
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default POWER_SUPPLY_LDO
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default POWER_SUPPLY_LDO
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@ -10,6 +10,9 @@ rsource "Kconfig.defconfig.stm32wba*"
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config STM32_LPTIM_TIMER
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config STM32_LPTIM_TIMER
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default y if PM
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default y if PM
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config STM32_FLASH_PREFETCH
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default y
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choice BT_HCI_BUS_TYPE
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choice BT_HCI_BUS_TYPE
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default BT_STM32WBA
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default BT_STM32WBA
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depends on BT
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depends on BT
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@ -37,6 +37,9 @@ int stm32wba_init(void)
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/* Enable instruction cache in 1-way (direct mapped cache) */
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/* Enable instruction cache in 1-way (direct mapped cache) */
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_Enable();
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LL_ICACHE_Enable();
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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#endif
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 16 MHz from HSI */
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/* At reset, system core clock is set to 16 MHz from HSI */
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