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arch/xtensa: Use ZSR assignments for the CPU pointer

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Use the zsr.h assignments for the special register containing the
current CPU pointer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2022-01-08 16:02:14 -08:00 committed by Anas Nashif
parent 82071be443
commit ca7024e1d6
11 changed files with 15 additions and 43 deletions
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7
arch/xtensa/Kconfig
View file

@ -55,13 +55,6 @@ config XTENSA_USE_CORE_CRT1
SoC or boards might define their own __start by setting this setting
to false.
config XTENSA_KERNEL_CPU_PTR_SR
string
default "MISC0"
help
Specify which special register to store the pointer to
_kernel.cpus[] for the current CPU.
config XTENSA_ENABLE_BACKTRACE
bool "Enable backtrace on panic exception"
default y

3
arch/xtensa/core/xtensa-asm2-util.S
View file

@ -6,6 +6,7 @@
#include <xtensa-asm2-s.h>
#include <offsets.h>
#include <toolchain.h>
#include <zsr.h>
/*
* xtensa_spill_reg_windows
@ -289,7 +290,7 @@ _switch_restore_pc:
*/
.align 4
_handle_excint:
EXCINT_HANDLER CONFIG_XTENSA_KERNEL_CPU_PTR_SR, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
EXCINT_HANDLER ZSR_CPU, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
/* Define the actual vectors for the hardware-defined levels with
* DEF_EXCINT. These load a C handler address and jump to our handler

14
arch/xtensa/include/kernel_arch_func.h
View file

@ -14,6 +14,7 @@
#include <kernel_internal.h>
#include <string.h>
#include <arch/xtensa/cache.h>
#include <zsr.h>
#ifdef __cplusplus
extern "C" {
@ -37,13 +38,14 @@ static ALWAYS_INLINE void arch_kernel_init(void)
cpu0->nested = 0;
/* The asm2 scheme keeps the kernel pointer in MISC0 for easy
* access. That saves 4 bytes of immediate value to store the
* address when compared to the legacy scheme. But in SMP
* this record is a per-CPU thing and having it stored in a SR
* already is a big win.
/* The asm2 scheme keeps the kernel pointer in a scratch SR
* (see zsr.h for generation specifics) for easy access. That
* saves 4 bytes of immediate value to store the address when
* compared to the legacy scheme. But in SMP this record is a
* per-CPU thing and having it stored in a SR already is a big
* win.
*/
WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0);
WSR(ZSR_CPU_STR, cpu0);
#ifdef CONFIG_INIT_STACKS
memset(Z_KERNEL_STACK_BUFFER(z_interrupt_stacks[0]), 0xAA,

3
include/arch/xtensa/arch_inlines.h
View file

@ -11,6 +11,7 @@
#ifndef _ASMLANGUAGE
#include <kernel_structs.h>
#include <zsr.h>
#define RSR(sr) \
({uint32_t v; \
@ -26,7 +27,7 @@ static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
{
_cpu_t *cpu;
cpu = (_cpu_t *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
cpu = (_cpu_t *)RSR(ZSR_CPU_STR);
return cpu;
}

5
soc/xtensa/intel_adsp/cavs_v15/Kconfig.defconfig.series
View file

@ -55,11 +55,6 @@ config SYS_CLOCK_TICKS_PER_SEC
config IRQ_OFFLOAD_INTNUM
default 0
# This series does not have MISC0.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
config KERNEL_ENTRY
default "_MainEntry"

5
soc/xtensa/intel_adsp/cavs_v18/Kconfig.defconfig.series
View file

@ -41,11 +41,6 @@ config SYS_CLOCK_TICKS_PER_SEC
config IRQ_OFFLOAD_INTNUM
default 0
# This series does not have MISC0.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
config KERNEL_ENTRY
default "_MainEntry"

5
soc/xtensa/intel_adsp/cavs_v20/Kconfig.defconfig.series
View file

@ -41,11 +41,6 @@ config SYS_CLOCK_TICKS_PER_SEC
config IRQ_OFFLOAD_INTNUM
default 0
# This series does not have MISC0.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
config KERNEL_ENTRY
default "_MainEntry"

5
soc/xtensa/intel_adsp/cavs_v25/Kconfig.defconfig.series
View file

@ -38,11 +38,6 @@ config SYS_CLOCK_TICKS_PER_SEC
config IRQ_OFFLOAD_INTNUM
default 0
# This series does not have MISC0.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE2"
config KERNEL_ENTRY
default "_MainEntry"

4
soc/xtensa/intel_adsp/common/soc_mp.c
View file

@ -17,6 +17,7 @@
#include <logging/log.h>
LOG_MODULE_REGISTER(soc_mp, CONFIG_SOC_LOG_LEVEL);
#include <zsr.h>
#include <cavs-idc.h>
#include <soc.h>
#include <arch/xtensa/cache.h>
@ -92,8 +93,7 @@ __imr void z_mp_entry(void)
/* Set up the CPU pointer. */
_cpu_t *cpu = &_kernel.cpus[start_rec.cpu];
__asm__ volatile(
"wsr." CONFIG_XTENSA_KERNEL_CPU_PTR_SR " %0" : : "r"(cpu));
__asm__ volatile("wsr %0, " ZSR_CPU_STR :: "r"(cpu));
soc_mp_startup(start_rec.cpu);
soc_cpus_active[start_rec.cpu] = true;

5
soc/xtensa/intel_s1000/Kconfig.defconfig
View file

@ -19,11 +19,6 @@ config SOC_TOOLCHAIN_NAME
config IRQ_OFFLOAD_INTNUM
default 0
# S1000 does not have MISC0.
# Since EXCSAVE7 is unused by Zephyr, use it instead.
config XTENSA_KERNEL_CPU_PTR_SR
default "EXCSAVE7"
config SPI_DW_FIFO_DEPTH
default 32

2
soc/xtensa/intel_s1000/soc_mp.c
View file

@ -66,7 +66,7 @@ static void mp_entry2(void)
_cpu_t *cpu = &_kernel.cpus[start_rec.cpu];
__asm__ volatile(
"wsr." CONFIG_XTENSA_KERNEL_CPU_PTR_SR " %0" : : "r"(cpu));
"wsr." ZSR_CPU_STR " %0" : : "r"(cpu));
#ifdef CONFIG_IPM_CAVS_IDC
/* Interrupt must be enabled while running on current core */