soc: atmel: add base support for C2x SOC

Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.

The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.

The code is inspirated from atmel_sam0/samd21.

Signed-off-by: Kamil Serwus <kserwus@gmail.com>

drivers/flash/Kconfig.sam0

@@ -16,6 +16,8 @@ menuconfig SOC_FLASH_SAM0
 config SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
 	bool "Emulate byte-sized pages"
 	depends on SOC_FLASH_SAM0
+	default y if SOC_SERIES_SAMC20 || \
+		     SOC_SERIES_SAMC21
 	help
 	  Emulate a device with byte-sized pages by doing a
 	  read/modify/erase/write.

dts/arm/atmel/samc20x15.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x16.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x17.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x18.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21.dtsi

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include <atmel/samc2x.dtsi>
+
+/ {
+	aliases {
+		sercom-4 = &sercom4;
+		sercom-5 = &sercom5;
+	};
+
+	soc {
+		adc1: adc@42004800 {
+			compatible = "atmel,sam0-adc";
+			status = "disabled";
+			reg = <0x42004800 0x30>;
+			interrupts = <26 0>;
+			interrupt-names = "resrdy";
+			clocks = <&gclk 34>, <&mclk 0x1c 18>;
+			clock-names = "GCLK", "MCLK";
+			gclk = <0>;
+			prescaler = <4>;
+			#io-channel-cells = <1>;
+		};
+
+		sercom4: sercom@42001400 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42001400 0x40>;
+			interrupts = <13 0>;
+			clocks = <&gclk 23>, <&mclk 0x1c 5>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		sercom5: sercom@42001800 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42001800 0x40>;
+			interrupts = <14 0>;
+			clocks = <&gclk 25>, <&mclk 0x1c 6>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+	};
+};

dts/arm/atmel/samc21x15.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x16.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x17.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x18.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc2x.dtsi

@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv6-m.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	aliases {
+		watchdog0 = &wdog;
+	};
+
+	chosen {
+		zephyr,flash-controller = &nvmctrl;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	id: device_id@80a00c {
+		compatible = "atmel,sam0-id";
+		reg =	<0x0080A00C 0x4>,
+			<0x0080A040 0x4>,
+			<0x0080A044 0x4>,
+			<0x0080A048 0x4>;
+	};
+
+	aliases {
+		port-a = &porta;
+		port-b = &portb;
+		port-c = &portc;
+
+		sercom-0 = &sercom0;
+		sercom-1 = &sercom1;
+		sercom-2 = &sercom2;
+		sercom-3 = &sercom3;
+
+		tcc-0 = &tcc0;
+		tcc-1 = &tcc1;
+		tcc-2 = &tcc2;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			compatible = "atmel,sam0-nvmctrl";
+			reg = <0x41004000 0x22>;
+			interrupts = <6 0>;
+			lock-regions = <16>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				write-block-size = <4>;
+			};
+		};
+
+		mclk: mclk@40000800 {
+			compatible = "atmel,samc2x-mclk";
+			reg = <0x40000800 0x400>;
+			#clock-cells = <2>;
+		};
+
+		gclk: gclk@40001c00 {
+			compatible = "atmel,samc2x-gclk";
+			reg = <0x40001c00 0x400>;
+			#clock-cells = <1>;
+		};
+
+		eic: eic@40002800 {
+			compatible = "atmel,sam0-eic";
+			reg = <0x40002800 0x1C>;
+			interrupts = <3 0>;
+		};
+
+		pinmux_a: pinmux@41000000 {
+			compatible = "atmel,sam0-pinmux";
+			reg = <0x41000000 0x80>;
+		};
+
+		wdog: watchdog@40002000 {
+			compatible = "atmel,sam0-watchdog";
+			reg = <0x40002000 9>;
+			interrupts = <1 0>;
+		};
+
+		adc0: adc@42004400 {
+			compatible = "atmel,sam0-adc";
+			status = "disabled";
+			reg = <0x42004400 0x30>;
+			interrupts = <25 0>;
+			interrupt-names = "resrdy";
+			clocks = <&gclk 33>, <&mclk 0x1c 17>;
+			clock-names = "GCLK", "MCLK";
+			gclk = <0>;
+			prescaler = <4>;
+			#io-channel-cells = <1>;
+		};
+
+		sercom0: sercom@42000400 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42000400 0x40>;
+			interrupts = <9 0>;
+			clocks = <&gclk 19>, <&mclk 0x1c 1>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		sercom1: sercom@42000800 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42000800 0x40>;
+			interrupts = <10 0>;
+			clocks = <&gclk 20>, <&mclk 0x1c 2>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		sercom2: sercom@42000c00 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42000c00 0x40>;
+			interrupts = <11 0>;
+			clocks = <&gclk 21>, <&mclk 0x1c 3>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		sercom3: sercom@42001000 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42001000 0x40>;
+			interrupts = <12 0>;
+			clocks = <&gclk 22>, <&mclk 0x1c 4>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		tcc0: tcc@42002400 {
+			compatible = "atmel,sam0-tcc";
+			reg = <0x42002400 0x80>;
+			interrupts = <17 0>;
+			clocks = <&gclk 28>, <&mclk 0x1c 9>;
+			clock-names = "GCLK", "MCLK";
+
+			channels = <4>;
+			counter-size = <24>;
+		};
+
+		tcc1: tcc@42002800 {
+			compatible = "atmel,sam0-tcc";
+			reg = <0x42002800 0x80>;
+			interrupts = <18 0>;
+			clocks = <&gclk 28>, <&mclk 0x1c 10>;
+			clock-names = "GCLK", "MCLK";
+
+			channels = <4>;
+			counter-size = <24>;
+		};
+
+		tcc2: tcc@42002c00 {
+			compatible = "atmel,sam0-tcc";
+			reg = <0x42002c00 0x80>;
+			interrupts = <19 0>;
+			clocks = <&gclk 29>, <&mclk 0x1c 11>;
+			clock-names = "GCLK", "MCLK";
+
+			channels = <2>;
+			counter-size = <16>;
+		};
+
+		pinctrl: pinctrl@41000000 {
+			compatible = "atmel,sam0-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x41000000 0x41000000 0x180>;
+
+			porta: gpio@41000000 {
+				compatible = "atmel,sam0-gpio";
+				reg = <0x41000000 0x80>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				#atmel,pin-cells = <2>;
+			};
+
+			portb: gpio@41000080 {
+				compatible = "atmel,sam0-gpio";
+				reg = <0x41000080 0x80>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				#atmel,pin-cells = <2>;
+			};
+
+			portc: gpio@41000100 {
+				compatible = "atmel,sam0-gpio";
+				reg = <0x41000100 0x80>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				#atmel,pin-cells = <2>;
+			};
+		};
+
+		rtc: rtc@40002400 {
+			compatible = "atmel,sam0-rtc";
+			reg = <0x40002400 0x1C>;
+			interrupts = <3 0>;
+			clock-generator = <0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};

dts/bindings/clock/atmel,samc2x-gclk.yaml

@@ -0,0 +1,18 @@
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMC2x Generic Clock Controller (GCLK)
+
+compatible: "atmel,samc2x-gclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - periph_ch

dts/bindings/clock/atmel,samc2x-mclk.yaml

@@ -0,0 +1,19 @@
+# Copyright (c) 2022, Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMC2x Generic Clock Controller (MCLK)
+
+compatible: "atmel,samc2x-mclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - offset
+  - bit

soc/arm/atmel_sam0/Kconfig

@@ -13,6 +13,7 @@ config SOC_FAMILY
 	string
 	default "atmel_sam0"
 
+source "soc/arm/atmel_sam0/common/Kconfig.samc2x"
 source "soc/arm/atmel_sam0/common/Kconfig.saml2x"
 source "soc/arm/atmel_sam0/common/Kconfig.samd2x"
 source "soc/arm/atmel_sam0/common/Kconfig.samd5x"

soc/arm/atmel_sam0/common/CMakeLists.txt

@@ -7,6 +7,8 @@ zephyr_sources(soc_port.c)
 
 zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c)
 
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC20 soc_samc2x.c)
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMC21 soc_samc2x.c)
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD20 soc_samd2x.c)
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMD21 soc_samd2x.c)
 zephyr_sources_ifdef(CONFIG_SOC_SERIES_SAMR21 soc_samd2x.c)

soc/arm/atmel_sam0/common/Kconfig.samc2x

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMC20 || SOC_SERIES_SAMC21
+
+endif

soc/arm/atmel_sam0/common/soc_samc2x.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Atmel SAMC MCU series initialization code
+ */
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <soc.h>
+
+static void flash_waitstates_init(void)
+{
+	/* One wait state at 48 MHz. */
+	NVMCTRL->CTRLB.bit.RWS = NVMCTRL_CTRLB_RWS_HALF_Val;
+}
+
+static void osc48m_init(void)
+{
+	/* Turn off the prescaler */
+	OSCCTRL->OSC48MDIV.bit.DIV = 0;
+	while (OSCCTRL->OSC48MSYNCBUSY.bit.OSC48MDIV) {
+	}
+	while (!OSCCTRL->STATUS.bit.OSC48MRDY) {
+	}
+}
+
+static void mclk_init(void)
+{
+	MCLK->CPUDIV.reg = MCLK_CPUDIV_CPUDIV_DIV1_Val;
+}
+
+static void gclks_init(void)
+{
+	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M)
+			     | GCLK_GENCTRL_DIV(1)
+			     | GCLK_GENCTRL_GENEN;
+}
+
+static int atmel_samc_init(const struct device *arg)
+{
+	uint32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	flash_waitstates_init();
+	osc48m_init();
+	mclk_init();
+	gclks_init();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	return 0;
+}
+
+SYS_INIT(atmel_samc_init, PRE_KERNEL_1, 0);

soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Atmel SAMC MCU series configuration options
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMC20
+
+config SOC_SERIES
+	default "samc20"
+
+config SOC_PART_NUMBER
+	default "samc20e15a" if SOC_PART_NUMBER_SAMC20E15A
+	default "samc20e16a" if SOC_PART_NUMBER_SAMC20E16A
+	default "samc20e17a" if SOC_PART_NUMBER_SAMC20E17A
+	default "samc20e18a" if SOC_PART_NUMBER_SAMC20E18A
+	default "samc20g15a" if SOC_PART_NUMBER_SAMC20G15A
+	default "samc20g16a" if SOC_PART_NUMBER_SAMC20G16A
+	default "samc20g17a" if SOC_PART_NUMBER_SAMC20G17A
+	default "samc20g18a" if SOC_PART_NUMBER_SAMC20G18A
+	default "samc20j15a" if SOC_PART_NUMBER_SAMC20J15A
+	default "samc20j16a" if SOC_PART_NUMBER_SAMC20J16A
+	default "samc20j17a" if SOC_PART_NUMBER_SAMC20J17A
+	default "samc20j17au" if SOC_PART_NUMBER_SAMC20J17AU
+	default "samc20j18a" if SOC_PART_NUMBER_SAMC20J18A
+	default "samc20j18au" if SOC_PART_NUMBER_SAMC20J18AU
+	default "samc20n17a" if SOC_PART_NUMBER_SAMC20N17A
+	default "samc20n18a" if SOC_PART_NUMBER_SAMC20N18A
+
+config NUM_IRQS
+	default 32
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default	$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+endif # SOC_SERIES_SAMC20

soc/arm/atmel_sam0/samc20/Kconfig.series

@@ -0,0 +1,15 @@
+# Atmel SAMC20 MCU series
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMC20
+	bool "Atmel SAMC20 MCU"
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select SOC_FAMILY_SAM0
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select ASF
+	help
+	  Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers.

soc/arm/atmel_sam0/samc20/Kconfig.soc

@@ -0,0 +1,60 @@
+# Atmel SAMC MCU series
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Atmel SAMC20 MCU Selection"
+	depends on SOC_SERIES_SAMC20
+
+config SOC_PART_NUMBER_SAMC20E15A
+	bool "SAMC20E15A"
+
+config SOC_PART_NUMBER_SAMC20E16A
+	bool "SAMC20E16A"
+
+config SOC_PART_NUMBER_SAMC20E17A
+	bool "SAMC20E17A"
+
+config SOC_PART_NUMBER_SAMC20E18A
+	bool "SAMC20E18A"
+
+config SOC_PART_NUMBER_SAMC20G15A
+	bool "SAMC20G15A"
+
+config SOC_PART_NUMBER_SAMC20G16A
+	bool "SAMC20G16A"
+
+config SOC_PART_NUMBER_SAMC20G17A
+	bool "SAMC20G17A"
+
+config SOC_PART_NUMBER_SAMC20G18A
+	bool "SAMC20G18A"
+
+config SOC_PART_NUMBER_SAMC20J15A
+	bool "SAMC20J15A"
+
+config SOC_PART_NUMBER_SAMC20J16A
+	bool "SAMC20J16A"
+
+config SOC_PART_NUMBER_SAMC20J17A
+	bool "SAMC20J17A"
+
+config SOC_PART_NUMBER_SAMC20J17AU
+	bool "SAMC20J17AU"
+
+config SOC_PART_NUMBER_SAMC20J18A
+	bool "SAMC20J18A"
+
+config SOC_PART_NUMBER_SAMC20J18AU
+	bool "SAMC20J18AU"
+
+config SOC_PART_NUMBER_SAMC20N17A
+	bool "SAMC20N17A"
+	select SOC_SERIES_REVISION_N
+
+config SOC_PART_NUMBER_SAMC20N18A
+	bool "SAMC20N18A"
+	select SOC_SERIES_REVISION_N
+
+endchoice

soc/arm/atmel_sam0/samc20/linker.ld

@@ -0,0 +1,8 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2017 Google LLC.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/atmel_sam0/samc20/soc.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ATMEL_SAMC_SOC_H_
+#define _ATMEL_SAMC_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#define DONT_USE_CMSIS_INIT
+
+#include <zephyr/types.h>
+
+
+#if defined(CONFIG_SOC_PART_NUMBER_SAMC20E15A)
+#include <samc20e15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E16A)
+#include <samc20e16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E17A)
+#include <samc20e17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E18A)
+#include <samc20e18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G15A)
+#include <samc20g15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G16A)
+#include <samc20g16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G17A)
+#include <samc20g17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G18A)
+#include <samc20g18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J15A)
+#include <samc20j15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J16A)
+#include <samc20j16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17A)
+#include <samc20j17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17AU)
+#include <samc20j17au.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18A)
+#include <samc20j18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18AU)
+#include <samc20j18au.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N17A)
+#include <samc20n17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N18A)
+#include <samc20n18a.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#include "adc_fixup_sam0.h"
+#include "../common/soc_port.h"
+#include "../common/atmel_sam0_dt.h"
+
+#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
+
+/** Processor Clock (HCLK) Frequency */
+#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+/** Master Clock (MCK) Frequency */
+#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
+#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
+
+#endif /* _ATMEL_SAMD51_SOC_H_ */

soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Atmel SAMC MCU series configuration options
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMC21
+
+config SOC_SERIES
+	default "samc21"
+
+config SOC_PART_NUMBER
+	default "samc21e15a" if SOC_PART_NUMBER_SAMC21E15A
+	default "samc21e16a" if SOC_PART_NUMBER_SAMC21E16A
+	default "samc21e17a" if SOC_PART_NUMBER_SAMC21E17A
+	default "samc21e18a" if SOC_PART_NUMBER_SAMC21E18A
+	default "samc21g15a" if SOC_PART_NUMBER_SAMC21G15A
+	default "samc21g16a" if SOC_PART_NUMBER_SAMC21G16A
+	default "samc21g17a" if SOC_PART_NUMBER_SAMC21G17A
+	default "samc21g18a" if SOC_PART_NUMBER_SAMC21G18A
+	default "samc21j15a" if SOC_PART_NUMBER_SAMC21J15A
+	default "samc21j16a" if SOC_PART_NUMBER_SAMC21J16A
+	default "samc21j17a" if SOC_PART_NUMBER_SAMC21J17A
+	default "samc21j17au" if SOC_PART_NUMBER_SAMC21J17AU
+	default "samc21j18a" if SOC_PART_NUMBER_SAMC21J18A
+	default "samc21j18au" if SOC_PART_NUMBER_SAMC21J18AU
+	default "samc21n17a" if SOC_PART_NUMBER_SAMC21N17A
+	default "samc21n18a" if SOC_PART_NUMBER_SAMC21N18A
+
+config NUM_IRQS
+	default 32
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default	$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+endif # SOC_SERIES_SAMC21

soc/arm/atmel_sam0/samc21/Kconfig.series

@@ -0,0 +1,15 @@
+# Atmel SAMC21 MCU series
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMC21
+	bool "Atmel SAMC21 MCU"
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select SOC_FAMILY_SAM0
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select ASF
+	help
+	  Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers.

soc/arm/atmel_sam0/samc21/Kconfig.soc

@@ -0,0 +1,60 @@
+# Atmel SAMC MCU series
+
+# Copyright (c) 2022 Kamil Serwus
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "Atmel SAMC21 MCU Selection"
+	depends on SOC_SERIES_SAMC21
+
+config SOC_PART_NUMBER_SAMC21E15A
+	bool "SAMC21E15A"
+
+config SOC_PART_NUMBER_SAMC21E16A
+	bool "SAMC21E16A"
+
+config SOC_PART_NUMBER_SAMC21E17A
+	bool "SAMC21E17A"
+
+config SOC_PART_NUMBER_SAMC21E18A
+	bool "SAMC21E18A"
+
+config SOC_PART_NUMBER_SAMC21G15A
+	bool "SAMC21G15A"
+
+config SOC_PART_NUMBER_SAMC21G16A
+	bool "SAMC21G16A"
+
+config SOC_PART_NUMBER_SAMC21G17A
+	bool "SAMC21G17A"
+
+config SOC_PART_NUMBER_SAMC21G18A
+	bool "SAMC21G18A"
+
+config SOC_PART_NUMBER_SAMC21J15A
+	bool "SAMC21J15A"
+
+config SOC_PART_NUMBER_SAMC21J16A
+	bool "SAMC21J16A"
+
+config SOC_PART_NUMBER_SAMC21J17A
+	bool "SAMC21J17A"
+
+config SOC_PART_NUMBER_SAMC21J17AU
+	bool "SAMC21J17AU"
+
+config SOC_PART_NUMBER_SAMC21J18A
+	bool "SAMC21J18A"
+
+config SOC_PART_NUMBER_SAMC21J18AU
+	bool "SAMC21J18AU"
+
+config SOC_PART_NUMBER_SAMC21N17A
+	bool "SAMC21N17A"
+	select SOC_SERIES_REVISION_N
+
+config SOC_PART_NUMBER_SAMC21N18A
+	bool "SAMC21N18A"
+	select SOC_SERIES_REVISION_N
+
+endchoice

soc/arm/atmel_sam0/samc21/linker.ld

@@ -0,0 +1,8 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2017 Google LLC.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

soc/arm/atmel_sam0/samc21/soc.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ATMEL_SAMC_SOC_H_
+#define _ATMEL_SAMC_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#define DONT_USE_CMSIS_INIT
+
+#include <zephyr/types.h>
+
+
+#if defined(CONFIG_SOC_PART_NUMBER_SAMC21E15A)
+#include <samc21e15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E16A)
+#include <samc21e16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E17A)
+#include <samc21e17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E18A)
+#include <samc21e18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G15A)
+#include <samc21g15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G16A)
+#include <samc21g16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G17A)
+#include <samc21g17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G18A)
+#include <samc21g18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J15A)
+#include <samc21j15a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J16A)
+#include <samc21j16a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17A)
+#include <samc21j17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17AU)
+#include <samc21j17au.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18A)
+#include <samc21j18a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18AU)
+#include <samc21j18au.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N17A)
+#include <samc21n17a.h>
+#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N18A)
+#include <samc21n18a.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#include "adc_fixup_sam0.h"
+#include "../common/soc_port.h"
+#include "../common/atmel_sam0_dt.h"
+
+#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768
+
+/** Processor Clock (HCLK) Frequency */
+#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+/** Master Clock (MCK) Frequency */
+#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
+#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
+
+#endif /* _ATMEL_SAMD51_SOC_H_ */