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net: dsa: ksz8794: Fix the port numbering for this ETH switch IC

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After the "dts: ksz8974: add support for ksz8863"
(SHA1: b0e4886dfa) commit the port numbering
for KSZ8794 was wrong.

This IC has 3 ETH ports (with linear offset), with port 4 being the
"master" with non linear offset (i.e. 0x50 instead of linear 0x40).

Such situation can be explained with similarity of this IC to ksz8795,
which has 4 LAN ports, and then the 0x40 offset is used.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski 2021-11-10 15:08:22 +01:00 committed by Maureen Helm
parent ab1f0b55d5
commit cb4f7bc15c
1 changed files with 19 additions and 5 deletions
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24
drivers/ethernet/dsa_ksz8794.h
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@ -257,13 +257,27 @@
#define KSZ8794_GLOBAL_CTRL20_LOWSPEED_28MA 0x07
enum {
/*
* KSZ8794 register's MAP
* (0x00 - 0x0F): Global Registers
* Port registers (offsets):
* (0x10): Port 1
* (0x20): Port 2
* (0x30): Port 3
* (0x40): Reserved
* (0x50): Port 4
*/
/* LAN ports for the ksz8794 switch */
KSZ8794_PORT1 = 0,
KSZ8794_PORT2,
KSZ8794_PORT3,
KSZ8794_PORT4,
/* SWITCH <-> CPU port */
KSZ8794_PORT5,
/*
* SWITCH <-> CPU port
*
* We also need to consider the "Reserved' offset
* defined above.
*/
KSZ8794_PORT4 = 4,
};
#define KSZ8794_REG_IND_DATA_8 0x70
@ -287,8 +301,8 @@ enum {
#define KSZ8XXX_CHIP_ID0_ID_DEFAULT KSZ8794_CHIP_ID0_ID_DEFAULT
#define KSZ8XXX_CHIP_ID1_ID_DEFAULT KSZ8794_CHIP_ID1_ID_DEFAULT
#define KSZ8XXX_FIRST_PORT KSZ8794_PORT1
#define KSZ8XXX_LAST_PORT KSZ8794_PORT5
#define KSZ8XXX_CPU_PORT KSZ8794_PORT5
#define KSZ8XXX_LAST_PORT KSZ8794_PORT3
#define KSZ8XXX_CPU_PORT KSZ8794_PORT4
#define KSZ8XXX_REG_IND_CTRL_0 KSZ8794_REG_IND_CTRL_0
#define KSZ8XXX_REG_IND_CTRL_1 KSZ8794_REG_IND_CTRL_1
#define KSZ8XXX_REG_IND_DATA_8 KSZ8794_REG_IND_DATA_8