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soc/intel_adsp: Unify/dtsify L2 local memory control block

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These registers were hardwired in the platform layer.  Move to
devicetree, via a struct interface that looks like the pre-existing
shim layer.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit is contained in:
Andy Ross 2021-10-20 11:51:55 -07:00 committed by Anas Nashif
parent 73f3374764
commit cb73032a32
9 changed files with 50 additions and 44 deletions
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5
dts/xtensa/intel/intel_cavs18.dtsi
View file

@ -61,6 +61,11 @@
reg = <0x71a00 0x20>;
};
l2lm: l2lm@71d00 {
compatible = "intel,cavs-l2lm";
reg = <0x71d00 0x20>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0x00 0x400>;

5
dts/xtensa/intel/intel_cavs20.dtsi
View file

@ -61,6 +61,11 @@
reg = <0x71a00 0x20>;
};
l2lm: l2lm@71d00 {
compatible = "intel,cavs-l2lm";
reg = <0x71d00 0x20>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0x00 0x400>;

5
dts/xtensa/intel/intel_cavs25.dtsi
View file

@ -61,6 +61,11 @@
reg = <0x71a00 0x20>;
};
l2lm: l2lm@71d00 {
compatible = "intel,cavs-l2lm";
reg = <0x71d00 0x20>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0x00 0x400>;

12
soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h
View file

@ -24,18 +24,6 @@
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define HSPGCTL0 0x71D10
#define HSRMCTL0 0x71D14
#define HSPGISTS0 0x71D18
#define HSPGCTL1 0x71D20
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF

12
soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h
View file

@ -24,18 +24,6 @@
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define HSPGCTL0 0x71D10
#define HSRMCTL0 0x71D14
#define HSPGISTS0 0x71D18
#define HSPGCTL1 0x71D20
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF

12
soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h
View file

@ -24,18 +24,6 @@
/* LP GPDMA Force Dynamic Clock Gating bits, 0--enable */
#define SHIM_CLKCTL_LPGPDMAFDCGB BIT(0)
#define HSPGCTL0 0x71D10
#define HSRMCTL0 0x71D14
#define HSPGISTS0 0x71D18
#define HSPGCTL1 0x71D20
#define HSRMCTL1 0x71D24
#define HSPGISTS1 0x71D28
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58
#define DSP_INIT_LPGPDMA(x) (0x71A60 + (2*x))
#define LPGPDMA_CTLOSEL_FLAG BIT(15)
#define LPGPDMA_CHOSEL_FLAG 0xFF

7
soc/xtensa/intel_adsp/common/bootloader/boot_entry.S
View file

@ -27,6 +27,13 @@
#define SHIM_L2_MECS (SHIM_ADDR + 0xd0)
#define SHIM_L2_PREF_CFG (SHIM_ADDR + 0x508)
#define HSPGCTL0 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x10
#define HSRMCTL0 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x14
#define HSPGISTS0 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x18
#define HSPGCTL1 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x20
#define HSRMCTL1 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x24
#define HSPGISTS1 DT_REG_ADDR(DT_NODELABEL(l2lm)) + 0x28
.type boot_master_core, @function
.begin literal_prefix .boot_entry

16
soc/xtensa/intel_adsp/common/bootloader/boot_loader.c
View file

@ -234,26 +234,26 @@ static int32_t hp_sram_pm_banks(uint32_t banks)
}
/* HSPGCTL, HSRMCTL use reverse logic - 0 means EBB is power gated */
io_reg_write(HSPGCTL0, (~ebb_mask0) & ebb_avail_mask0);
io_reg_write(HSRMCTL0, (~ebb_mask0) & ebb_avail_mask0);
io_reg_write(HSPGCTL1, (~ebb_mask1) & ebb_avail_mask1);
io_reg_write(HSRMCTL1, (~ebb_mask1) & ebb_avail_mask1);
CAVS_L2LM.hspgctl0 = (~ebb_mask0) & ebb_avail_mask0;
CAVS_L2LM.hsrmctl0 = (~ebb_mask0) & ebb_avail_mask0;
CAVS_L2LM.hspgctl1 = (~ebb_mask1) & ebb_avail_mask1;
CAVS_L2LM.hsrmctl1 = (~ebb_mask1) & ebb_avail_mask1;
/* query the power status of first part of HP memory */
/* to check whether it has been powered up. A few */
/* cycles are needed for it to be powered up */
status = io_reg_read(HSPGISTS0);
status = CAVS_L2LM.hspgists0;
while (status != ((~ebb_mask0) & ebb_avail_mask0)) {
idelay(delay_count);
status = io_reg_read(HSPGISTS0);
status = CAVS_L2LM.hspgists0;
}
/* query the power status of second part of HP memory */
/* and do as above code */
status = io_reg_read(HSPGISTS1);
status = CAVS_L2LM.hspgists1;
while (status != ((~ebb_mask1) & ebb_avail_mask1)) {
idelay(delay_count);
status = io_reg_read(HSPGISTS1);
status = CAVS_L2LM.hspgists1;
}
/* add some delay before touch power register */
idelay(delay_count);

20
soc/xtensa/intel_adsp/common/include/cavs-shim.h
View file

@ -65,6 +65,26 @@ struct cavs_shim {
uint32_t _unused9[2];
};
/* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm {
uint32_t l2lmcap;
uint32_t l2lmpat;
uint32_t _unused0[2];
uint32_t hspgctl0;
uint32_t hsrmctl0;
uint32_t hspgists0;
uint32_t _unused1;
uint32_t hspgctl1;
uint32_t hsrmctl1;
uint32_t hspgists1;
uint32_t _unused2[9];
uint32_t lspgctl;
uint32_t lsrmctl;
uint32_t lspgists;
};
#define CAVS_L2LM (*((volatile struct cavs_l2lm *)DT_REG_ADDR(DT_NODELABEL(l2lm))))
/* Host memory window control. Not strictly part of the shim block. */
struct cavs_win {
uint32_t dmwba;