diff --git a/dts/arm/ti/cc1352r7.dtsi b/dts/arm/ti/cc1352r7.dtsi new file mode 100644 index 0000000000..0b098c81c8 --- /dev/null +++ b/dts/arm/ti/cc1352r7.dtsi @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019 Brett Witherspoon + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(144)>; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(704)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* CCFG registers occupy the last 88 bytes of flash */ + ti_ccfg_partition: partition@affa8 { + compatible = "zephyr,memory-region"; + reg = <0xaffa8 88>; + zephyr,memory-region = "FLASH_CCFG"; + }; + }; +}; diff --git a/modules/Kconfig.simplelink b/modules/Kconfig.simplelink index 4506a916bb..cbcf1766d6 100644 --- a/modules/Kconfig.simplelink +++ b/modules/Kconfig.simplelink @@ -29,3 +29,6 @@ config HAS_MSP432P4XXSDK config HAS_CC13X2_CC26X2_SDK bool + +config HAS_CC13X2X7_CC26X2X7_SDK + bool diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt new file mode 100644 index 0000000000..4a2a41c5a5 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Vaishnav Achath +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_sources(ccfg.c) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c) + +zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 new file mode 100644 index 0000000000..fabdeedf2d --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 @@ -0,0 +1,9 @@ +# Texas Instruments SimpleLink CC1352R +# +# Copyright (c) 2022 Vaishnav Achath +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC + default "cc1352r7" + depends on SOC_CC1352R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 new file mode 100644 index 0000000000..2ba4afb876 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 @@ -0,0 +1,8 @@ +# Texas Instruments SimpleLink CC2652R + +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC + default "cc2652r7" + depends on SOC_CC2652R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series new file mode 100644 index 0000000000..ede32e9270 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series @@ -0,0 +1,47 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 + +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC13X2X7_CC26X2X7 + +source "soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc*" + +config SOC_SERIES + default "cc13x2x7_cc26x2x7" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Note that when using the RTC as system clock, this needs to be 32768 +# to reduce truncation errors from accumulating due to conversion to/from +# time, ticks, and HW cycles +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config NUM_IRQS + default 38 + +if IEEE802154 + +config IEEE802154_CC13XX_CC26XX + # required for linking with PowerCC26X2_config in + # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +config IEEE802154_CC13XX_CC26XX_SUB_GHZ + # required for linking with PowerCC26X2_config in + # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +endif # IEEE802154 + +if BT + +config BLE_CC13XX_CC26XX + bool + default y + +endif # BT + +endif # SOC_SERIES_CC13X2X7_CC26X2X7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series new file mode 100644 index 0000000000..a937b6c521 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series @@ -0,0 +1,18 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 + +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2X7_CC26X2X7 + bool "TI SimpleLink Family CC13x2x7/ CC26x2x7" + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select SOC_FAMILY_TISIMPLELINK + select HAS_CC13X2X7_CC26X2X7_SDK + select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT + help + Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc new file mode 100644 index 0000000000..74fae9acaf --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc @@ -0,0 +1,68 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 + +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "TI SimpleLink MCU Selection" + depends on SOC_SERIES_CC13X2X7_CC26X2X7 + +config SOC_CC2652R7 + bool "CC2652R7" + +config SOC_CC1352R7 + bool "CC1352R7" + +config SOC_CC2652P7 + bool "CC2652P7" + +config SOC_CC1352P7 + bool "CC1352P7" + +endchoice + +menu "Customer Configuration (CCFG)" +depends on SOC_SERIES_CC13X2X7_CC26X2X7 + +config CC13X2_CC26X2_BOOST_MODE + bool "Radio boost mode (VDDR_HH)" + help + Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). + +config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS + bool "Board defines custom RFCC26XX hwAttrs structure" + help + The board defines its own RFCC26XX_hwAttrs structure (e.g., for + custom antenna switching callback). + +config CC13X2_CC26X2_BOOTLOADER_ENABLE + bool "ROM bootloader" + help + Enable the serial bootloader which resides in ROM on CC13xx / CC26xx + devices. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + bool "ROM bootloader backdoor" + depends on CC13X2_CC26X2_BOOTLOADER_ENABLE + help + Enable the ROM bootloader backdoor which starts the bootloader if the + associated pin is at the correct logic level on reset. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN + int "ROM bootloader backdoor pin" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 255 + default 255 + help + Set the pin that is level checked if the bootloader backdoor is + enabled. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL + int "ROM bootloader backdoor level" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 1 + default 0 + help + Set the active level of the pin selected for the bootloader backdoor. + +endmenu diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c new file mode 100644 index 0000000000..148a128d62 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef CONFIG_CC13X2_CC26X2_BOOST_MODE +#define CCFG_FORCE_VDDR_HH 1 +#endif + +#ifdef CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 +#else +#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 +#endif /* CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE */ + +#ifdef CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 +#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN +#define SET_CCFG_BL_CONFIG_BL_LEVEL CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL +#else +#define SET_CCFG_BL_CONFIG_BL_ENABLE 0x00 +#endif /* CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE */ + +/* TI recommends setting CCFG values and then including the TI provided ccfg.c */ +#include diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld new file mode 100644 index 0000000000..e0e7edbaa0 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2021, Commonwealth Scientific and Industrial Research + * Organisation (CSIRO) ABN 41 687 119 230. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +GROUP_START(FLASH_CCFG) + +SECTION_PROLOGUE(.ti_ccfg,,) +{ + KEEP(*(_TI_CCFG_SECTION_NAME)) +} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(ti_ccfg_partition))) + +GROUP_END(FLASH_CCFG) diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld new file mode 100644 index 0000000000..f7ba43c42c --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/linker.ld @@ -0,0 +1,8 @@ +/* linker.ld - Linker command/script file + * + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h new file mode 100644 index 0000000000..2c9678801f --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../cc13x2_cc26x2/pinctrl_soc.h" diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c new file mode 100644 index 0000000000..cdb54233dc --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2019 Linaro Limited. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include +#include +#include + +#include +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +const PowerCC26X2_Config PowerCC26X2_config = { +#if defined(CONFIG_IEEE802154_CC13XX_CC26XX) \ + || defined(CONFIG_BLE_CC13XX_CC26XX) \ + || defined(CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ) + .policyInitFxn = NULL, + .policyFxn = NULL, + .calibrateFxn = &PowerCC26XX_calibrate, + .enablePolicy = false, + .calibrateRCOSC_LF = true, + .calibrateRCOSC_HF = true +#else +/* Configuring TI Power module to not use its policy function (we use Zephyr's + * instead), and disable oscillator calibration functionality for now. + */ + .policyInitFxn = NULL, + .policyFxn = NULL, + .calibrateFxn = NULL, + .enablePolicy = false, + .calibrateRCOSC_LF = false, + .calibrateRCOSC_HF = false +#endif +}; + +extern PowerCC26X2_ModuleState PowerCC26X2_module; + +#ifdef CONFIG_PM +/* + * Power state mapping: + * PM_STATE_SUSPEND_TO_IDLE: Idle + * PM_STATE_STANDBY: Standby + * PM_STATE_SUSPEND_TO_RAM | PM_STATE_SUSPEND_TO_DISK: Shutdown + */ + +/* Invoke Low Power/System Off specific Tasks */ +__weak void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + uint32_t modeVIMS; + uint32_t constraints; + + LOG_DBG("SoC entering power state %d", state); + + /* Switch to using PRIMASK instead of BASEPRI register, since + * we are only able to wake up from standby while using PRIMASK. + */ + /* Set PRIMASK */ + CPUcpsid(); + /* Set BASEPRI to 0 */ + irq_unlock(0); + + switch (state) { + case PM_STATE_SUSPEND_TO_IDLE: + /* query the declared constraints */ + constraints = Power_getConstraintMask(); + /* 1. Get the current VIMS mode */ + do { + modeVIMS = VIMSModeGet(VIMS_BASE); + } while (modeVIMS == VIMS_MODE_CHANGING); + + /* 2. Configure flash to remain on in IDLE or not and keep + * VIMS powered on if it is configured as GPRAM + * 3. Always keep cache retention ON in IDLE + * 4. Turn off the CPU power domain + * 5. Ensure any possible outstanding AON writes complete + * 6. Enter IDLE + */ + if ((constraints & (1 << PowerCC26XX_NEED_FLASH_IN_IDLE)) || + (modeVIMS == VIMS_MODE_DISABLED)) { + SysCtrlIdle(VIMS_ON_BUS_ON_MODE); + } else { + SysCtrlIdle(VIMS_ON_CPU_ON_MODE); + } + + /* 7. Make sure MCU and AON are in sync after wakeup */ + SysCtrlAonUpdate(); + break; + + case PM_STATE_STANDBY: + /* go to standby mode */ + Power_sleep(PowerCC26XX_STANDBY); + break; + case PM_STATE_SUSPEND_TO_RAM: + __fallthrough; + case PM_STATE_SUSPEND_TO_DISK: + __fallthrough; + case PM_STATE_SOFT_OFF: + Power_shutdown(0, 0); + break; + default: + LOG_DBG("Unsupported power state %u", state); + break; + } + + LOG_DBG("SoC leaving power state %d", state); +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(state); + ARG_UNUSED(substate_id); + + /* + * System is now in active mode. Reenable interrupts which were disabled + * when OS started idling code. + */ + CPUcpsie(); +} +#endif /* CONFIG_PM */ + +/* Initialize TI Power module */ +static int power_initialize(const struct device *dev) +{ + unsigned int ret; + + ARG_UNUSED(dev); + + ret = irq_lock(); + Power_init(); + irq_unlock(ret); + + return 0; +} + +/* + * Unlatch IO pins after waking up from shutdown + * This needs to be called during POST_KERNEL in order for "Booting Zephyr" + * message to show up + */ +static int unlatch_pins(const struct device *dev) +{ + /* Get the reason for reset. */ + uint32_t rSrc = SysCtrlResetSourceGet(); + + if (rSrc == RSTSRC_WAKEUP_FROM_SHUTDOWN) { + PowerCtrlPadSleepDisable(); + } + + return 0; +} + +/* + * ======== PowerCC26XX_schedulerDisable ======== + */ +void PowerCC26XX_schedulerDisable(void) +{ + /* + * We are leaving this empty because Zephyr's + * scheduler would not get to run with interrupts being disabled + * in the context of Power_sleep() in any case. + */ +} + +/* + * ======== PowerCC26XX_schedulerRestore ======== + */ +void PowerCC26XX_schedulerRestore(void) +{ + /* + * We are leaving this empty because Zephyr's + * scheduler would not get to run with interrupts being disabled + * in the context of Power_sleep() in any case. + */ +} + +SYS_INIT(power_initialize, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +SYS_INIT(unlatch_pins, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY); diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c new file mode 100644 index 0000000000..ac126bdab2 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include + +static int ti_cc13x2_cc26x2_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + /* Performs necessary trim of the device. */ + SetupTrimDevice(); + + return 0; +} + +SYS_INIT(ti_cc13x2_cc26x2_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h new file mode 100644 index 0000000000..c0f578f417 --- /dev/null +++ b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Vaishnav Achath + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "../cc13x2_cc26x2/soc.h" diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c index 0057491c0f..f51291cd95 100644 --- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c +++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c @@ -216,7 +216,7 @@ vth __irq_vector_table _irq_vector_table[] = { }; #endif #endif -#elif defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) +#elif defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) || defined(CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7) /* TI CC13x2/CC26x2 based platforms also employ a Hardware RTC peripheral * to implement the Kernel system timer, instead of the ARM Cortex-M * SysTick. Therefore, a pointer to the timer ISR needs to be added in diff --git a/west.yml b/west.yml index 22f3a67a77..b67a39d8b8 100644 --- a/west.yml +++ b/west.yml @@ -139,7 +139,7 @@ manifest: groups: - hal - name: hal_ti - revision: 5e7d5cd584047699c9fd279923120cb25ba3dda7 + revision: cd40806ee15f4f8f73e1561d3c0e9d99444ea8f0 path: modules/hal/ti groups: - hal