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arch: arm: cleanup workaround for QEMU Cortex-M3

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Qemu is already updated past 2.9 release, so this
workaround for QEMU_CORTEX_M3 is now obsolete and
can be removed.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2019-07-17 09:12:08 +02:00 committed by Andrew Boie
parent f8c37d56fd
commit cbc4d41c32
1 changed files with 0 additions and 8 deletions
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8
arch/arm/include/cortex_m/exc.h
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@ -68,15 +68,7 @@ static ALWAYS_INLINE bool z_IsInIsr(void)
/* If not in thread mode, and if RETTOBASE bit in ICSR is 0,
* then there are preempted active exceptions to execute.
*/
#ifndef CONFIG_BOARD_QEMU_CORTEX_M3
/* The polarity of RETTOBASE is incorrectly flipped in
* all but the very latest master tip of QEMU's NVIC driver,
* see commit "armv7m: Rewrite NVIC to not use any GIC code".
* Until QEMU 2.9 is released, and the SDK is updated to
* include it, skip this check in QEMU.
*/
|| (vector && !(SCB->ICSR & SCB_ICSR_RETTOBASE_Msk))
#endif /* CONFIG_BOARD_QEMU_CORTEX_M3 */
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */