drivers: gpio: Add NXP SC18IM704 GPIO support
Implement external GPIO controller driver with NXP's SC18IM704 device. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This commit is contained in:
Pieter De Gendt
Carles Cufí
parent
9b36e723f4
commit
cd6fe580b0
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@ -74,3 +74,8 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S gpio_rt1718s_port.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NUMICRO gpio_numicro.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_HOGS gpio_hogs.c)
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if(CONFIG_GPIO_SC18IM704)
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zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_library_sources(gpio_sc18im704.c)
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endif()
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@ -181,4 +181,6 @@ source "drivers/gpio/Kconfig.numicro"
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source "drivers/gpio/Kconfig.bd8lb600fs"
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source "drivers/gpio/Kconfig.sc18im704"
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endif # GPIO
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19
drivers/gpio/Kconfig.sc18im704
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19
drivers/gpio/Kconfig.sc18im704
Normal file
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@ -0,0 +1,19 @@
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# Copyright (c) 2023 Basalte bv
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_SC18IM704
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bool "NXP SC18IM704 GPIO controller driver"
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default y
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depends on I2C_SC18IM704
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depends on DT_HAS_NXP_SC18IM704_GPIO_ENABLED
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help
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Enables NXP SC18IM704 GPIO controller driver
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config GPIO_SC18IM704_INIT_PRIORITY
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int "SC18IM704 GPIO init priority"
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default 52
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depends on GPIO_SC18IM704
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help
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SC18IM704 GPIO controller initialization priority.
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Note: Has to be greater than the parent SC18IM704 bridge initialization priority.
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301
drivers/gpio/gpio_sc18im704.c
Normal file
301
drivers/gpio/gpio_sc18im704.c
Normal file
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@ -0,0 +1,301 @@
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/*
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* Copyright (c), 2023 Basalte bv
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_sc18im704_gpio
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#include <errno.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_sc18im, CONFIG_GPIO_LOG_LEVEL);
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#include "i2c/i2c_sc18im704.h"
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#define GPIO_SC18IM_MAX_PINS 8
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/* After reset the GPIO config registers are 0x55 */
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#define GPIO_SC18IM_DEFAULT_CONF 0x55
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#define GPIO_SC18IM_CONF_INPUT 0x01
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#define GPIO_SC18IM_CONF_PUSH_PULL 0x02
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#define GPIO_SC18IM_CONF_OPEN_DRAIN 0x03
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#define GPIO_SC18IM_CONF_MASK 0x03
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struct gpio_sc18im_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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const struct device *bridge;
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};
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struct gpio_sc18im_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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uint8_t conf1;
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uint8_t conf2;
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uint8_t output_state;
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};
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static int gpio_sc18im_port_set_raw(const struct device *port,
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uint8_t mask, uint8_t value, uint8_t toggle)
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{
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const struct gpio_sc18im_config *cfg = port->config;
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struct gpio_sc18im_data *data = port->data;
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uint8_t buf[] = {
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SC18IM704_CMD_WRITE_GPIO,
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data->output_state,
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SC18IM704_CMD_STOP,
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};
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int ret;
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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buf[1] &= ~mask;
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buf[1] |= (value & mask);
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buf[1] ^= toggle;
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ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), NULL, 0);
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if (ret < 0) {
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LOG_ERR("Failed to write GPIO state (%d)", ret);
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return ret;
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}
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data->output_state = buf[1];
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return 0;
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}
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static int gpio_sc18im_pin_configure(const struct device *port, gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_sc18im_config *cfg = port->config;
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struct gpio_sc18im_data *data = port->data;
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uint8_t pin_conf;
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int ret;
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uint8_t buf[] = {
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SC18IM704_CMD_WRITE_REG,
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0x00,
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0x00,
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SC18IM704_CMD_STOP,
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};
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if (pin >= GPIO_SC18IM_MAX_PINS) {
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return -EINVAL;
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}
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if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) {
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return -ENOTSUP;
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}
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if (flags & GPIO_INPUT) {
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pin_conf = GPIO_SC18IM_CONF_INPUT;
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} else if (flags & GPIO_OUTPUT) {
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if (flags & GPIO_SINGLE_ENDED) {
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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pin_conf = GPIO_SC18IM_CONF_OPEN_DRAIN;
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} else {
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/* Open-drain is the only supported single-ended mode */
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return -ENOTSUP;
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}
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} else {
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/* Default to push/pull */
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pin_conf = GPIO_SC18IM_CONF_PUSH_PULL;
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}
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} else {
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/* Neither input nor output mode is selected */
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return -ENOTSUP;
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}
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ret = sc18im704_claim(cfg->bridge);
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if (ret < 0) {
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LOG_ERR("Failed to claim bridge (%d)", ret);
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return ret;
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}
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if (pin < 4) {
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/* Shift the config to the pin offset */
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data->conf1 &= ~(GPIO_SC18IM_CONF_MASK << (pin * 2));
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data->conf1 |= pin_conf << (pin * 2);
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buf[1] = SC18IM704_REG_GPIO_CONF1;
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buf[2] = data->conf1;
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} else {
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/* Shift the config to the pin offset */
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data->conf2 &= ~(GPIO_SC18IM_CONF_MASK << ((pin - 4) * 2));
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data->conf2 |= pin_conf << ((pin - 4) * 2);
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buf[1] = SC18IM704_REG_GPIO_CONF2;
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buf[2] = data->conf2;
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}
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ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), NULL, 0);
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if (ret < 0) {
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LOG_ERR("Failed to configure GPIO (%d)", ret);
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}
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if (ret == 0 && flags & GPIO_OUTPUT) {
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_sc18im_port_set_raw(port, BIT(pin), BIT(pin), 0);
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}
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if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_sc18im_port_set_raw(port, BIT(pin), 0, 0);
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}
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}
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sc18im704_release(cfg->bridge);
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return ret;
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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static int gpio_sc18im_pin_get_config(const struct device *port, gpio_pin_t pin,
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gpio_flags_t *flags)
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{
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struct gpio_sc18im_data *data = port->data;
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uint8_t conf;
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if (pin >= GPIO_SC18IM_MAX_PINS) {
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return -EINVAL;
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}
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if (pin < 4) {
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conf = (data->conf1 >> (2 * pin)) & GPIO_SC18IM_CONF_MASK;
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} else {
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conf = (data->conf2 >> (2 * (pin - 4))) & GPIO_SC18IM_CONF_MASK;
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}
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switch (conf) {
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case GPIO_SC18IM_CONF_PUSH_PULL:
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*flags = GPIO_OUTPUT | GPIO_PUSH_PULL;
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break;
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case GPIO_SC18IM_CONF_OPEN_DRAIN:
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*flags = GPIO_OUTPUT | GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN;
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break;
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case GPIO_SC18IM_CONF_INPUT:
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default:
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*flags = GPIO_INPUT;
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break;
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}
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return 0;
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}
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#endif
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static int gpio_sc18im_port_get_raw(const struct device *port, gpio_port_value_t *value)
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{
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const struct gpio_sc18im_config *cfg = port->config;
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uint8_t buf[] = {
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SC18IM704_CMD_READ_GPIO,
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SC18IM704_CMD_STOP,
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};
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uint8_t data;
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int ret;
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if (k_is_in_isr()) {
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return -EWOULDBLOCK;
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}
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ret = sc18im704_transfer(cfg->bridge, buf, sizeof(buf), &data, 1);
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if (ret < 0) {
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LOG_ERR("Failed to read GPIO state (%d)", ret);
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return ret;
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}
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*value = data;
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return 0;
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}
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static int gpio_sc18im_port_set_masked_raw(const struct device *port,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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return gpio_sc18im_port_set_raw(port, (uint8_t)mask, (uint8_t)value, 0);
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}
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static int gpio_sc18im_port_set_bits_raw(const struct device *port, gpio_port_pins_t pins)
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{
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return gpio_sc18im_port_set_raw(port, (uint8_t)pins, (uint8_t)pins, 0);
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}
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static int gpio_sc18im_port_clear_bits_raw(const struct device *port, gpio_port_pins_t pins)
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{
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return gpio_sc18im_port_set_raw(port, (uint8_t)pins, 0, 0);
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}
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static int gpio_sc18im_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
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{
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return gpio_sc18im_port_set_raw(port, 0, 0, (uint8_t)pins);
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}
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static int gpio_sc18im_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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ARG_UNUSED(port);
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ARG_UNUSED(pin);
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ARG_UNUSED(mode);
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ARG_UNUSED(trig);
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return -ENOTSUP;
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}
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static int gpio_sc18im_init(const struct device *dev)
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{
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const struct gpio_sc18im_config *cfg = dev->config;
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if (!device_is_ready(cfg->bridge)) {
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LOG_ERR("Parent device not ready");
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return -ENODEV;
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_sc18im_driver_api = {
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.pin_configure = gpio_sc18im_pin_configure,
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#ifdef CONFIG_GPIO_GET_CONFIG
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.pin_get_config = gpio_sc18im_pin_get_config,
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#endif
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.port_get_raw = gpio_sc18im_port_get_raw,
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.port_set_masked_raw = gpio_sc18im_port_set_masked_raw,
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.port_set_bits_raw = gpio_sc18im_port_set_bits_raw,
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.port_clear_bits_raw = gpio_sc18im_port_clear_bits_raw,
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.port_toggle_bits = gpio_sc18im_port_toggle_bits,
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.pin_interrupt_configure = gpio_sc18im_pin_interrupt_configure,
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};
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#define CHECK_COMPAT(node) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(node, nxp_sc18im704_i2c), (DEVICE_DT_GET(node)), ())
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#define GPIO_SC18IM704_I2C_SIBLING(n) \
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DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_PARENT(n), CHECK_COMPAT)
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#define GPIO_SC18IM704_DEFINE(n) \
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static const struct gpio_sc18im_config gpio_sc18im_config_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.bridge = GPIO_SC18IM704_I2C_SIBLING(n), \
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}; \
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static struct gpio_sc18im_data gpio_sc18im_data_##n = { \
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.conf1 = GPIO_SC18IM_DEFAULT_CONF, \
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.conf2 = GPIO_SC18IM_DEFAULT_CONF, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, gpio_sc18im_init, NULL, \
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&gpio_sc18im_data_##n, &gpio_sc18im_config_##n, \
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POST_KERNEL, CONFIG_GPIO_SC18IM704_INIT_PRIORITY, \
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&gpio_sc18im_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_SC18IM704_DEFINE);
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23
dts/bindings/gpio/nxp,sc18im704-gpio.yaml
Normal file
23
dts/bindings/gpio/nxp,sc18im704-gpio.yaml
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@ -0,0 +1,23 @@
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# Copyright (c), 2023 Basalte bv
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# SPDX-License-Identifier: Apache-2.0
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description: GPIO controller part for the SC18IM704 bridge
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compatible: "nxp,sc18im704-gpio"
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include: gpio-controller.yaml
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properties:
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"#gpio-cells":
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required: true
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const: 2
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ngpios:
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required: true
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const: 8
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gpio-cells:
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- pin
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- flags
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on-bus: nxp,sc18im704
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