flash: add a driver for the internal flash on the SAM0 series.
The SAM0 has a 64 byte page (the programing unit) with 4 pages to a row (the erase unit). This driver implements a read/modify/write to emulate the byte level writes used by NFFS. Signed-off-by: Michael Hope <mlhx@google.com>
This commit is contained in:
Michael Hope
Anas Nashif
parent
5aa0d88b58
commit
cd92dd139b
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@ -4,6 +4,7 @@ zephyr_sources_ifdef(CONFIG_SOC_FLASH_NRF5 soc_flash_nrf5.c)
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zephyr_sources_ifdef(CONFIG_SOC_FLASH_MCUX soc_flash_mcux.c)
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zephyr_sources_ifdef(CONFIG_FLASH_PAGE_LAYOUT flash_page_layout.c)
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zephyr_sources_ifdef(CONFIG_USERSPACE flash_handlers.c)
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zephyr_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c)
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if(CONFIG_SOC_SERIES_STM32F0X)
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zephyr_sources_ifdef(CONFIG_SOC_FLASH_STM32
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@ -164,3 +164,5 @@ config SOC_FLASH_MCUX_DEV_NAME
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Specify the device name for the flash driver.
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source "drivers/flash/Kconfig.stm32"
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source "drivers/flash/Kconfig.sam0"
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32
drivers/flash/Kconfig.sam0
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32
drivers/flash/Kconfig.sam0
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@ -0,0 +1,32 @@
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# Kconfig - Atmel SAM0 flash driver config
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#
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# Copyright (c) 2018 Google LLC.
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# SPDX-License-Identifier: Apache-2.0
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if FLASH && SOC_FAMILY_SAM0
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menuconfig SOC_FLASH_SAM0
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bool
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prompt "Atmel SAM0 flash driver"
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default n
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select FLASH_HAS_PAGE_LAYOUT
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help
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Enable the Atmel SAM0 series internal flash driver.
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config SOC_FLASH_SAM0_DEV_NAME
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string "Flash device name"
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depends on SOC_FLASH_SAM0
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default "FLASH_0"
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help
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Specify the device name for the flash driver.
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config SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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bool
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prompt "Emulate byte-sized pages"
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depends on SOC_FLASH_SAM0
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default n
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help
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Emulate a device with byte-sized pages by doing a
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read/modify/erase/write. Needed for NFFS.
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endif
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376
drivers/flash/flash_sam0.c
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376
drivers/flash/flash_sam0.c
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@ -0,0 +1,376 @@
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/*
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* Copyright (c) 2018 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SYS_LOG_DOMAIN "flash"
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#include <logging/sys_log.h>
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#include <device.h>
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#include <flash.h>
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#include <init.h>
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#include <kernel.h>
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#include <soc.h>
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#include <string.h>
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/*
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* Zephyr and the SAM0 series use different and conflicting names for
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* the erasable units and programmable units:
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*
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* The erase unit is a row, which is a 'page' in Zephyr terms.
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* The program unit is a page, which is a 'write_block' in Zephyr.
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*
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* This file uses the SAM0 names internally and the Zephyr names in
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* any error messages.
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*/
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/*
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* Number of lock regions. The number is fixed and the region size
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* grows with the flash size.
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*/
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#define LOCK_REGIONS 16
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#define LOCK_REGION_SIZE (FLASH_SIZE / LOCK_REGIONS)
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#define PAGES_PER_ROW 4
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#define ROW_SIZE (FLASH_PAGE_SIZE * PAGES_PER_ROW)
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#define FLASH_MEM(_a) ((u32_t *)((u8_t *)((_a) + CONFIG_FLASH_BASE_ADDRESS)))
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struct flash_sam0_data {
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#if CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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u8_t buf[ROW_SIZE];
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off_t offset;
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#endif
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struct k_sem sem;
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};
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static const struct flash_pages_layout flash_sam0_pages_layout = {
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.pages_count = CONFIG_FLASH_SIZE * 1024 / ROW_SIZE,
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.pages_size = ROW_SIZE,
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};
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static inline void flash_sam0_sem_take(struct device *dev)
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{
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struct flash_sam0_data *ctx = dev->driver_data;
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k_sem_take(&ctx->sem, K_FOREVER);
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}
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static inline void flash_sam0_sem_give(struct device *dev)
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{
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struct flash_sam0_data *ctx = dev->driver_data;
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k_sem_give(&ctx->sem);
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}
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static int flash_sam0_valid_range(off_t offset, size_t len)
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{
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if (offset < 0) {
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SYS_LOG_WRN("%x: before start of flash", offset);
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return -EINVAL;
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}
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if ((offset + len) > CONFIG_FLASH_SIZE * 1024) {
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SYS_LOG_WRN("%x: ends past the end of flash", offset);
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return -EINVAL;
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}
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return 0;
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}
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static void flash_sam0_wait_ready(void)
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{
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while (NVMCTRL->INTFLAG.bit.READY == 0) {
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}
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}
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static int flash_sam0_check_status(off_t offset)
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{
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NVMCTRL_STATUS_Type status;
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flash_sam0_wait_ready();
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status = NVMCTRL->STATUS;
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/* Clear any flags */
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NVMCTRL->STATUS = status;
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if (status.bit.PROGE) {
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SYS_LOG_ERR("programming error at 0x%x", offset);
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return -EIO;
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} else if (status.bit.LOCKE) {
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SYS_LOG_ERR("lock error at 0x%x", offset);
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return -EROFS;
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} else if (status.bit.NVME) {
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SYS_LOG_ERR("NVM error at 0x%x", offset);
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return -EIO;
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}
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return 0;
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}
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static int flash_sam0_write_page(struct device *dev, off_t offset,
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const void *data)
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{
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const u32_t *src = data;
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const u32_t *end = src + FLASH_PAGE_SIZE / sizeof(*src);
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u32_t *dst = FLASH_MEM(offset);
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int err;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY;
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flash_sam0_wait_ready();
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/* Ensure writes happen 32 bits at a time. */
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for (; src != end; src++, dst++) {
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*dst = *src;
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}
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY;
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err = flash_sam0_check_status(offset);
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if (err != 0) {
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return err;
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}
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if (memcmp(data, FLASH_MEM(offset), FLASH_PAGE_SIZE) != 0) {
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SYS_LOG_ERR("verify error at offset 0x%x", offset);
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return -EIO;
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}
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return 0;
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}
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static int flash_sam0_erase_row(struct device *dev, off_t offset)
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{
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*FLASH_MEM(offset) = 0;
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY;
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return flash_sam0_check_status(offset);
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}
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#if CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
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static int flash_sam0_commit(struct device *dev)
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{
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struct flash_sam0_data *ctx = dev->driver_data;
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int err;
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int page;
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off_t offset = ctx->offset;
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ctx->offset = 0;
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if (offset == 0) {
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return 0;
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}
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err = flash_sam0_erase_row(dev, offset);
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if (err != 0) {
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return err;
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}
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for (page = 0; page < PAGES_PER_ROW; page++) {
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err = flash_sam0_write_page(
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dev, offset + page * FLASH_PAGE_SIZE,
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&ctx->buf[page * FLASH_PAGE_SIZE]);
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if (err != 0) {
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return err;
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}
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}
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return 0;
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}
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static int flash_sam0_write(struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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struct flash_sam0_data *ctx = dev->driver_data;
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const u8_t *pdata = data;
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off_t addr;
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int err;
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SYS_LOG_DBG("%x: len %u", offset, len);
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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flash_sam0_sem_take(dev);
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for (addr = offset; addr < offset + len; addr++) {
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off_t base = addr & ~(ROW_SIZE - 1);
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if (base != ctx->offset) {
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/* Started a new row. Flush any pending ones. */
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flash_sam0_commit(dev);
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memcpy(ctx->buf, (void *)base, sizeof(ctx->buf));
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ctx->offset = base;
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}
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ctx->buf[addr % ROW_SIZE] = *pdata++;
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}
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flash_sam0_commit(dev);
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flash_sam0_sem_give(dev);
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return 0;
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}
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#else /* CONFIG_SOC_FLASH_SAM0_EMULATE_BYTE_PAGES */
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static int flash_sam0_write(struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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const u8_t *pdata = data;
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int err;
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size_t idx;
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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if ((offset % FLASH_PAGE_SIZE) != 0) {
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SYS_LOG_WRN("%x: not on a write block boundrary", offset);
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return -EINVAL;
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}
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if ((len % FLASH_PAGE_SIZE) != 0) {
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SYS_LOG_WRN("%x: not a integer number of write blocks", len);
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return -EINVAL;
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}
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flash_sam0_sem_take(dev);
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for (idx = 0; idx < len; idx += FLASH_PAGE_SIZE) {
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err = flash_sam0_write_page(dev, offset + idx, &pdata[idx]);
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if (err != 0) {
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goto done;
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}
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}
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done:
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flash_sam0_sem_give(dev);
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return err;
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}
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#endif
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static int flash_sam0_read(struct device *dev, off_t offset, void *data,
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size_t len)
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{
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int err;
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err = flash_sam0_valid_range(offset, len);
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if (err != 0) {
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return err;
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}
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memcpy(data, (u8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, len);
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return 0;
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}
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static int flash_sam0_erase(struct device *dev, off_t offset, size_t size)
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{
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int err;
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err = flash_sam0_valid_range(offset, ROW_SIZE);
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if (err != 0) {
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return err;
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}
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if ((offset % ROW_SIZE) != 0) {
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SYS_LOG_WRN("%x: not on a page boundrary", offset);
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return -EINVAL;
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}
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if ((size % ROW_SIZE) != 0) {
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SYS_LOG_WRN("%x: not a integer number of pages", size);
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return -EINVAL;
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}
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flash_sam0_sem_take(dev);
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for (size_t addr = offset; addr < offset + size; addr += ROW_SIZE) {
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err = flash_sam0_erase_row(dev, addr);
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if (err != 0) {
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goto done;
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}
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}
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done:
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flash_sam0_sem_give(dev);
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return err;
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}
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static int flash_sam0_write_protection(struct device *dev, bool enable)
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{
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off_t offset;
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int err;
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flash_sam0_sem_take(dev);
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for (offset = 0; offset < CONFIG_FLASH_SIZE * 1024;
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offset += LOCK_REGION_SIZE) {
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*FLASH_MEM(offset) = 0;
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if (enable) {
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_LR |
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NVMCTRL_CTRLA_CMDEX_KEY;
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} else {
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NVMCTRL->CTRLA.reg = NVMCTRL_CTRLA_CMD_UR |
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NVMCTRL_CTRLA_CMDEX_KEY;
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}
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err = flash_sam0_check_status(offset);
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if (err != 0) {
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goto done;
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}
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}
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done:
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flash_sam0_sem_give(dev);
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return err;
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}
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void flash_sam0_page_layout(struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &flash_sam0_pages_layout;
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*layout_size = 1;
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}
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static int flash_sam0_init(struct device *dev)
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{
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struct flash_sam0_data *ctx = dev->driver_data;
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k_sem_init(&ctx->sem, 1, 1);
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/* Ensure the clock is on. */
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PM->APBBMASK.bit.NVMCTRL_ = 1;
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/* Require an explicit write command */
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NVMCTRL->CTRLB.bit.MANW = 1;
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return flash_sam0_write_protection(dev, false);
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}
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static const struct flash_driver_api flash_sam0_api = {
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.write_protection = flash_sam0_write_protection,
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.erase = flash_sam0_erase,
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.write = flash_sam0_write,
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.read = flash_sam0_read,
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#ifdef CONFIG_FLASH_PAGE_LAYOUT
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.page_layout = flash_sam0_page_layout,
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#endif
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.write_block_size = FLASH_PAGE_SIZE,
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};
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static struct flash_sam0_data flash_sam0_data_0;
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DEVICE_AND_API_INIT(flash_sam0, CONFIG_SOC_FLASH_SAM0_DEV_NAME,
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flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api);
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@ -19,7 +19,9 @@
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};
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 0x40000>;
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write-block-size = <64>;
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};
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sram0: memory@20000000 {
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|
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Loading…
Reference in a new issue