drivers: spi: Enable dma transfer for SPI on stm32
Enable dma operations with or w/o a dmamux on STM32 for SPI periph/memory operations. Use the pi dma client with dma macros Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu
Kumar Gala
parent
bea0a95578
commit
ce093dc35e
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@ -17,10 +17,18 @@ config SPI_STM32_INTERRUPT
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help
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Enable Interrupt support for the SPI Driver of STM32 family.
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config SPI_STM32_DMA
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bool "STM32 MCU SPI DMA Support"
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select DMA
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help
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Enable the SPI DMA mode for SPI instances
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that enable dma channels in their device tree node.
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config SPI_STM32_USE_HW_SS
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bool "STM32 Hardware Slave Select support"
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default y
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help
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Use Slave Select pin instead of software Slave Select.
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endif # SPI_STM32
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@ -16,7 +16,10 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
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#include <errno.h>
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#include <drivers/spi.h>
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#include <toolchain.h>
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#ifdef CONFIG_SPI_STM32_DMA
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#include <dt-bindings/dma/stm32_dma.h>
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#include <drivers/dma.h>
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#endif
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/clock_control.h>
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@ -48,6 +51,166 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
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#endif
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#endif /* CONFIG_SOC_SERIES_STM32MP1X */
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#ifdef CONFIG_SPI_STM32_DMA
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/* dummy value used for transferring NOP when tx buf is null */
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u32_t nop_tx;
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/* This function is executed in the interrupt context */
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static void dma_callback(void *arg, u32_t channel, int status)
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{
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/* TODO: callback function where arg directly holds the client data */
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}
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static int spi_stm32_dma_tx_load(struct device *dev, const u8_t *buf,
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size_t len)
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{
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const struct spi_stm32_config *cfg = DEV_CFG(dev);
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struct spi_stm32_data *data = DEV_DATA(dev);
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struct dma_block_config blk_cfg;
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int ret;
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/* remember active TX DMA channel (used in callback) */
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struct stream *stream = &data->dma_tx;
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/* prepare the block for this TX DMA channel */
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memset(&blk_cfg, 0, sizeof(blk_cfg));
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blk_cfg.block_size = len;
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/* tx direction has memory as source and periph as dest. */
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if (buf == NULL) {
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nop_tx = 0;
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/* if tx buff is null, then sends NOP on the line. */
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blk_cfg.source_address = (u32_t)&nop_tx;
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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} else {
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blk_cfg.source_address = (u32_t)buf;
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if (data->dma_tx.src_addr_increment) {
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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}
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blk_cfg.dest_address = (u32_t)LL_SPI_DMA_GetRegAddr(cfg->spi);
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/* fifo mode NOT USED there */
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if (data->dma_tx.dst_addr_increment) {
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blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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/* give the fifo mode from the DT */
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blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold;
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/* direction is given by the DT */
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stream->dma_cfg.head_block = &blk_cfg;
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/* give the client data as arg, as the callback comes from the dma */
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stream->dma_cfg.callback_arg = data;
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/* pass our client origin to the dma: data->dma_tx.dma_channel */
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ret = dma_config(data->dev_dma_tx, data->dma_tx.channel,
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&stream->dma_cfg);
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/* the channel is the actual stream from 0 */
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if (ret != 0) {
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return ret;
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}
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/* starting this dma transfer */
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data->dma_tx.transfer_complete = false;
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/* gives the request ID to the dma mux */
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return dma_start(data->dev_dma_tx, data->dma_tx.channel);
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}
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static int spi_stm32_dma_rx_load(struct device *dev, u8_t *buf, size_t len)
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{
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const struct spi_stm32_config *cfg = DEV_CFG(dev);
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struct spi_stm32_data *data = DEV_DATA(dev);
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struct dma_block_config blk_cfg;
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int ret;
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/* retrieve active RX DMA channel (used in callback) */
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struct stream *stream = &data->dma_rx;
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/* prepare the block for this RX DMA channel */
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memset(&blk_cfg, 0, sizeof(blk_cfg));
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blk_cfg.block_size = len;
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/* rx direction has periph as source and mem as dest. */
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blk_cfg.dest_address = (buf != NULL) ? (u32_t)buf : (u32_t)NULL;
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blk_cfg.source_address = (u32_t)LL_SPI_DMA_GetRegAddr(cfg->spi);
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if (data->dma_rx.src_addr_increment) {
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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if (data->dma_rx.dst_addr_increment) {
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blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
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} else {
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blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
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}
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/* give the fifo mode from the DT */
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blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold;
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/* direction is given by the DT */
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stream->dma_cfg.head_block = &blk_cfg;
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stream->dma_cfg.callback_arg = data;
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/* pass our client origin to the dma: data->dma_rx.channel */
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ret = dma_config(data->dev_dma_rx, data->dma_rx.channel,
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&stream->dma_cfg);
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/* the channel is the actual stream from 0 */
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if (ret != 0) {
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return ret;
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}
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/* starting this dma transfer */
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data->dma_rx.transfer_complete = false;
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/* gives the request ID to the dma mux */
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return dma_start(data->dev_dma_rx, data->dma_rx.channel);
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}
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static int spi_dma_move_buffers(struct device *dev)
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{
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struct spi_stm32_data *data = DEV_DATA(dev);
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int ret;
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/* the length to transmit depends on the source data size (1,2 4) */
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data->dma_segment_len = data->ctx.tx_len
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/ data->dma_tx.dma_cfg.source_data_size;
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/* Load receive first, so it can accept transmit data */
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if (data->ctx.rx_len) {
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ret = spi_stm32_dma_rx_load(dev, data->ctx.rx_buf,
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data->dma_segment_len);
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} else {
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ret = spi_stm32_dma_rx_load(dev, NULL, data->dma_segment_len);
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}
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if (ret != 0) {
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return ret;
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}
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if (data->ctx.tx_len) {
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ret = spi_stm32_dma_tx_load(dev, data->ctx.tx_buf,
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data->dma_segment_len);
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} else {
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ret = spi_stm32_dma_tx_load(dev, NULL, data->dma_segment_len);
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}
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return ret;
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}
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static bool spi_stm32_dma_transfer_ongoing(struct spi_stm32_data *data)
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{
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return ((data->dma_tx.transfer_complete != true)
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&& (data->dma_rx.transfer_complete != true));
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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/* Value to shift out when no application data needs transmitting. */
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#define SPI_STM32_TX_NOP 0x00
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@ -348,6 +511,16 @@ static int spi_stm32_configure(struct device *dev,
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ll_func_set_fifo_threshold_8bit(spi);
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#endif
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#ifdef CONFIG_SPI_STM32_DMA
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/* with LL_SPI_FULL_DUPLEX mode, both tx and Rx DMA are on */
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if (data->dev_dma_tx) {
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LL_SPI_EnableDMAReq_TX(spi);
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}
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if (data->dev_dma_rx) {
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LL_SPI_EnableDMAReq_RX(spi);
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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#ifndef CONFIG_SOC_SERIES_STM32F1X
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LL_SPI_SetStandard(spi, LL_SPI_PROTOCOL_MOTOROLA);
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#endif
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@ -451,11 +624,72 @@ static int transceive(struct device *dev,
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return ret;
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}
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#ifdef CONFIG_SPI_STM32_DMA
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static int transceive_dma(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs,
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bool asynchronous, struct k_poll_signal *signal)
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{
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const struct spi_stm32_config *cfg = DEV_CFG(dev);
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struct spi_stm32_data *data = DEV_DATA(dev);
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SPI_TypeDef *spi = cfg->spi;
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int ret;
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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if (asynchronous) {
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return -ENOTSUP;
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}
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spi_context_lock(&data->ctx, asynchronous, signal);
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data->dma_tx.transfer_complete = false;
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data->dma_rx.transfer_complete = false;
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ret = spi_stm32_configure(dev, config);
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if (ret) {
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return ret;
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}
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/* Set buffers info */
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = spi_dma_move_buffers(dev);
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if (ret) {
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return ret;
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}
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LL_SPI_Enable(spi);
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do {
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} while (spi_stm32_dma_transfer_ongoing(data));
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/* This is turned off in spi_stm32_complete(). */
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spi_context_cs_control(&data->ctx, true);
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spi_context_release(&data->ctx, ret);
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return ret;
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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static int spi_stm32_transceive(struct device *dev,
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const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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#ifdef CONFIG_SPI_STM32_DMA
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struct spi_stm32_data *data = DEV_DATA(dev);
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if ((data->dma_tx.dma_name != NULL)
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&& (data->dma_rx.dma_name != NULL)) {
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return transceive_dma(dev, config, tx_bufs, rx_bufs,
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false, NULL);
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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return transceive(dev, config, tx_bufs, rx_bufs, false, NULL);
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}
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@ -495,6 +729,24 @@ static int spi_stm32_init(struct device *dev)
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cfg->irq_config(dev);
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#endif
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#ifdef CONFIG_SPI_STM32_DMA
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if (data->dma_tx.dma_name != NULL) {
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/* Get the binding to the DMA device */
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data->dev_dma_tx = device_get_binding(data->dma_tx.dma_name);
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if (!data->dev_dma_tx) {
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LOG_ERR("%s device not found", data->dma_tx.dma_name);
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return -ENODEV;
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}
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}
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if (data->dma_rx.dma_name != NULL) {
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data->dev_dma_rx = device_get_binding(data->dma_rx.dma_name);
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if (!data->dev_dma_rx) {
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LOG_ERR("%s device not found", data->dma_rx.dma_name);
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return -ENODEV;
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}
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}
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#endif /* CONFIG_SPI_STM32_DMA */
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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@ -519,14 +771,49 @@ static void spi_stm32_irq_config_func_##id(struct device *dev) \
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#define STM32_SPI_IRQ_HANDLER(id)
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#endif
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#define DMA_CHANNEL_CONFIG(id, dir) \
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DT_INST_DMAS_CELL_BY_NAME(id, dir, channel_config)
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#define DMA_FEATURES(id, dir) \
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DT_INST_DMAS_CELL_BY_NAME(id, dir, features)
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#define SPI_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \
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.dma_##dir = { \
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.dma_name = DT_INST_DMAS_LABEL_BY_NAME(index, dir), \
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.channel = \
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DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
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.dma_cfg = { \
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.dma_slot = \
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DT_INST_DMAS_CELL_BY_NAME(index, dir, slot), \
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.channel_direction = STM32_DMA_CONFIG_DIRECTION( \
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DMA_CHANNEL_CONFIG(index, dir)),\
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.source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(\
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DMA_CHANNEL_CONFIG(index, dir)),\
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.dest_data_size = STM32_DMA_CONFIG_##dest_dev##_DATA_SIZE(\
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DMA_CHANNEL_CONFIG(index, dir)),\
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.source_burst_length = 1, /* SINGLE transfer */ \
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.dest_burst_length = 1, /* SINGLE transfer */ \
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.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
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DMA_CHANNEL_CONFIG(index, dir)),\
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.dma_callback = dma_callback, \
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.block_count = 2, \
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}, \
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.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
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DMA_CHANNEL_CONFIG(index, dir)),\
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.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
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DMA_CHANNEL_CONFIG(index, dir)),\
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.transfer_complete = false, \
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.fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \
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DMA_FEATURES(index, dir)) \
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}
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#define STM32_SPI_INIT(id) \
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STM32_SPI_IRQ_HANDLER_DECL(id); \
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\
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static const struct spi_stm32_config spi_stm32_cfg_##id = { \
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.spi = (SPI_TypeDef *) DT_INST_REG_ADDR(id),\
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.pclken = { \
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.enr = DT_INST_CLOCKS_CELL(id, bits), \
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.bus = DT_INST_CLOCKS_CELL(id, bus) \
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.enr = DT_INST_CLOCKS_CELL(id, bits), \
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.bus = DT_INST_CLOCKS_CELL(id, bus) \
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}, \
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STM32_SPI_IRQ_HANDLER_FUNC(id) \
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}; \
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@ -534,6 +821,10 @@ static const struct spi_stm32_config spi_stm32_cfg_##id = { \
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static struct spi_stm32_data spi_stm32_dev_data_##id = { \
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SPI_CONTEXT_INIT_LOCK(spi_stm32_dev_data_##id, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_stm32_dev_data_##id, ctx), \
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UTIL_AND(DT_INST_DMAS_HAS_NAME(id, rx), \
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SPI_DMA_CHANNEL_INIT(id, rx, RX, PERIPHERAL, MEMORY)), \
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UTIL_AND(DT_INST_DMAS_HAS_NAME(id, tx), \
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SPI_DMA_CHANNEL_INIT(id, tx, TX, MEMORY, PERIPHERAL)), \
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}; \
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\
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DEVICE_AND_API_INIT(spi_stm32_##id, DT_INST_LABEL(id), \
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@ -19,8 +19,28 @@ struct spi_stm32_config {
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#endif
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};
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#ifdef CONFIG_SPI_STM32_DMA
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struct stream {
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const char *dma_name;
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u32_t channel; /* stores the channel for dma or mux */
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struct dma_config dma_cfg;
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u8_t priority;
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bool src_addr_increment;
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bool dst_addr_increment;
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bool transfer_complete;
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int fifo_threshold;
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};
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#endif
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struct spi_stm32_data {
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struct spi_context ctx;
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#ifdef CONFIG_SPI_STM32_DMA
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struct device *dev_dma_tx;
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struct device *dev_dma_rx;
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struct stream dma_rx;
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struct stream dma_tx;
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size_t dma_segment_len;
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#endif
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};
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static inline u32_t ll_func_tx_is_empty(SPI_TypeDef *spi)
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