soc: arm: framework for common fixed MPU region configuration

We move the configuration of the fixed MPU regions for ARM
Cortex-M SoCs in a common place under soc/arm/common/cortex-m,
instead of having this configuration present in each ARM SoC or
SoC Series definition. The rationale behind this is that for all
SoCs the fixed MPU regions configured at SoC definition are only
used for enforcing default Flash and SRAM access policies, and
currently, this is common to all ARM SoCs with MPU support.

We also simplify the Flash and SRAM MPU region definition,
aiming at using a single MPU region index to program each
of them.

We still support the possibility for ARM SoCs to opt-out and,
instead, define their own custom fixed MPU regions at SoC
definition. We do it using a Kconfig option, introduced
explicitly for this purpose.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>

soc/arm/CMakeLists.txt

@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
+add_subdirectory_ifdef(CONFIG_CPU_CORTEX_M common/cortex_m)
+
 if(SOC_FAMILY)
   add_subdirectory(${SOC_FAMILY})
 else()

soc/arm/Kconfig

@@ -17,6 +17,15 @@ config CPU_HAS_NXP_MPU
 	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
 	  in NXP flavor.
 
+config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	bool "Custom fixed SoC MPU region definition"
+	help
+	  If enabled, this option signifies that the SoC will
+	  define and configure its own fixed MPU regions in the
+	  SoC definition. These fixed MPU regions are currently
+	  used to set Flash and SRAM default access policies and
+	  they are programmed at boot time.
+
 config CPU_HAS_ARM_SAU
 	bool
 	select CPU_HAS_TEE

soc/arm/common/cortex_m/CMakeLists.txt

@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_ARM_MPU AND NOT CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS)
+
+  zephyr_library()
+
+  zephyr_library_sources_ifdef(CONFIG_CPU_HAS_ARM_MPU
+    arm_mpu_regions.c
+    )
+  zephyr_library_sources_ifdef(CONFIG_CPU_HAS_NXP_MPU
+    nxp_mpu_regions.c
+    )
+endif()

soc/arm/common/cortex_m/arm_mpu_mem_cfg.h

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ARM_CORTEX_M_MPU_MEM_CFG_H_
+#define _ARM_CORTEX_M_MPU_MEM_CFG_H_
+
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+#if !defined(CONFIG_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV8_M_MAINLINE)
+
+/* Flash Region Definitions */
+#if CONFIG_FLASH_SIZE <= 64
+#define REGION_FLASH_SIZE REGION_64K
+#elif CONFIG_FLASH_SIZE <= 128
+#define REGION_FLASH_SIZE REGION_128K
+#elif CONFIG_FLASH_SIZE <= 256
+#define REGION_FLASH_SIZE REGION_256K
+#elif CONFIG_FLASH_SIZE <= 512
+#define REGION_FLASH_SIZE REGION_512K
+#elif CONFIG_FLASH_SIZE <= 1024
+#define REGION_FLASH_SIZE REGION_1M
+#elif CONFIG_FLASH_SIZE <= 2048
+#define REGION_FLASH_SIZE REGION_2M
+#elif CONFIG_FLASH_SIZE <= 4096
+#define REGION_FLASH_SIZE REGION_4M
+#elif CONFIG_FLASH_SIZE <= 8192
+#define REGION_FLASH_SIZE REGION_8M
+#elif CONFIG_FLASH_SIZE <= 16384
+#define REGION_FLASH_SIZE REGION_16M
+#elif CONFIG_FLASH_SIZE <= 65536
+#define REGION_FLASH_SIZE REGION_64M
+#else
+#error "Unsupported configuration"
+#endif
+
+/* SRAM Region Definitions */
+#if CONFIG_SRAM_SIZE <= 16
+#define REGION_SRAM_SIZE REGION_16K
+#elif CONFIG_SRAM_SIZE <= 32
+#define REGION_SRAM_SIZE REGION_32K
+#elif CONFIG_SRAM_SIZE <= 64
+#define REGION_SRAM_SIZE REGION_64K
+#elif CONFIG_SRAM_SIZE <= 128
+#define REGION_SRAM_SIZE REGION_128K
+#elif CONFIG_SRAM_SIZE <= 256
+#define REGION_SRAM_SIZE REGION_256K
+#elif CONFIG_SRAM_SIZE <= 512
+#define REGION_SRAM_SIZE REGION_512K
+#elif CONFIG_SRAM_SIZE <= 1024
+#define REGION_SRAM_SIZE REGION_1M
+#elif CONFIG_SRAM_SIZE <= 2048
+#define REGION_SRAM_SIZE REGION_2M
+#elif CONFIG_SRAM_SIZE <= 4096
+#define REGION_SRAM_SIZE REGION_4M
+#elif CONFIG_SRAM_SIZE == 32768
+#define REGION_SRAM_SIZE REGION_32M
+#else
+#error "Unsupported configuration"
+#endif
+
+#endif /* !ARMV8_M_BASELINE && !ARMV8_M_MAINLINE */
+
+#endif /* _ARM_CORTEX_M_MPU_MEM_CFG_H_ */

soc/arm/common/cortex_m/arm_mpu_regions.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/slist.h>
+#include <misc/slist.h>
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+#include "arm_mpu_mem_cfg.h"
+
+static const struct arm_mpu_region mpu_regions[] = {
+	/* Region 0 */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \
+				 CONFIG_FLASH_SIZE * 1024)),
+#else
+			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
+#endif
+	/* Region 1 */
+	MPU_REGION_ENTRY("SRAM_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \
+				 CONFIG_SRAM_SIZE * 1024)),
+#else
+			 REGION_RAM_ATTR(REGION_SRAM_SIZE)),
+#endif
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};