drivers: uart_mcux_flexcomm: Add ASYNC API
Support ASYNC API on Flexcomm UART Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder
Mahesh Mahadevan
parent
2af408b8fa
commit
cf34d2cbdc
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@ -1,5 +1,4 @@
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# MCUXpresso SDK USART
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# Copyright 2017, NXP
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# SPDX-License-Identifier: Apache-2.0
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@ -9,6 +8,9 @@ config UART_MCUX_FLEXCOMM
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depends on DT_HAS_NXP_LPC_USART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SERIAL_SUPPORT_ASYNC if \
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DT_HAS_NXP_LPC_DMA_ENABLED
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select DMA if UART_ASYNC_API
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select PINCTRL
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help
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Enable the MCUX USART driver.
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@ -19,6 +19,19 @@
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#include <soc.h>
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#include <fsl_device_registers.h>
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#include <zephyr/drivers/pinctrl.h>
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#ifdef CONFIG_UART_ASYNC_API
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#include <zephyr/drivers/dma.h>
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#include <fsl_inputmux.h>
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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struct mcux_flexcomm_uart_dma_config {
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const struct device *dev;
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DMA_Type *base;
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uint8_t channel;
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struct dma_config cfg;
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};
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#endif
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struct mcux_flexcomm_config {
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USART_Type *base;
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@ -30,13 +43,46 @@ struct mcux_flexcomm_config {
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void (*irq_config_func)(const struct device *dev);
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#endif
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const struct pinctrl_dev_config *pincfg;
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#ifdef CONFIG_UART_ASYNC_API
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struct mcux_flexcomm_uart_dma_config tx_dma;
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struct mcux_flexcomm_uart_dma_config rx_dma;
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void (*rx_timeout_func)(struct k_work *work);
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void (*tx_timeout_func)(struct k_work *work);
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#endif
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};
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#if CONFIG_UART_ASYNC_API
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struct mcux_flexcomm_uart_tx_data {
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const uint8_t *xfer_buf;
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size_t xfer_len;
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struct dma_block_config active_block;
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struct k_work_delayable timeout_work;
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};
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struct mcux_flexcomm_uart_rx_data {
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uint8_t *xfer_buf;
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size_t xfer_len;
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struct dma_block_config active_block;
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uint8_t *next_xfer_buf;
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size_t next_xfer_len;
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struct k_work_delayable timeout_work;
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int32_t timeout;
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size_t count;
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size_t offset;
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};
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#endif
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struct mcux_flexcomm_data {
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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uart_irq_callback_user_data_t irq_callback;
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void *irq_cb_data;
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#endif
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#ifdef CONFIG_UART_ASYNC_API
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uart_callback_t async_callback;
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void *async_cb_data;
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struct mcux_flexcomm_uart_tx_data tx_data;
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struct mcux_flexcomm_uart_rx_data rx_data;
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#endif
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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struct uart_config uart_config;
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#endif
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@ -234,15 +280,6 @@ static void mcux_flexcomm_irq_callback_set(const struct device *dev,
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data->irq_callback = cb;
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data->irq_cb_data = cb_data;
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}
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static void mcux_flexcomm_isr(const struct device *dev)
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{
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struct mcux_flexcomm_data *data = dev->data;
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if (data->irq_callback) {
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data->irq_callback(dev, data->irq_cb_data);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
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@ -342,6 +379,612 @@ static int mcux_flexcomm_uart_config_get(const struct device *dev,
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}
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#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
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#ifdef CONFIG_UART_ASYNC_API
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/* This function is called by this driver to notify user callback of events */
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static void async_user_callback(const struct device *dev,
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struct uart_event *evt)
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{
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const struct mcux_flexcomm_data *data = dev->data;
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if (data->async_callback) {
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data->async_callback(dev, evt, data->async_cb_data);
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}
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}
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static int mcux_flexcomm_uart_callback_set(const struct device *dev,
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uart_callback_t callback,
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void *user_data)
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{
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struct mcux_flexcomm_data *data = dev->data;
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data->async_callback = callback;
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data->async_cb_data = user_data;
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return 0;
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}
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static int mcux_flexcomm_uart_tx(const struct device *dev, const uint8_t *buf,
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size_t len, int32_t timeout)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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int ret = 0;
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if (config->tx_dma.dev == NULL) {
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return -ENODEV;
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}
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unsigned int key = irq_lock();
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/* Getting DMA status to tell if channel is busy or not set up */
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struct dma_status status;
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ret = dma_get_status(config->tx_dma.dev, config->tx_dma.channel, &status);
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if (ret < 0) {
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return ret;
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}
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/* There is an ongoing transfer */
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if (status.busy) {
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return -EBUSY;
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}
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/* Disable TX DMA requests for uart while setting up */
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USART_EnableTxDMA(config->base, false);
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/* Set up the dma channel/transfer */
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data->tx_data.xfer_buf = buf;
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data->tx_data.xfer_len = len;
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data->tx_data.active_block.source_address = (uint32_t)buf;
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data->tx_data.active_block.dest_address = (uint32_t) &config->base->FIFOWR;
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data->tx_data.active_block.block_size = len;
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data->tx_data.active_block.next_block = NULL;
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ret = dma_config(config->tx_dma.dev, config->tx_dma.channel,
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(struct dma_config *) &config->tx_dma.cfg);
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if (ret) {
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return ret;
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}
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/* Enable interrupt for when TX fifo is empty (all data transmitted) */
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config->base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
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/* Enable TX DMA requests */
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USART_EnableTxDMA(config->base, true);
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/* Trigger the DMA to start transfer */
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ret = dma_start(config->tx_dma.dev, config->tx_dma.channel);
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if (ret) {
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return ret;
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}
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/* Schedule a TX abort for @param timeout */
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if (timeout != SYS_FOREVER_US) {
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k_work_schedule(&data->tx_data.timeout_work, K_USEC(timeout));
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}
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irq_unlock(key);
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return ret;
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}
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static int mcux_flexcomm_uart_tx_abort(const struct device *dev)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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int ret = 0;
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/* First disable DMA requests from UART to prevent transfer
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* status change during the abort routine
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*/
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USART_EnableTxDMA(config->base, false);
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/* In case there is no transfer to abort */
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if (data->tx_data.xfer_len == 0) {
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return -EFAULT;
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}
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/* In case a user called this function, do not abort twice */
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(void)k_work_cancel_delayable(&data->tx_data.timeout_work);
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/* Getting dma status to use to calculate bytes sent */
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struct dma_status status = {0};
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ret = dma_get_status(config->tx_dma.dev, config->tx_dma.channel, &status);
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if (ret < 0) {
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return ret;
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}
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/* Done with the DMA transfer, can stop it now */
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ret = dma_stop(config->tx_dma.dev, config->tx_dma.channel);
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if (ret) {
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return ret;
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}
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/* Define TX abort event before resetting driver variables */
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size_t sent_len = data->tx_data.xfer_len - status.pending_length;
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const uint8_t *aborted_buf = data->tx_data.xfer_buf;
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struct uart_event tx_abort_event = {
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.type = UART_TX_ABORTED,
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.data.tx.buf = aborted_buf,
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.data.tx.len = sent_len
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};
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/* Driver data needs reset since there is no longer an ongoing
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* transfer, this should before the user callback, not after,
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* just in case the user callback calls tx again
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*/
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data->tx_data.xfer_len = 0;
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data->tx_data.xfer_buf = NULL;
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async_user_callback(dev, &tx_abort_event);
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return ret;
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}
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static int mcux_flexcomm_uart_rx_enable(const struct device *dev, uint8_t *buf,
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const size_t len, const int32_t timeout)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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int ret = 0;
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if (config->rx_dma.dev == NULL) {
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return -ENODEV;
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}
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/* Getting DMA status to tell if channel is busy or not set up */
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struct dma_status status;
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ret = dma_get_status(config->rx_dma.dev, config->rx_dma.channel, &status);
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if (ret < 0) {
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return ret;
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}
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/* There is an ongoing transfer */
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if (status.busy) {
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return -EBUSY;
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}
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/* Disable RX DMA requests for uart while setting up */
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USART_EnableRxDMA(config->base, false);
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/* Set up the dma channel/transfer */
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data->rx_data.xfer_buf = buf;
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data->rx_data.xfer_len = len;
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data->rx_data.active_block.dest_address = (uint32_t)data->rx_data.xfer_buf;
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data->rx_data.active_block.source_address = (uint32_t) &config->base->FIFORD;
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data->rx_data.active_block.block_size = data->rx_data.xfer_len;
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ret = dma_config(config->rx_dma.dev, config->rx_dma.channel,
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(struct dma_config *) &config->rx_dma.cfg);
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if (ret) {
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return ret;
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}
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data->rx_data.timeout = timeout;
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/* Enable RX DMA requests from UART */
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USART_EnableRxDMA(config->base, true);
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/* Enable start bit detected interrupt, this is the only
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* way for the flexcomm uart to support the Zephyr Async API.
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* This is only needed if using a timeout.
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*/
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if (timeout != SYS_FOREVER_US) {
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config->base->INTENSET |= USART_INTENSET_STARTEN_MASK;
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}
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/* Trigger the DMA to start transfer */
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ret = dma_start(config->rx_dma.dev, config->rx_dma.channel);
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if (ret) {
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return ret;
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}
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/* Request next buffer */
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struct uart_event rx_buf_request = {
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.type = UART_RX_BUF_REQUEST,
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};
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async_user_callback(dev, &rx_buf_request);
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return ret;
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}
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static void flexcomm_uart_rx_update(const struct device *dev)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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struct dma_status status;
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(void)dma_get_status(config->rx_dma.dev, config->rx_dma.channel, &status);
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/* Calculate how many bytes have been received by RX DMA */
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size_t total_rx_receive_len = data->rx_data.xfer_len - status.pending_length;
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/* Generate RX ready event if there has been new data received */
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if (total_rx_receive_len > data->rx_data.offset) {
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data->rx_data.count = total_rx_receive_len - data->rx_data.offset;
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struct uart_event rx_rdy_event = {
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.type = UART_RX_RDY,
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.data.rx.buf = data->rx_data.xfer_buf,
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.data.rx.len = data->rx_data.count,
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.data.rx.offset = data->rx_data.offset,
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};
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async_user_callback(dev, &rx_rdy_event);
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}
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/* The data is no longer new, update buffer tracking variables */
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data->rx_data.offset += data->rx_data.count;
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data->rx_data.count = 0;
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}
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static int mcux_flexcomm_uart_rx_disable(const struct device *dev)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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int ret = 0;
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/* This bit can be used to check if RX is already disabled
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* because it is the bit changed by enabling and disabling DMA
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* requests, and in this driver, RX DMA requests should only be
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* disabled when the rx function is disabled other than when
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* setting up in uart_rx_enable.
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*/
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if (!(config->base->FIFOCFG & USART_FIFOCFG_DMARX_MASK)) {
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return -EFAULT;
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}
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/* In case a user called this function, don't disable twice */
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(void)k_work_cancel_delayable(&data->rx_data.timeout_work);
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/* Disable RX requests to pause DMA first and measure what happened,
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* Can't stop yet because DMA pending length is needed to
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* calculate how many bytes have been received
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*/
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USART_EnableRxDMA(config->base, false);
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/* Check if RX data received and generate rx ready event if so */
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flexcomm_uart_rx_update(dev);
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/* Notify DMA driver to stop transfer only after RX data handled */
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ret = dma_stop(config->rx_dma.dev, config->rx_dma.channel);
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if (ret) {
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return ret;
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}
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/* Generate buffer release event for current buffer */
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struct uart_event current_buffer_release_event = {
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.type = UART_RX_BUF_RELEASED,
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.data.rx_buf.buf = data->rx_data.xfer_buf,
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};
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async_user_callback(dev, ¤t_buffer_release_event);
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/* Generate buffer release event for next buffer */
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if (data->rx_data.next_xfer_buf) {
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struct uart_event next_buffer_release_event = {
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.type = UART_RX_BUF_RELEASED,
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.data.rx_buf.buf = data->rx_data.next_xfer_buf
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};
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async_user_callback(dev, &next_buffer_release_event);
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}
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/* Reset RX driver data */
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data->rx_data.xfer_buf = NULL;
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data->rx_data.xfer_len = 0;
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data->rx_data.next_xfer_buf = NULL;
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data->rx_data.next_xfer_len = 0;
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data->rx_data.offset = 0;
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data->rx_data.count = 0;
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/* Final event is the RX disable event */
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struct uart_event rx_disabled_event = {
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.type = UART_RX_DISABLED
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};
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async_user_callback(dev, &rx_disabled_event);
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return ret;
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}
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static int mcux_flexcomm_uart_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
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{
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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/* There is already a next buffer scheduled */
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if (data->rx_data.next_xfer_buf != NULL || data->rx_data.next_xfer_len != 0) {
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return -EBUSY;
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}
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/* DMA requests are disabled, meaning the RX has been disabled */
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if (!(config->base->FIFOCFG & USART_FIFOCFG_DMARX_MASK)) {
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return -EACCES;
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}
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/* If everything is fine, schedule the new buffer */
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data->rx_data.next_xfer_buf = buf;
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data->rx_data.next_xfer_len = len;
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return 0;
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}
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/* This callback is from the TX DMA and consumed by this driver */
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static void mcux_flexcomm_uart_dma_tx_callback(const struct device *dma_device, void *cb_data,
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uint32_t channel, int status)
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{
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/* DMA callback data was configured during driver init as UART device ptr */
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struct device *dev = (struct device *)cb_data;
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const struct mcux_flexcomm_config *config = dev->config;
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struct mcux_flexcomm_data *data = dev->data;
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unsigned int key = irq_lock();
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/* Turn off requests since we are aborting */
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USART_EnableTxDMA(config->base, false);
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/* Timeout did not happen */
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(void)k_work_cancel_delayable(&data->tx_data.timeout_work);
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irq_unlock(key);
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}
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/* This callback is from the RX DMA and consumed by this driver */
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static void mcux_flexcomm_uart_dma_rx_callback(const struct device *dma_device, void *cb_data,
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uint32_t channel, int status)
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{
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||||
/* DMA callback data was configured during driver init as UART device ptr */
|
||||
struct device *dev = (struct device *)cb_data;
|
||||
|
||||
const struct mcux_flexcomm_config *config = dev->config;
|
||||
struct mcux_flexcomm_data *data = dev->data;
|
||||
|
||||
/* Cancel timeout now that the transfer is complete */
|
||||
(void)k_work_cancel_delayable(&data->rx_data.timeout_work);
|
||||
|
||||
/* Update user with received RX data if needed */
|
||||
flexcomm_uart_rx_update(dev);
|
||||
|
||||
/* Release current buffer */
|
||||
struct uart_event current_buffer_release_event = {
|
||||
.type = UART_RX_BUF_RELEASED,
|
||||
.data.rx_buf.buf = data->rx_data.xfer_buf,
|
||||
};
|
||||
|
||||
async_user_callback(dev, ¤t_buffer_release_event);
|
||||
|
||||
if (data->rx_data.next_xfer_buf) {
|
||||
/* Replace buffer in driver data */
|
||||
data->rx_data.xfer_buf = data->rx_data.next_xfer_buf;
|
||||
data->rx_data.xfer_len = data->rx_data.next_xfer_len;
|
||||
data->rx_data.next_xfer_buf = NULL;
|
||||
data->rx_data.next_xfer_len = 0;
|
||||
|
||||
/* Reload DMA channel with new buffer */
|
||||
data->rx_data.active_block.block_size = data->rx_data.xfer_len;
|
||||
data->rx_data.active_block.dest_address = (uint32_t) data->rx_data.xfer_buf;
|
||||
dma_reload(config->rx_dma.dev, config->rx_dma.channel,
|
||||
data->rx_data.active_block.source_address,
|
||||
data->rx_data.active_block.dest_address,
|
||||
data->rx_data.active_block.block_size);
|
||||
|
||||
/* Request next buffer */
|
||||
struct uart_event rx_buf_request = {
|
||||
.type = UART_RX_BUF_REQUEST,
|
||||
};
|
||||
|
||||
async_user_callback(dev, &rx_buf_request);
|
||||
|
||||
/* Start the new transfer */
|
||||
dma_start(config->rx_dma.dev, config->rx_dma.channel);
|
||||
|
||||
} else {
|
||||
/* If there is no next available buffer then disable DMA */
|
||||
mcux_flexcomm_uart_rx_disable(dev);
|
||||
}
|
||||
|
||||
/* Now that this transfer was finished, reset tracking variables */
|
||||
data->rx_data.count = 0;
|
||||
data->rx_data.offset = 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX)
|
||||
/*
|
||||
* This functions calculates the inputmux connection value
|
||||
* needed by INPUTMUX_EnableSignal to allow the UART's DMA
|
||||
* request to reach the DMA.
|
||||
*/
|
||||
static uint32_t fc_uart_calc_inmux_connection(uint8_t channel, DMA_Type *base)
|
||||
{
|
||||
uint32_t chmux_avl = 0;
|
||||
uint32_t chmux_sel = 0;
|
||||
uint32_t chmux_val = 0;
|
||||
|
||||
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX)
|
||||
uint32_t chmux_sel_id = 0;
|
||||
|
||||
if (base == (DMA_Type *)DMA0_BASE) {
|
||||
chmux_sel_id = DMA0_CHMUX_SEL0_ID;
|
||||
} else if (base == (DMA_Type *)DMA1_BASE) {
|
||||
chmux_sel_id = DMA1_CHMUX_SEL0_ID;
|
||||
}
|
||||
|
||||
|
||||
if (channel >= 16 && !(channel >= 24 && channel <= 27)) {
|
||||
chmux_avl = 1 << CHMUX_AVL_SHIFT;
|
||||
} else {
|
||||
chmux_avl = 0;
|
||||
}
|
||||
|
||||
/* 1 for flexcomm */
|
||||
chmux_val = 1 << CHMUX_VAL_SHIFT;
|
||||
|
||||
|
||||
if (channel <= 15 || (channel >= 24 && channel <= 27)) {
|
||||
chmux_sel = 0;
|
||||
} else if (channel >= 16 && channel <= 23) {
|
||||
chmux_sel = (chmux_sel_id + 4 * (channel - 16))
|
||||
<< CHMUX_OFF_SHIFT;
|
||||
} else {
|
||||
chmux_sel = (chmux_sel_id + 4 * (channel - 20))
|
||||
<< CHMUX_OFF_SHIFT;
|
||||
}
|
||||
|
||||
#endif /* RT5xx */
|
||||
|
||||
uint32_t req_en_id = 0;
|
||||
|
||||
if (base == (DMA_Type *)DMA0_BASE) {
|
||||
req_en_id = DMA0_REQ_ENA0_ID;
|
||||
} else if (base == (DMA_Type *)DMA1_BASE) {
|
||||
req_en_id = DMA1_REQ_ENA0_ID;
|
||||
}
|
||||
|
||||
|
||||
uint32_t en_val;
|
||||
|
||||
if (channel <= 31) {
|
||||
en_val = channel + (req_en_id << ENA_SHIFT);
|
||||
} else {
|
||||
en_val = (channel - 32) + ((req_en_id + 4) << ENA_SHIFT);
|
||||
}
|
||||
|
||||
|
||||
uint32_t ret = en_val + chmux_avl + chmux_val + chmux_sel;
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* RT 3-digit */
|
||||
|
||||
|
||||
static int flexcomm_uart_async_init(const struct device *dev)
|
||||
{
|
||||
const struct mcux_flexcomm_config *config = dev->config;
|
||||
struct mcux_flexcomm_data *data = dev->data;
|
||||
|
||||
if (config->rx_dma.dev == NULL ||
|
||||
config->tx_dma.dev == NULL) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!device_is_ready(config->rx_dma.dev) ||
|
||||
!device_is_ready(config->tx_dma.dev)) {
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Disable DMA requests */
|
||||
USART_EnableTxDMA(config->base, false);
|
||||
USART_EnableRxDMA(config->base, false);
|
||||
|
||||
/* Route DMA requests */
|
||||
#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX)
|
||||
/* RT 3 digit uses input mux to route DMA requests from
|
||||
* the UART peripheral to a hardware designated DMA channel
|
||||
*/
|
||||
INPUTMUX_Init(INPUTMUX);
|
||||
INPUTMUX_EnableSignal(INPUTMUX,
|
||||
fc_uart_calc_inmux_connection(config->rx_dma.channel,
|
||||
config->rx_dma.base), true);
|
||||
INPUTMUX_EnableSignal(INPUTMUX,
|
||||
fc_uart_calc_inmux_connection(config->tx_dma.channel,
|
||||
config->tx_dma.base), true);
|
||||
INPUTMUX_Deinit(INPUTMUX);
|
||||
#endif /* RT5xx and RT6xx */
|
||||
|
||||
/* Init work objects for RX and TX timeouts */
|
||||
k_work_init_delayable(&data->tx_data.timeout_work,
|
||||
config->tx_timeout_func);
|
||||
k_work_init_delayable(&data->rx_data.timeout_work,
|
||||
config->rx_timeout_func);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_UART_ASYNC_API */
|
||||
|
||||
|
||||
static void mcux_flexcomm_isr(const struct device *dev)
|
||||
{
|
||||
struct mcux_flexcomm_data *data = dev->data;
|
||||
|
||||
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
|
||||
if (data->irq_callback) {
|
||||
data->irq_callback(dev, data->irq_cb_data);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
const struct mcux_flexcomm_config *config = dev->config;
|
||||
|
||||
/* If there is an async callback then we are using async api */
|
||||
if (data->async_callback) {
|
||||
|
||||
/* Handle RX interrupt (START bit detected)
|
||||
* RX interrupt defeats the purpose of UART ASYNC API
|
||||
* because core is involved for every byte but
|
||||
* it is included for compatibility of applications.
|
||||
* There is no other way with flexcomm UART to handle
|
||||
* Zephyr's RX ASYNC API. However, if not using the RX
|
||||
* timeout (timeout is forever), then the performance is
|
||||
* still as might be expected.
|
||||
*/
|
||||
if (config->base->INTSTAT & USART_INTSTAT_START_MASK) {
|
||||
|
||||
/* Receiving some data so reschedule timeout,
|
||||
* unless timeout is 0 in which case just handle
|
||||
* rx data now. If timeout is forever, don't do anything.
|
||||
*/
|
||||
if (data->rx_data.timeout == 0) {
|
||||
flexcomm_uart_rx_update(dev);
|
||||
} else if (data->rx_data.timeout != SYS_FOREVER_US) {
|
||||
k_work_reschedule(&data->rx_data.timeout_work,
|
||||
K_USEC(data->rx_data.timeout));
|
||||
}
|
||||
|
||||
/* Write 1 to clear start bit status bit */
|
||||
config->base->STAT |= USART_STAT_START_MASK;
|
||||
}
|
||||
|
||||
/* Handle TX interrupt (TXLVL = 0)
|
||||
* Default TXLVL interrupt happens when TXLVL = 0, which
|
||||
* has not been changed by this driver, so in this case the
|
||||
* TX interrupt should happen when transfer is complete
|
||||
* because DMA filling TX fifo is faster than transmitter rate
|
||||
*/
|
||||
if (config->base->FIFOINTSTAT & USART_FIFOINTSTAT_TXLVL_MASK) {
|
||||
|
||||
/* Disable interrupt */
|
||||
config->base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
|
||||
|
||||
/* Set up TX done event to notify the user of completion */
|
||||
struct uart_event tx_done_event = {
|
||||
.type = UART_TX_DONE,
|
||||
.data.tx.buf = data->tx_data.xfer_buf,
|
||||
.data.tx.len = data->tx_data.xfer_len,
|
||||
};
|
||||
|
||||
/* Reset TX data */
|
||||
data->tx_data.xfer_len = 0;
|
||||
data->tx_data.xfer_buf = NULL;
|
||||
|
||||
async_user_callback(dev, &tx_done_event);
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static int mcux_flexcomm_init(const struct device *dev)
|
||||
{
|
||||
const struct mcux_flexcomm_config *config = dev->config;
|
||||
|
|
@ -398,6 +1041,13 @@ static int mcux_flexcomm_init(const struct device *dev)
|
|||
config->irq_config_func(dev);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
err = flexcomm_uart_async_init(dev);
|
||||
if (err) {
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -425,6 +1075,14 @@ static const struct uart_driver_api mcux_flexcomm_driver_api = {
|
|||
.irq_update = mcux_flexcomm_irq_update,
|
||||
.irq_callback_set = mcux_flexcomm_irq_callback_set,
|
||||
#endif
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
.callback_set = mcux_flexcomm_uart_callback_set,
|
||||
.tx = mcux_flexcomm_uart_tx,
|
||||
.tx_abort = mcux_flexcomm_uart_tx_abort,
|
||||
.rx_enable = mcux_flexcomm_uart_rx_enable,
|
||||
.rx_disable = mcux_flexcomm_uart_rx_disable,
|
||||
.rx_buf_rsp = mcux_flexcomm_uart_rx_buf_rsp,
|
||||
#endif
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -445,6 +1103,70 @@ static const struct uart_driver_api mcux_flexcomm_driver_api = {
|
|||
#define UART_MCUX_FLEXCOMM_IRQ_CFG_FUNC_INIT(n)
|
||||
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
|
||||
|
||||
#ifdef CONFIG_UART_ASYNC_API
|
||||
#define UART_MCUX_FLEXCOMM_TX_TIMEOUT_FUNC(n) \
|
||||
static void mcux_flexcomm_uart_##n##_tx_timeout(struct k_work *work) \
|
||||
{ \
|
||||
mcux_flexcomm_uart_tx_abort(DEVICE_DT_INST_GET(n)); \
|
||||
}
|
||||
#define UART_MCUX_FLEXCOMM_RX_TIMEOUT_FUNC(n) \
|
||||
static void mcux_flexcomm_uart_##n##_rx_timeout(struct k_work *work) \
|
||||
{ \
|
||||
flexcomm_uart_rx_update(DEVICE_DT_INST_GET(n)); \
|
||||
}
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(UART_MCUX_FLEXCOMM_TX_TIMEOUT_FUNC);
|
||||
DT_INST_FOREACH_STATUS_OKAY(UART_MCUX_FLEXCOMM_RX_TIMEOUT_FUNC);
|
||||
|
||||
#define UART_MCUX_FLEXCOMM_ASYNC_CFG(n) \
|
||||
.tx_dma = { \
|
||||
.dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
|
||||
.channel = DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
|
||||
.cfg = { \
|
||||
.source_burst_length = 1, \
|
||||
.dest_burst_length = 1, \
|
||||
.source_data_size = 1, \
|
||||
.dest_data_size = 1, \
|
||||
.complete_callback_en = 1, \
|
||||
.error_callback_en = 1, \
|
||||
.block_count = 1, \
|
||||
.head_block = \
|
||||
&mcux_flexcomm_##n##_data.tx_data.active_block, \
|
||||
.channel_direction = MEMORY_TO_PERIPHERAL, \
|
||||
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, channel), \
|
||||
.dma_callback = mcux_flexcomm_uart_dma_tx_callback, \
|
||||
.user_data = (void *)DEVICE_DT_INST_GET(n), \
|
||||
}, \
|
||||
.base = (DMA_Type *) \
|
||||
DT_REG_ADDR(DT_INST_DMAS_CTLR_BY_NAME(n, tx)), \
|
||||
}, \
|
||||
.rx_dma = { \
|
||||
.dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
|
||||
.channel = DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
|
||||
.cfg = { \
|
||||
.source_burst_length = 1, \
|
||||
.dest_burst_length = 1, \
|
||||
.source_data_size = 1, \
|
||||
.dest_data_size = 1, \
|
||||
.complete_callback_en = 1, \
|
||||
.error_callback_en = 1, \
|
||||
.block_count = 1, \
|
||||
.head_block = \
|
||||
&mcux_flexcomm_##n##_data.rx_data.active_block, \
|
||||
.channel_direction = PERIPHERAL_TO_MEMORY, \
|
||||
.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, channel), \
|
||||
.dma_callback = mcux_flexcomm_uart_dma_rx_callback, \
|
||||
.user_data = (void *)DEVICE_DT_INST_GET(n) \
|
||||
}, \
|
||||
.base = (DMA_Type *) \
|
||||
DT_REG_ADDR(DT_INST_DMAS_CTLR_BY_NAME(n, rx)), \
|
||||
}, \
|
||||
.rx_timeout_func = mcux_flexcomm_uart_##n##_rx_timeout, \
|
||||
.tx_timeout_func = mcux_flexcomm_uart_##n##_tx_timeout,
|
||||
#else
|
||||
#define UART_MCUX_FLEXCOMM_ASYNC_CFG(n)
|
||||
#endif /* CONFIG_UART_ASYNC_API */
|
||||
|
||||
#define UART_MCUX_FLEXCOMM_INIT_CFG(n) \
|
||||
static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config = { \
|
||||
.base = (USART_Type *)DT_INST_REG_ADDR(n), \
|
||||
|
|
@ -455,7 +1177,8 @@ static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config = { \
|
|||
.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE), \
|
||||
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
|
||||
UART_MCUX_FLEXCOMM_IRQ_CFG_FUNC_INIT(n) \
|
||||
}
|
||||
UART_MCUX_FLEXCOMM_ASYNC_CFG(n) \
|
||||
};
|
||||
|
||||
#define UART_MCUX_FLEXCOMM_INIT(n) \
|
||||
\
|
||||
|
|
@ -476,6 +1199,6 @@ static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config = { \
|
|||
\
|
||||
UART_MCUX_FLEXCOMM_IRQ_CFG_FUNC(n) \
|
||||
\
|
||||
UART_MCUX_FLEXCOMM_INIT_CFG(n);
|
||||
UART_MCUX_FLEXCOMM_INIT_CFG(n)
|
||||
|
||||
DT_INST_FOREACH_STATUS_OKAY(UART_MCUX_FLEXCOMM_INIT)
|
||||
|
|
|
|||
Loading…
Reference in a new issue