boards: xtensa: intel_s1000_crb: Enable SPI Master driver
patch enables SPI Master driver on intel_s1000_crb Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This commit is contained in:
parent
eddfd537d2
commit
cf58f83dd6
|
@ -60,6 +60,9 @@ config HEAP_MEM_POOL_SIZE
|
|||
|
||||
endif # DMA_CAVS
|
||||
|
||||
config SPI_DW_FIFO_DEPTH
|
||||
default 32
|
||||
|
||||
if USB
|
||||
config USB_DW
|
||||
default y
|
||||
|
@ -145,5 +148,14 @@ config GPIO_DW_0
|
|||
|
||||
endif
|
||||
|
||||
if SPI
|
||||
|
||||
config SPI_DW
|
||||
def_bool y
|
||||
|
||||
config SPI_0
|
||||
def_bool y
|
||||
|
||||
endif
|
||||
|
||||
endif # BOARD_INTEL_S1000_CRB
|
||||
|
|
|
@ -32,4 +32,3 @@ CONFIG_SERIAL_HAS_DRIVER=y
|
|||
CONFIG_SERIAL=y
|
||||
CONFIG_UART_CONSOLE=y
|
||||
CONFIG_UART_NS16550=y
|
||||
|
||||
|
|
|
@ -109,7 +109,12 @@ struct spi_dw_data {
|
|||
#define DW_SPI_CTRLR0_SLV_OE_BIT (10)
|
||||
#define DW_SPI_CTRLR0_SLV_OE BIT(DW_SPI_CTRLR0_SLV_OE_BIT)
|
||||
|
||||
#ifdef CONFIG_SOC_INTEL_S1000
|
||||
#define DW_SPI_CTRLR0_TMOD_SHIFT (10)
|
||||
#else
|
||||
#define DW_SPI_CTRLR0_TMOD_SHIFT (8)
|
||||
#endif
|
||||
|
||||
#define DW_SPI_CTRLR0_TMOD_TX_RX (0)
|
||||
#define DW_SPI_CTRLR0_TMOD_TX (1 << DW_SPI_CTRLR0_TMOD_SHIFT)
|
||||
#define DW_SPI_CTRLR0_TMOD_RX (2 << DW_SPI_CTRLR0_TMOD_SHIFT)
|
||||
|
@ -119,7 +124,7 @@ struct spi_dw_data {
|
|||
#define DW_SPI_CTRLR0_DFS_16(__bpw) ((__bpw) - 1)
|
||||
#define DW_SPI_CTRLR0_DFS_32(__bpw) (((__bpw) - 1) << 16)
|
||||
|
||||
#ifdef CONFIG_ARC
|
||||
#if defined(CONFIG_ARC) || defined(CONFIG_SOC_INTEL_S1000)
|
||||
#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_16
|
||||
#else
|
||||
#define DW_SPI_CTRLR0_DFS DW_SPI_CTRLR0_DFS_32
|
||||
|
|
|
@ -109,5 +109,16 @@
|
|||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@e000 {
|
||||
compatible = "snps,designware-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0000E000 0x400>;
|
||||
interrupts = <7 0 0>;
|
||||
interrupt-parent = <&dw_intc>;
|
||||
label = "SPI_0";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
|
@ -46,4 +46,17 @@
|
|||
|
||||
#define DT_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
|
||||
#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
|
||||
|
||||
|
||||
#define CONFIG_SPI_0_BASE_ADDRESS SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
|
||||
#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_E000_LABEL
|
||||
|
||||
#define CONFIG_SPI_0_IRQ ((SNPS_DESIGNWARE_SPI_E000_IRQ_0 << 16) | \
|
||||
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
|
||||
(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
|
||||
|
||||
|
||||
#define SPI_DW_IRQ_FLAGS SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
|
||||
|
||||
#define CONFIG_SPI_0_IRQ_PRI SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
Loading…
Reference in a new issue