dts: arm: Add Renesas r8a779f0 support

r8a779f0 is also know as S4, this SoC is part of the Gen4 SoC series,
has 8 Cortex-A55 and a dual core lockstep Cortex-R52 processor.

SCIF0 is dedicated to Zephyr and SCIF3 to Linux.

**Control Domains**
IMPORTANT: This SoC is divided into two "domains":
- Application domain contains some peripherals as well as A55 & R52 cores.
- Control domain that contain a G4MH/RH850 MCU and other peripherals.

In order to access control domain peripherals such as gpio4-7 and CAN-FD
from application domain, the G4MH MCU has to unlock a protection
mechanism from control domain buses.

"Protected" controllers will be flagged in gen4 device trees,
warning users that they need to flash a custom G4MH firmware
to unlock access to these controllers.

**Clock controller**
This SoC clock controller is offering "domains"
for each world (Zephyr/Linux).

These domains are several "entry points" to the clock controller
which are arbitrated to avoid a world from turning off a clock needed
by another one.

We decided to use the same domain as Linux because the
security mechanism as to be implemented before accessing
another domain.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>

dts/arm/renesas/rcar/gen4/r8a779f0.dtsi

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <renesas/rcar/gen4/rcar_gen4_cr52.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/clock/r8a779f0_cpg_mssr.h>
+
+/ {
+	soc {
+		/* The last four registers of this controller are
+		 * located in the control domain
+		 * A custom G4MH/RH850 µC firmware has to be flashed to access them
+		 */
+		pfc: pin-controller@e6050000 {
+			compatible = "renesas,rcar-pfc";
+			reg = <0xe6050000 0x16c>, <0xe6050800 0x16c>,
+				  <0xe6051000 0x16c>, <0xe6051800 0x16c>,
+				  <0xdfd90000 0x16c>, <0xdfd90800 0x16c>,
+				  <0xdfd91000 0x16c>, <0xdfd91800 0x16c>;
+		};
+
+		/* Clock controller
+		 * Using domain 0 as Linux
+		 */
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a779f0-cpg-mssr";
+			reg = <0xe6150000 0x4000>;
+			#clock-cells = <2>;
+		};
+
+		gpio0: gpio@e6050180 {
+			compatible = "renesas,rcar-gpio";
+			reg = <0xe6050180 0x54>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 915>;
+			status = "disabled";
+		};
+
+		/*
+		 * Control domain security has to be released to access gpio4 controller
+		 * A custom G4MH/RH850 µC firmware has to be flashed to do that
+		 */
+		gpio4: gpio@dfd90180 {
+			compatible = "renesas,rcar-gpio";
+			reg = <0xdfd90180 0x54>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			interrupts = <GIC_SPI 826 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 915>;
+			status = "disabled";
+		};
+
+		/* Zephyr console */
+		scif0: serial@e6e60000 {
+			interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 702>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
+		};
+
+		/* Linux console */
+		scif3: serial@e6c50000 {
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_CORE R8A779F0_CLK_S0D12_PER>;
+		};
+	};
+};

dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2023 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm64/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/clock/renesas_cpg_mssr.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+				 IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL
+				 IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL
+				 IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL
+				 IRQ_DEFAULT_PRIORITY>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		sram0: memory@40040000 {
+			compatible = "mmio-sram";
+			reg = <0x40040000 0x100000>;
+		};
+
+		gic: interrupt-controller@f0000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0xf0000000 0x1000>,
+				  <0xf0100000 0x20000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		scif0: serial@e6e60000 {
+			compatible = "renesas,rcar-scif";
+			reg = <0xe6e60000 0x64>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		scif3: serial@e6c50000 {
+			compatible = "renesas,rcar-scif";
+			reg = <0xe6c50000 0x64>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+	};
+};