patrick/zephyr
1
0
Fork 0
Code Issues Pull requests Actions 8 Packages Projects Releases Wiki Activity

intel_adsp: move memory windows to DTS proper

Browse source 
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.

Move FW status to own workflow and separate from window setup.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-08-09 20:31:37 -04:00
parent e8395351e6
commit d038eb5dc7
29 changed files with 324 additions and 128 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.dts
View file

@ -19,5 +19,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs15/intel_adsp_cavs15.dts
View file

@ -14,5 +14,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs18/intel_adsp_cavs18.dts
View file

@ -14,5 +14,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20.dts
View file

@ -14,5 +14,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs20/intel_adsp_cavs20_jsl.dts
View file

@ -14,5 +14,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts
View file

@ -18,5 +18,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

1
boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts
View file

@ -18,5 +18,6 @@
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

22
dts/bindings/memory-window/intel,adsp-mem-window.yaml Normal file
View file

@ -0,0 +1,22 @@
description: ADSP Memory Window
compatible: "intel,adsp-mem-window"
include: [base.yaml]
properties:
reg:
required: true
initialize:
type: boolean
description: Initialize memory region and flush cache.
memory:
required: true
type: phandle
description: memory region the windows are exposed through.
offset:
type: int
description: offset from memory base.

26
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -157,9 +157,29 @@
reg = <0x28800 0x1000>;
};
win: win@70200 {
compatible = "intel,cavs-win";
reg = <0x70200 0x30>;
mem_window0: mem_window@70200 {
compatible = "intel,adsp-mem-window";
reg = <0x70200 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
reg = <0x70208 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@70210 {
compatible = "intel,adsp-mem-window";
reg = <0x70210 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@70218 {
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
};
tlb: tlb@17e000 {

26
dts/xtensa/intel/intel_adsp_cavs15.dtsi
View file

@ -73,9 +73,29 @@
reg = <0x1500 0x40>;
};
win: win@1580 {
compatible = "intel,cavs-win";
reg = <0x1580 0x20>;
mem_window0: mem_window@1580 {
compatible = "intel,adsp-mem-window";
reg = <0x1580 0x8>;
offset = <0x6000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@1588 {
compatible = "intel,adsp-mem-window";
reg = <0x1588 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@1590 {
compatible = "intel,adsp-mem-window";
reg = <0x1590 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@1598 {
compatible = "intel,adsp-mem-window";
reg = <0x1598 0x8>;
memory = <&sram0>;
};
core_intc: core_intc@0 {

26
dts/xtensa/intel/intel_adsp_cavs18.dtsi
View file

@ -65,9 +65,29 @@
reg = <0x71f00 0x100>;
};
win: win@71a00 {
compatible = "intel,cavs-win";
reg = <0x71a00 0x20>;
mem_window0: mem_window@71a00 {
compatible = "intel,adsp-mem-window";
reg = <0x71a00 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
reg = <0x71a08 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@71a10 {
compatible = "intel,adsp-mem-window";
reg = <0x71a10 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@71a18 {
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
};
l2lm: l2lm@71d00 {

26
dts/xtensa/intel/intel_adsp_cavs20.dtsi
View file

@ -65,9 +65,29 @@
reg = <0x71f00 0x100>;
};
win: win@71a00 {
compatible = "intel,cavs-win";
reg = <0x71a00 0x20>;
mem_window0: mem_window@71a00 {
compatible = "intel,adsp-mem-window";
reg = <0x71a00 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
reg = <0x71a08 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@71a10 {
compatible = "intel,adsp-mem-window";
reg = <0x71a10 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@71a18 {
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
};
l2lm: l2lm@71d00 {

26
dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi
View file

@ -44,11 +44,31 @@
reg = <0x71f00 0x100>;
};
win: win@71a00 {
compatible = "intel,cavs-win";
reg = <0x71a00 0x20>;
mem_window0: mem_window@71a00 {
compatible = "intel,adsp-mem-window";
reg = <0x71a00 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
reg = <0x71a08 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@71a10 {
compatible = "intel,adsp-mem-window";
reg = <0x71a10 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@71a18 {
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
};
l2lm: l2lm@71d00 {
compatible = "intel,cavs-l2lm";
reg = <0x71d00 0x20>;

26
dts/xtensa/intel/intel_adsp_cavs25.dtsi
View file

@ -85,9 +85,29 @@
reg = <0x71f00 0x100>;
};
win: win@71a00 {
compatible = "intel,cavs-win";
reg = <0x71a00 0x20>;
mem_window0: mem_window@71a00 {
compatible = "intel,adsp-mem-window";
reg = <0x71a00 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
reg = <0x71a08 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@71a10 {
compatible = "intel,adsp-mem-window";
reg = <0x71a10 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@71a18 {
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
};
sspbase: ssp_base@71c00 {

26
dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi
View file

@ -43,9 +43,29 @@
reg = <0x71f00 0x100>;
};
win: win@71a00 {
compatible = "intel,cavs-win";
reg = <0x71a00 0x20>;
mem_window0: mem_window@71a00 {
compatible = "intel,adsp-mem-window";
reg = <0x71a00 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
reg = <0x71a08 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@71a10 {
compatible = "intel,adsp-mem-window";
reg = <0x71a10 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@71a18 {
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
};
l2lm: l2lm@71d00 {

60
soc/xtensa/intel_adsp/Kconfig
View file

@ -28,6 +28,38 @@ config INTEL_ADSP_IPC
Driver for the host IPC interrupt delivery mechanism.
Currently SOF has its own driver for this hardware.
config MEMORY_WIN_0_SIZE
int "Size of memory window 0"
default 8192
help
Size of memory window 0.
This window is used for firmware status & outbox/uplink mbox.
config MEMORY_WIN_1_SIZE
int "Size of memory window 1"
default 8192
help
Size of memory window 1.
This window is used for inbox/downlink mbox.
config MEMORY_WIN_2_SIZE
int "Size of memory window 2"
default 8192
help
Size of memory window 2.
This window is used for debug.
config MEMORY_WIN_3_SIZE
int "Size of memory window 3"
default 8192
help
Size of memory window 3.
This window is used for trace.
config ADSP_CLOCK
bool
help
@ -43,34 +75,6 @@ config HP_SRAM_RESERVE
addresses here. The SOF application also makes direct use
of this region, so be very careful changing this value.
config ADSP_WIN0_OFFSET
int "Byte offset of host window zero"
default 16384
help
Offset of the first host shared memory window (used for the
"firmware status register" at boot) within the reserved
region at the start of HP-SRAM.
config ADSP_WIN2_OFFSET
int "Byte offset of host window two"
default 32768
help
Offset of the second host shared memory window within
the reserved region at the start of HP-SRAM.
Typically used for debug output, but semantics can vary
depending on the host-firmware communication scheme that
is used.
config ADSP_WIN3_OFFSET
int "Byte offset of host window three"
default 40960
help
Offset of the second host shared memory window within
the reserved region at the start of HP-SRAM.
Typically used for debug output, but semantics can vary
depending on the host-firmware communication scheme that
is used.
config ADSP_TRACE_SIMCALL
bool "Emit SIMCALL output in addition to window tracing"
help

9
soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h
View file

@ -22,15 +22,6 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,

6
soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15
View file

@ -17,12 +17,6 @@ config SOC_SERIES_INTEL_CAVS_V15
config HP_SRAM_RESERVE
default 32768
config ADSP_WIN0_OFFSET
default 24576
config ADSP_WIN3_OFFSET
default 0
config MP_NUM_CPUS
default 2

9
soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_memory.h
View file

@ -22,15 +22,6 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,

9
soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_memory.h
View file

@ -22,15 +22,6 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,

9
soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_memory.h
View file

@ -22,15 +22,6 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,

9
soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h
View file

@ -22,15 +22,6 @@
#define RAM_BASE (L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE + VECTOR_TBL_SIZE)
#define RAM_SIZE (L2_SRAM_SIZE - CONFIG_HP_SRAM_RESERVE - VECTOR_TBL_SIZE)
/* Host shared memory windows */
#define HP_SRAM_WIN0_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN0_OFFSET)
#define HP_SRAM_WIN0_SIZE 0x2000
#define HP_SRAM_WIN2_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN2_OFFSET)
/* window 2 size is variable */
#define HP_SRAM_WIN2_SIZE (CONFIG_ADSP_WIN3_OFFSET - CONFIG_ADSP_WIN2_OFFSET)
#define HP_SRAM_WIN3_BASE (L2_SRAM_BASE + CONFIG_ADSP_WIN3_OFFSET)
#define HP_SRAM_WIN3_SIZE 0x2000
/* The rimage tool produces two blob addresses we need to find: one is
* our bootloader code block which starts at its entry point, the
* other is the "manifest" containing the HP-SRAM data to unpack,

1
soc/xtensa/intel_adsp/common/CMakeLists.txt
View file

@ -16,6 +16,7 @@ zephyr_library_sources(
rimage_modules.c
boot.c
soc.c
mem_window.c
)
zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c)

27
soc/xtensa/intel_adsp/common/boot.c
View file

@ -7,6 +7,8 @@
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/arch/xtensa/cache.h>
#include <adsp_shim.h>
@ -128,26 +130,6 @@ __imr void parse_manifest(void)
}
}
__imr void win_setup(void)
{
uint32_t *win0 = z_soc_uncached_ptr((void *)HP_SRAM_WIN0_BASE);
/* Software protocol: "firmware entered" has the value 5 */
win0[0] = 5;
CAVS_WIN[0].dmwlo = HP_SRAM_WIN0_SIZE | 0x7;
CAVS_WIN[0].dmwba = (HP_SRAM_WIN0_BASE | CAVS_DMWBA_READONLY
| CAVS_DMWBA_ENABLE);
CAVS_WIN[2].dmwlo = HP_SRAM_WIN2_SIZE | 0x7;
CAVS_WIN[2].dmwba = (HP_SRAM_WIN2_BASE | CAVS_DMWBA_ENABLE);
CAVS_WIN[3].dmwlo = HP_SRAM_WIN3_SIZE | 0x7;
CAVS_WIN[3].dmwba = (HP_SRAM_WIN3_BASE | CAVS_DMWBA_READONLY
| CAVS_DMWBA_ENABLE);
}
extern void hp_sram_init(uint32_t memory_size);
extern void lp_sram_init(void);
extern void hp_sram_pm_banks(uint32_t banks);
@ -166,12 +148,13 @@ __imr void boot_core0(void)
#endif
hp_sram_init(L2_SRAM_SIZE);
win_setup();
lp_sram_init();
parse_manifest();
soc_trace_init();
z_xtensa_cache_flush_all();
z_sys_init_run_level(_SYS_INIT_LEVEL_ARCH);
soc_trace_init();
/* Zephyr! */
extern FUNC_NORETURN void z_cstart(void);
z_cstart();

7
soc/xtensa/intel_adsp/common/include/adsp_debug_window.h
View file

@ -61,7 +61,12 @@ struct adsp_debug_window {
uint8_t slots[ADSP_DW_SLOT_COUNT][ADSP_DW_SLOT_SIZE];
} __packed;
#define WIN2_MBASE DT_REG_ADDR(DT_PHANDLE(DT_NODELABEL(mem_window2), memory))
#define WIN2_OFFSET DT_PROP(DT_NODELABEL(mem_window2), offset)
#define ADSP_DW ((volatile struct adsp_debug_window *) \
(z_soc_uncached_ptr((void *)HP_SRAM_WIN2_BASE)))
(z_soc_uncached_ptr((void *)(WIN2_MBASE + WIN2_OFFSET))))
#endif

19
soc/xtensa/intel_adsp/common/include/mem_window.h Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2022 Intel Corp.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ADSP_MEMORY_WINDOW_H_
#define _ADSP_MEMORY_WINDOW_H_
struct mem_win_config {
uint32_t base_addr;
uint32_t size;
uint32_t offset;
uint32_t mem_base;
bool initialize;
};
#endif

2
soc/xtensa/intel_adsp/common/include/soc.h
View file

@ -54,7 +54,7 @@
#define DSP_WCT_CS_TT(x) BIT(4 + x)
extern void soc_trace_init(void);
extern int soc_trace_init(void);
extern void z_soc_mp_asm_entry(void);
extern void soc_mp_startup(uint32_t cpu);

56
soc/xtensa/intel_adsp/common/mem_window.c Normal file
View file

@ -0,0 +1,56 @@
/* Copyright(c) 2022 Intel Corporation. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/xtensa/cache.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
#include <mem_window.h>
#include <soc.h>
/* host windows */
#define DMWBA(win_base) (win_base + 0x0)
#define DMWLO(win_base) (win_base + 0x4)
#define DT_DRV_COMPAT intel_adsp_mem_window
#define WIN_SIZE(N) (CONFIG_MEMORY_WIN_##N##_SIZE)
#define WIN0_OFFSET DT_PROP(DT_NODELABEL(mem_window0), offset)
#define WIN1_OFFSET WIN0_OFFSET + WIN_SIZE(0)
#define WIN2_OFFSET WIN1_OFFSET + WIN_SIZE(1)
#define WIN3_OFFSET WIN2_OFFSET + WIN_SIZE(2)
#define WIN_OFFSET(N) (WIN##N##_OFFSET)
__imr int mem_win_init(const struct device *dev)
{
const struct mem_win_config *config = dev->config;
if (config->initialize) {
uint32_t *win = z_soc_uncached_ptr((void *)config->mem_base);
/* Software protocol: "firmware entered" has the value 5 */
win[0] = 5;
}
sys_write32(config->size | 0x7, DMWLO(config->base_addr));
sys_write32((config->mem_base | CAVS_DMWBA_READONLY | CAVS_DMWBA_ENABLE),
DMWBA(config->base_addr));
return 0;
}
#define MEM_WIN_INIT(inst) \
static const struct mem_win_config mem_win_config_##inst = { \
.base_addr = DT_INST_REG_ADDR(inst), \
.size = WIN_SIZE(inst), \
.offset = WIN_OFFSET(inst), \
.mem_base = DT_REG_ADDR(DT_INST_PHANDLE(inst, memory)) + WIN_OFFSET(inst), \
.initialize = DT_INST_PROP(inst, initialize), \
}; \
DEVICE_DT_INST_DEFINE(inst, mem_win_init, NULL, NULL, &mem_win_config_##inst, ARCH, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
DT_INST_FOREACH_STATUS_OKAY(MEM_WIN_INIT)

18
soc/xtensa/intel_adsp/common/trace_out.c
View file

@ -2,9 +2,12 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/winstream.h>
#include <zephyr/device.h>
#include <soc.h>
#include <adsp_memory.h>
#include <zephyr/sys/winstream.h>
#include <mem_window.h>
struct k_spinlock trace_lock;
@ -40,9 +43,16 @@ int arch_printk_char_out(int c)
return 0;
}
void soc_trace_init(void)
int soc_trace_init(void)
{
void *buf = z_soc_uncached_ptr((void *)HP_SRAM_WIN3_BASE);
const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
winstream = sys_winstream_init(buf, HP_SRAM_WIN3_SIZE);
if (!device_is_ready(dev)) {
return -ENODEV;
}
const struct mem_win_config *config = dev->config;
void *buf = arch_xtensa_uncached_ptr((void *)config->mem_base);
winstream = sys_winstream_init(buf, config->size);
return 0;
}