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ext: simplelink: Update cc32xx SDK to version 1.50.00.06

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This includes:
- peripheral drivers
- driverlib (HAL)
- WiFi host driver and porting layer interface headers

See README in this patch for details.

Origin: Texas Instruments cc32xx SimpleLink SDK
URL: http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK
Purpose: Provide driver libraries and HAL for TI CC32XX SoC
Maintained-by: External

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
This commit is contained in:
Gil Pitney 2017-10-03 11:59:17 -07:00 committed by Kumar Gala
parent e9eb128895
commit d06212707d
218 changed files with 105590 additions and 400 deletions
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27
ext/hal/ti/simplelink/README
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@ -6,25 +6,32 @@ For an explanation of the SimpleLink family SDK directory structure, see:
http://dev.ti.com/tirex/content/simplelink_cc13x0_sdk_1_30_00_06/docs/simplelink_mcu_sdk/Users_Guide.html#directory-structure
The current version supported in Zephyr is the SimpleLink CC3220 SDK
1.30.01.03, downloaded from:
1.50.00.06, downloaded from:
http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK
A subset of the files in the source/ti/devices/cc32xx/driverlib/ and inc/
directories are copied from a Linux CC3220 SDK installation without
modification.
The source files in the source/ti/devices/ and source/ti/drivers/
directories are copied from a Linux CC3220 SDK installation, using
the following commands:
TI provides the driver library functions burned into ROM at the factory,
% cd ~/ti/simplelink_cc32xx_sdk_1_50_00_06/
% find devices -name '*.[c|h]' | \
cpio -pdm ~/zephyr/ext/hal/ti/simplelink/source/ti
% find drivers -name '*.[c|h]' | \
cpio -pdm ~/zephyr/ext/hal/ti/simplelink/source/ti
In a separate commit, the file modes and trailing whitespace are fixed.
Note: TI provides the driver library functions burned into ROM at the factory,
or updated via a service pack patch, thus saving application code space.
Calling driverlib APIs prefixed by "MAP_" will vector to those functions
already existing in ROM.
For the zephyr shell sample, for example, using these ROM functions
results in a savings of about 2Kb in code space.
After setting CONFIG_HAS_CC3220SDK=y in Kconfig, most of the
peripheral driver library functions will be accessible from ROM,
except for the following modules:
- driverlib/prcm.c
except for some functions in the following modules, which are
compiled in the Kbuild file:
- driverlib/pin.c
- driverlib/utils.c
- driverlib/prcm.c

168
ext/hal/ti/simplelink/source/ti/devices/DeviceFamily.h Executable file
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@ -0,0 +1,168 @@
/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file DeviceFamily.h
*
* @brief Infrastructure to select correct driverlib path and identify devices
*
* This module enables the selection of the correct driverlib path for the current
* device. It also facilitates the use of per-device conditional compilation
* to enable minor variations in drivers between devices.
*
* In order to use this functionality, DeviceFamily_XYZ must be defined as one of
* the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines
* are set based on DeviceFamily_XYZ.
*/
#ifndef ti_devices_DeviceFamily__include
#define ti_devices_DeviceFamily__include
#ifdef __cplusplus
extern "C" {
#endif
/*
* DeviceFamily_ID_XYZ values.
*
* DeviceFamily_ID may be used in the preprocessor for conditional compilation.
* DeviceFamily_ID is set to one of these values based on the top level
* DeviceFamily_XYZ define.
*/
#define DeviceFamily_ID_CC13X0 1
#define DeviceFamily_ID_CC13X2 2
#define DeviceFamily_ID_CC26X0 3
#define DeviceFamily_ID_CC26X0R2 4
#define DeviceFamily_ID_CC26X2 5
#define DeviceFamily_ID_CC3200 6
#define DeviceFamily_ID_CC3220 7
#define DeviceFamily_ID_MSP432P401x 8
#define DeviceFamily_ID_MSP432P4x1xI 9
#define DeviceFamily_ID_MSP432P4x1xT 10
#define DeviceFamily_ID_MSP432E4 11
/*
* DeviceFamily_PARENT_XYZ values.
*
* DeviceFamily_PARENT may be used in the preprocessor for conditional
* compilation. DeviceFamily_PARENT is set to one of these values based
* on the top-level DeviceFamily_XYZ define.
*/
#define DeviceFamily_PARENT_CC13X0_CC26X0 1
#define DeviceFamily_PARENT_CC13X2_CC26X2 2
#define DeviceFamily_PARENT_MSP432P401R 3
#define DeviceFamily_PARENT_MSP432P4111 4
/*
* Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and
* DeviceFamily_PARENT based on the DeviceFamily_XYZ define.
* If DeviceFamily_XYZ is undefined, a compiler error is thrown. If
* multiple DeviceFamily_XYZ are defined, the first one encountered is used.
*/
#if defined(DeviceFamily_CC13X0)
#define DeviceFamily_ID DeviceFamily_ID_CC13X0
#define DeviceFamily_DIRECTORY cc13x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC13X2)
#define DeviceFamily_ID DeviceFamily_ID_CC13X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC26X0)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0
#define DeviceFamily_DIRECTORY cc26x0
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X0R2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X0R2
#define DeviceFamily_DIRECTORY cc26x0r2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0
#elif defined(DeviceFamily_CC26X2)
#define DeviceFamily_ID DeviceFamily_ID_CC26X2
#define DeviceFamily_DIRECTORY cc13x2_cc26x2
#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2
#elif defined(DeviceFamily_CC3200)
#define DeviceFamily_ID DeviceFamily_ID_CC3200
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_CC3220)
#define DeviceFamily_ID DeviceFamily_ID_CC3220
#define DeviceFamily_DIRECTORY cc32xx
#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P401x
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R
#if !defined(__MSP432P401R__)
#define __MSP432P401R__
#endif
#elif defined(DeviceFamily_MSP432P4x1xI)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432P4x1xT)
#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT
#define DeviceFamily_DIRECTORY msp432p4xx
#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111
#if !defined(__MSP432P4111__)
#define __MSP432P4111__
#endif
#elif defined(DeviceFamily_MSP432E4)
#define DeviceFamily_ID DeviceFamily_ID_MSP432E4
#define DeviceFamily_DIRECTORY msp432e4
#if !defined(__MSP432E401Y__)
#define __MSP432E401Y__
#endif
#else
#error "DeviceFamily_XYZ undefined. You must defined DeviceFamily_XYZ!"
#endif
/*!
* @brief Macro to include correct driverlib path.
*
* @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined
* first.
*
* @param x A token containing the path of the file to include based on
* the root device folder. The preceding forward slash must be
* omitted. For example:
* - #include DeviceFamily_constructPath(inc/hw_memmap.h)
* - #include DeviceFamily_constructPath(driverlib/ssi.h)
*
* @return Returns an include path.
*
*/
#define DeviceFamily_constructPath(x) <ti/devices/DeviceFamily_DIRECTORY/x>
#ifdef __cplusplus
}
#endif
#endif /* ti_devices_DeviceFamily__include */

693
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.c Executable file
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@ -0,0 +1,693 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// adc.c
//
// Driver for the ADC module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup ADC_Analog_to_Digital_Converter_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_adc.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "adc.h"
//*****************************************************************************
//
//! Enables the ADC
//!
//! \param ulBase is the base address of the ADC
//!
//! This function sets the ADC global enable
//!
//! \return None.
//
//*****************************************************************************
void ADCEnable(unsigned long ulBase)
{
//
// Set the global enable bit in the control register.
//
HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1;
}
//*****************************************************************************
//
//! Disable the ADC
//!
//! \param ulBase is the base address of the ADC
//!
//! This function clears the ADC global enable
//!
//! \return None.
//
//*****************************************************************************
void ADCDisable(unsigned long ulBase)
{
//
// Clear the global enable bit in the control register.
//
HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ;
}
//*****************************************************************************
//
//! Enables specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function enables specified ADC channel and configures the
//! pin as analog pin.
//!
//! \return None.
//
//*****************************************************************************
void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulCh;
ulCh = (ulChannel == ADC_CH_0)? 0x02 :
(ulChannel == ADC_CH_1)? 0x04 :
(ulChannel == ADC_CH_2)? 0x08 : 0x10;
HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh;
}
//*****************************************************************************
//
//! Disables specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channelsber
//!
//! This function disables specified ADC channel.
//!
//! \return None.
//
//*****************************************************************************
void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulCh;
ulCh = (ulChannel == ADC_CH_0)? 0x02 :
(ulChannel == ADC_CH_1)? 0x04 :
(ulChannel == ADC_CH_2)? 0x08 : 0x10;
HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh;
}
//*****************************************************************************
//
//! Enables and registers ADC interrupt handler for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param pfnHandler is a pointer to the function to be called when the
//! ADC channel interrupt occurs.
//!
//! This function enables and registers ADC interrupt handler for specified
//! channel. Individual interrupt for each channel should be enabled using
//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear
//! the interrupt source.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
void (*pfnHandler)(void))
{
unsigned long ulIntNo;
//
// Get the interrupt number associted with the specified channel
//
ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
(ulChannel == ADC_CH_1)? INT_ADCCH1 :
(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
//
// Register the interrupt handler
//
IntRegister(ulIntNo,pfnHandler);
//
// Enable ADC interrupt
//
IntEnable(ulIntNo);
}
//*****************************************************************************
//
//! Disables and unregisters ADC interrupt handler for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function disables and unregisters ADC interrupt handler for specified
//! channel. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulIntNo;
//
// Get the interrupt number associted with the specified channel
//
ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 :
(ulChannel == ADC_CH_1)? INT_ADCCH1 :
(ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3;
//
// Disable ADC interrupt
//
IntDisable(ulIntNo);
//
// Unregister the interrupt handler
//
IntUnregister(ulIntNo);
}
//*****************************************************************************
//
//! Enables individual interrupt sources for specified channel
//!
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//! - \b ADC_DMA_DONE for DMA done
//! - \b ADC_FIFO_OVERFLOW for FIFO over flow
//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow
//! - \b ADC_FIFO_EMPTY for FIFO empty
//! - \b ADC_FIFO_FULL for FIFO full
//!
//! \return None.
//
//*****************************************************************************
void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Enable DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk;
}
ulIntFlags = ulIntFlags & 0x0F;
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
//
// Unmask the specified interrupts
//
HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf);
}
//*****************************************************************************
//
//! Disables individual interrupt sources for specified channel
//!
//!
//! \param ulBase is the base address of the ADC.
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function disables the indicated ADC interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The parameters\e ulIntFlags and \e ulChannel should be as explained in
//! ADCIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Disable DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk;
}
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_en + ulChannel;
//
// Unmask the specified interrupts
//
HWREG(ulBase + ulOffset) &= ~ulIntFlags;
}
//*****************************************************************************
//
//! Gets the current channel interrupt status
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function returns the interrupt status of the specified ADC channel.
//!
//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
//!
//! \return Return the ADC channel interrupt status, enumerated as a bit
//! field of values described in ADCIntEnable()
//
//*****************************************************************************
unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
unsigned long ulIntStatus;
//
// Get DMA Done interrupt status
//
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
ulIntStatus = HWREG(APPS_CONFIG_BASE +
APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk;
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
//
// Read ADC interrupt status
//
ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf;
//
// Return the current interrupt status
//
return(ulIntStatus);
}
//*****************************************************************************
//
//! Clears the current channel interrupt sources
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//!
//! This function clears individual interrupt source for the specified
//! ADC channel.
//!
//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags)
{
unsigned long ulOffset;
unsigned long ulDmaMsk;
//
// Clear DMA Done interrupt
//
if(ulIntFlags & ADC_DMA_DONE)
{
ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000:
(ulChannel == ADC_CH_1)?0x00002000:
(ulChannel == ADC_CH_2)?0x00004000:0x00008000;
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk;
}
//
// Get the interrupt enable register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_irq_status + ulChannel;
//
// Clear the specified interrupts
//
HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE));
}
//*****************************************************************************
//
//! Enables the ADC DMA operation for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function enables the DMA operation for specified ADC channel
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulBitMask;
//
// Get the bit mask for enabling DMA for specified channel
//
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
(ulChannel == ADC_CH_1)?0x04:
(ulChannel == ADC_CH_2)?0x10:0x40;
//
// Enable DMA request for the specified channel
//
HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask;
}
//*****************************************************************************
//
//! Disables the ADC DMA operation for specified channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels
//!
//! This function disables the DMA operation for specified ADC channel
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \return None.
//
//*****************************************************************************
void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulBitMask;
//
// Get the bit mask for disabling DMA for specified channel
//
ulBitMask = (ulChannel == ADC_CH_0)?0x01:
(ulChannel == ADC_CH_1)?0x04:
(ulChannel == ADC_CH_2)?0x10:0x40;
//
// Disable DMA request for the specified channel
//
HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask;
}
//*****************************************************************************
//
//! Configures the ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//! \param ulValue is wrap arround value of the timer
//!
//! This function Configures the ADC internal timer. The ADC timer is a 17 bit
//! used to timestamp the ADC data samples internally.
//! User can read the timestamp along with the sample from the FIFO register(s).
//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp
//!
//! The parameter \e ulValue can take any value between 0 - 2^17
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue)
{
unsigned long ulReg;
//
// Read the currrent config
//
ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration);
//
// Mask and set timer count field
//
ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF));
//
// Set the timer count value
//
HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg;
}
//*****************************************************************************
//
//! Resets ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function resets 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerReset(unsigned long ulBase)
{
//
// Reset the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24);
}
//*****************************************************************************
//
//! Enables ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function enables 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerEnable(unsigned long ulBase)
{
//
// Enable the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25);
}
//*****************************************************************************
//
//! Disables ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function disables 17-bit ADC internal timer
//!
//! \returns None.
//
//*****************************************************************************
void ADCTimerDisable(unsigned long ulBase)
{
//
// Disable the timer
//
HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25);
}
//*****************************************************************************
//
//! Gets the current value of ADC internal timer
//!
//! \param ulBase is the base address of the ADC
//!
//! This function the current value of 17-bit ADC internal timer
//!
//! \returns Return the current value of ADC internal timer.
//
//*****************************************************************************
unsigned long ADCTimerValueGet(unsigned long ulBase)
{
return(HWREG(ulBase + ADC_O_adc_timer_current_count));
}
//*****************************************************************************
//
//! Gets the current FIFO level for specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels.
//!
//! This function returns the current FIFO level for specified ADC channel.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \returns Return the current FIFO level for specified channel
//
//*****************************************************************************
unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
//
// Get the fifo level register offset for specified channel
//
ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel;
//
// Return FIFO level
//
return(HWREG(ulBase + ulOffset) & 0x7);
}
//*****************************************************************************
//
//! Reads FIFO for specified ADC channel
//!
//! \param ulBase is the base address of the ADC
//! \param ulChannel is one of the valid ADC channels.
//!
//! This function returns one data sample from the channel fifo as specified by
//! \e ulChannel parameter.
//!
//! The parameter \e ulChannel should be one of the following
//!
//! - \b ADC_CH_0 for channel 0
//! - \b ADC_CH_1 for channel 1
//! - \b ADC_CH_2 for channel 2
//! - \b ADC_CH_3 for channel 3
//!
//! \returns Return one data sample from the channel fifo.
//
//*****************************************************************************
unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel)
{
unsigned long ulOffset;
//
// Get the fifo register offset for specified channel
//
ulOffset = ADC_O_channel0FIFODATA + ulChannel;
//
// Return FIFO level
//
return(HWREG(ulBase + ulOffset));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// adc.h
//
// Defines and Macros for the ADC.
//
//*****************************************************************************
#ifndef __ADC_H__
#define __ADC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to APIs as ulChannel parameter
//*****************************************************************************
#define ADC_CH_0 0x00000000
#define ADC_CH_1 0x00000008
#define ADC_CH_2 0x00000010
#define ADC_CH_3 0x00000018
//*****************************************************************************
//
// Values that can be passed to ADCIntEnable(), ADCIntDisable()
// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus()
//
//*****************************************************************************
#define ADC_DMA_DONE 0x00000010
#define ADC_FIFO_OVERFLOW 0x00000008
#define ADC_FIFO_UNDERFLOW 0x00000004
#define ADC_FIFO_EMPTY 0x00000002
#define ADC_FIFO_FULL 0x00000001
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void ADCEnable(unsigned long ulBase);
extern void ADCDisable(unsigned long ulBase);
extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel,
void (*pfnHandler)(void));
extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel);
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel);
extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulIntFlags);
extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel);
extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue);
extern void ADCTimerEnable(unsigned long ulBase);
extern void ADCTimerDisable(unsigned long ulBase);
extern void ADCTimerReset(unsigned long ulBase);
extern unsigned long ADCTimerValueGet(unsigned long ulBase);
extern unsigned char ADCFIFOLvlGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long ADCFIFORead(unsigned long ulBase,
unsigned long ulChannel);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __ADC_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// aes.h
//
// Defines and Macros for the AES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_AES_H__
#define __DRIVERLIB_AES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the operation direction in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_DIR_ENCRYPT 0x00000004
#define AES_CFG_DIR_DECRYPT 0x00000000
//*****************************************************************************
//
// The following defines are used to specify the key size in the ui32Config
// argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_KEY_SIZE_128BIT 0x00000008
#define AES_CFG_KEY_SIZE_192BIT 0x00000010
#define AES_CFG_KEY_SIZE_256BIT 0x00000018
//*****************************************************************************
//
// The following defines are used to specify the mode of operation in the
// ui32Config argument in the AESConfig function. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_MODE_M 0x2007fe60
#define AES_CFG_MODE_ECB 0x00000000
#define AES_CFG_MODE_CBC 0x00000020
#define AES_CFG_MODE_CTR 0x00000040
#define AES_CFG_MODE_ICM 0x00000200
#define AES_CFG_MODE_CFB 0x00000400
#define AES_CFG_MODE_XTS_TWEAKJL \
0x00000800
#define AES_CFG_MODE_XTS_K2IJL \
0x00001000
#define AES_CFG_MODE_XTS_K2ILJ0 \
0x00001800
#define AES_CFG_MODE_F8 0x00002000
#define AES_CFG_MODE_F9 0x20004000
#define AES_CFG_MODE_CBCMAC 0x20008000
#define AES_CFG_MODE_GCM_HLY0ZERO \
0x20010040
#define AES_CFG_MODE_GCM_HLY0CALC \
0x20020040
#define AES_CFG_MODE_GCM_HY0CALC \
0x20030040
#define AES_CFG_MODE_CCM 0x20040040
//*****************************************************************************
//
// The following defines are used to specify the counter width in the
// ui32Config argument in the AESConfig function. It is only required to
// be defined when using CTR, CCM, or GCM modes. Only one length is permitted.
//
//*****************************************************************************
#define AES_CFG_CTR_WIDTH_32 0x00000000
#define AES_CFG_CTR_WIDTH_64 0x00000080
#define AES_CFG_CTR_WIDTH_96 0x00000100
#define AES_CFG_CTR_WIDTH_128 0x00000180
//*****************************************************************************
//
// The following defines are used to define the width of the length field for
// CCM operation through the ui32Config argument in the AESConfig function.
// This value is also known as L. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_L_2 0x00080000
#define AES_CFG_CCM_L_4 0x00180000
#define AES_CFG_CCM_L_8 0x00380000
//*****************************************************************************
//
// The following defines are used to define the length of the authentication
// field for CCM operations through the ui32Config argument in the AESConfig
// function. This value is also known as M. Only one is permitted.
//
//*****************************************************************************
#define AES_CFG_CCM_M_4 0x00400000
#define AES_CFG_CCM_M_6 0x00800000
#define AES_CFG_CCM_M_8 0x00c00000
#define AES_CFG_CCM_M_10 0x01000000
#define AES_CFG_CCM_M_12 0x01400000
#define AES_CFG_CCM_M_14 0x01800000
#define AES_CFG_CCM_M_16 0x01c00000
//*****************************************************************************
//
// Interrupt flags for use with the AESIntEnable, AESIntDisable, and
// AESIntStatus functions.
//
//*****************************************************************************
#define AES_INT_CONTEXT_IN 0x00000001
#define AES_INT_CONTEXT_OUT 0x00000008
#define AES_INT_DATA_IN 0x00000002
#define AES_INT_DATA_OUT 0x00000004
#define AES_INT_DMA_CONTEXT_IN 0x00010000
#define AES_INT_DMA_CONTEXT_OUT 0x00020000
#define AES_INT_DMA_DATA_IN 0x00040000
#define AES_INT_DMA_DATA_OUT 0x00080000
//*****************************************************************************
//
// Defines used when enabling and disabling DMA requests in the
// AESEnableDMA and AESDisableDMA functions.
//
//*****************************************************************************
#define AES_DMA_DATA_IN 0x00000040
#define AES_DMA_DATA_OUT 0x00000020
#define AES_DMA_CONTEXT_IN 0x00000080
#define AES_DMA_CONTEXT_OUT 0x00000100
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key,
uint32_t ui32Keysize);
extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key);
extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData);
extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length);
extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest,
uint32_t ui32Length);
extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src,
uint32_t ui32Length,
uint8_t *pui8Tag);
extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length,
uint8_t *pui8AuthSrc, uint32_t ui32AuthLength,
uint8_t *pui8Tag);
extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked);
extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern void AESIntUnregister(uint32_t ui32Base);
extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_AES_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// camera.c
//
// Driver for the camera controller module
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup camera_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_camera.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "camera.h"
//******************************************************************************
//
//! Resets the Camera core
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function resets the camera core
//!
//! \return None.
//
//******************************************************************************
void CameraReset(unsigned long ulBase)
{
//
// Reset the camera
//
HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET;
//
// Wait for reset completion
//
while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)&
CAMERA_CC_SYSSTATUS_RESET_DONE2))
{
}
}
//******************************************************************************
//
//! Configures camera parameters
//!
//! \param ulBase is the base address of the camera module.
//! \param ulHSPol sets the HSync polarity
//! \param ulVSPol sets the VSync polarity
//! \param ulFlags are configuration flags
//!
//! This function sets different camera parameters.
//!
//! The parameter \e ulHSPol should be on the follwoing:
//! - \b CAM_HS_POL_HI
//! - \b CAM_HS_POL_LO
//!
//! The parameter \e ulVSPol should be on the follwoing:
//! - \b CAM_VS_POL_HI
//! - \b CAM_VS_POL_LO
//!
//! The parameter \e ulFlags can be logical OR of one or more of the follwoing
//! or 0:
//! - \b CAM_PCLK_RISE_EDGE
//! - \b CAM_PCLK_FALL_EDGE
//! - \b CAM_ORDERCAM_SWAP
//! - \b CAM_NOBT_SYNCHRO
//! - \b CAM_IF_SYNCHRO
//!
//! \return None.
//
//******************************************************************************
void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol,
unsigned long ulVSPol, unsigned long ulFlags)
{
unsigned long ulReg;
//
// Read the register
//
ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL);
//
// Set the requested parameter
//
ulFlags = (ulFlags|ulHSPol|ulVSPol);
ulReg = ((ulReg & ~(CAMERA_CC_CTRL_NOBT_SYNCHRO |
CAMERA_CC_CTRL_NOBT_HS_POL |
CAMERA_CC_CTRL_NOBT_VS_POL |
CAMERA_CC_CTRL_BT_CORRECT |
CAMERA_CC_CTRL_PAR_ORDERCAM |
CAMERA_CC_CTRL_PAR_CLK_POL )) | ulFlags);
//
// Write the configuration
//
HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg;
}
//******************************************************************************
//
//! Set the internal clock divider
//!
//! \param ulBase is the base address of the camera module.
//! \param ulCamClkIn is input to camera module
//! \param ulXClk defines the output required
//!
//! This function sets the internal clock divider based on \e ulCamClkIn to
//! generate XCLK as specified be \e ulXClk. Maximum suppoter division is 30
//!
//! \return None.
//
//******************************************************************************
void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn,
unsigned long ulXClk)
{
unsigned long ulReg;
unsigned long ucDiv;
//
// Read the register
//
ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK);
//
// Mask XCLK divider value
//
ulReg &= ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M);
//
// Compute the divider
//
ucDiv = ((ulCamClkIn)/ulXClk);
//
// Max supported division is 30
//
if(ucDiv > 30)
{
return;
}
//
// Set and write back the configuration
//
ulReg |= ucDiv;
HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg;
}
//******************************************************************************
//
//! Sets the internal divide in specified mode
//!
//! \param ulBase is the base address of the camera module.
//! \param bXClkFlags decides the divide mode
//!
//! This function sets the internal divide in specified mode.
//!
//! The parameter \e bXClkFlags should be one of the following :
//!
//! - \b CAM_XCLK_STABLE_LO
//! - \b CAM_XCLK_STABLE_HI
//! - \b CAM_XCLK_DIV_BYPASS
//!
//! \return None.
//
//******************************************************************************
void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags)
{
unsigned long ulReg;
//
// Read and Mask XTAL Divider config.
//
ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) &
~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M));
//
// Set config. base on parameter flag
//
switch(bXClkFlags)
{
case CAM_XCLK_STABLE_HI : ulReg |= 0x00000001;
break;
case CAM_XCLK_DIV_BYPASS: ulReg |= 0x0000001F;
break;
}
//
// Write the config.
//
HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg;
}
//******************************************************************************
//
//! Enable camera DMA
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function enables transfer request to DMA from camera. DMA specific
//! configuration has to be done seperately.
//!
//! \return None.
//
//******************************************************************************
void CameraDMAEnable(unsigned long ulBase)
{
//
// Enable DMA
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN;
}
//******************************************************************************
//
//! Disable camera DMA
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function masks transfer request to DMA from camera.
//!
//! \return None.
//
//******************************************************************************
void CameraDMADisable(unsigned long ulBase)
{
//
// Disable DMA
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN;
}
//******************************************************************************
//
//! Sets the FIFO threshold for DMA transfer request
//!
//! \param ulBase is the base address of the camera module.
//! \param ulThreshold specifies the FIFO threshold
//!
//! This function sets the FIFO threshold for DMA transfer request.
//! Parameter \e ulThreshold can range from 1 - 64
//!
//! \return None.
//
//******************************************************************************
void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold)
{
//
// Read and Mask DMA threshold field
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M;
//
// Write the new threshold value
//
HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= (ulThreshold -1);
}
//******************************************************************************
//
//! Register camera interrupt handler
//!
//! \param ulBase is the base address of the camera module.
//! \param pfnHandler hold pointer to interrupt handler
//!
//! This function registers and enables global camera interrupt from the
//! interrupt controller. Individual camera interrupts source
//! should be enabled using \sa CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_CAMERA, pfnHandler);
//
// Enable the Camera interrupt.
//
IntEnable(INT_CAMERA);
}
//******************************************************************************
//
//! Un-Register camera interrupt handler
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function unregisters and disables global camera interrupt from the
//! interrupt controller.
//!
//! \return None.
//
//******************************************************************************
void CameraIntUnregister(unsigned long ulBase)
{
//
// Disable the interrupt.
//
IntDisable(INT_CAMERA);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_CAMERA);
}
//******************************************************************************
//! Enables individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! This function enables individual camera interrupt sources.
//!
//! the parameter \e ulIntFlags should be logical OR of one or more of the
//! following:
//!
//! - \b CAM_INT_DMA
//! - \b CAM_INT_FE
//! - \b CAM_INT_FSC_ERR
//! - \b CAM_INT_FIFO_NOEMPTY
//! - \b CAM_INT_FIFO_FULL
//! - \b CAM_INT_FIFO_THR
//! - \b CAM_INT_FIFO_OF
//! - \b CAN_INT_FIFO_UR
//!
//! \return None.
//
//******************************************************************************
void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// unmask Camera DMA done interrupt
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ((1<<8));
}
//
// Enable specific camera interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQENABLE) |= ulIntFlags;
}
//******************************************************************************
//! Disables individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! This function disables individual camera interrupt sources.
//!
//! The parameter \e ulIntFlags should be logical OR of one or more of the
//! values as defined in CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Mask Camera DMA done interrupt
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ((1<<8));
}
//
// Disable specific camera interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQENABLE) &= ~ulIntFlags;
}
//******************************************************************************
//
//! Returns the current interrupt status,
//!
//! \param ulBase is the base address of the camera module.
//! \param ulBase is the base address of the camera module.
//!
//! This functions returns the current interrupt status for the camera.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in CameraIntEnable().
//******************************************************************************
unsigned long CameraIntStatus(unsigned long ulBase)
{
unsigned ulIntFlag;
//
// Read camera interrupt
//
ulIntFlag = HWREG(ulBase + CAMERA_O_CC_IRQSTATUS);
//
//
// Read camera DMA doner interrupt
//
if(HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED) & (1<<8))
{
ulIntFlag |= CAM_INT_DMA;
}
//
// Return status
//
return(ulIntFlag);
}
//******************************************************************************
//! Clears individual camera interrupt sources.
//!
//! \param ulBase is the base address of the camera module.
//! \param ulIntFlags is the bit mask of the interrupt sources to be Clears.
//!
//! This function Clears individual camera interrupt sources.
//!
//! The parameter \e ulIntFlags should be logical OR of one or more of the
//! values as defined in CameraIntEnable().
//!
//! \return None.
//
//******************************************************************************
void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags)
{
//
// Clear DMA done int status
//
if(ulIntFlags & CAM_INT_DMA)
{
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ((1<<8));
}
//
// Clear the interrupts
//
HWREG(ulBase + CAMERA_O_CC_IRQSTATUS) = ulIntFlags;
}
//******************************************************************************
//
//! Starts image capture
//!
//! \param ulBase is the base address of the camera module.
//!
//! This function starts the image capture over the configured camera interface
//! This function should be called after configuring the camera module
//! completele
//!
//! \return None.
//
//******************************************************************************
void CameraCaptureStart(unsigned long ulBase)
{
//
// Set the mode
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~0xF;
//
// Enable image capture
//
HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_EN;
}
//******************************************************************************
//
//! Stops image capture
//!
//! \param ulBase is the base address of the camera module.
//! \param bImmediate is \b true to stop capture imeediately else \b flase.
//!
//! This function stops the image capture over the camera interface.
//! The capture is stopped either immediatelt or at the end of current frame
//! based on \e bImmediate parameter.
//!
//! \return None.
//
//******************************************************************************
void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate)
{
if(bImmediate)
{
//
// Stop capture immediately
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_FRAME_TRIG;
}
else
{
//
// Stop capture at the end of frame
//
HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_FRAME_TRIG;
}
//
// Request camera to stop capture
//
HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_EN;
}
//******************************************************************************
//
//! Reads the camera buffer (FIFO)
//!
//! \param ulBase is the base address of the camera module.
//! \param pBuffer is the pointer to the read buffer
//! \param ucSize specifies the size to data to be read
//!
//! This function reads the camera buffer (FIFO).
//!
//! \return None.
//
//******************************************************************************
void CameraBufferRead(unsigned long ulBase, unsigned long *pBuffer,
unsigned char ucSize)
{
unsigned char *pCamBuff;
unsigned char i;
//
// Initilize a pointer to ecamera buffer
//
pCamBuff = (unsigned char *)CAM_BUFFER_ADDR;
//
// Read out requested data
//
for(i=0; i < ucSize; i++)
{
*(pBuffer+i) = *(pCamBuff + i);
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// camera.h
//
// Prototypes and macros for the camera controller module.
//
//*****************************************************************************
#ifndef __CAMERA_H__
#define __CAMERA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Macro defining Camera buffer address
//*****************************************************************************
#define CAM_BUFFER_ADDR 0x44018100
//*****************************************************************************
// Value that can be passed to CameraXClkSet().
//*****************************************************************************
#define CAM_XCLK_STABLE_LO 0x00
#define CAM_XCLK_STABLE_HI 0x01
#define CAM_XCLK_DIV_BYPASS 0x02
//*****************************************************************************
// Value that can be passed to CameraIntEnable(), CameraIntDisable,
// CameraIntClear() or returned from CameraIntStatus().
//*****************************************************************************
#define CAM_INT_DMA 0x80000000
#define CAM_INT_FE 0x00010000
#define CAM_INT_FIFO_NOEMPTY 0x00000010
#define CAM_INT_FIFO_FULL 0x00000008
#define CAM_INT_FIFO_THR 0x00000004
#define CAM_INT_FIFO_OF 0x00000002
#define CAN_INT_FIFO_UR 0x00000001
//*****************************************************************************
// Value that can be passed to CameraXClkConfig().
//*****************************************************************************
#define CAM_HS_POL_HI 0x00000000
#define CAM_HS_POL_LO 0x00000200
#define CAM_VS_POL_HI 0x00000000
#define CAM_VS_POL_LO 0x00000100
#define CAM_PCLK_RISE_EDGE 0x00000000
#define CAM_PCLK_FALL_EDGE 0x00000400
#define CAM_ORDERCAM_SWAP 0x00000800
#define CAM_NOBT_SYNCHRO 0x00002000
#define CAM_IF_SYNCHRO 0x00080000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void CameraReset(unsigned long ulBase);
extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol,
unsigned long ulVSPol, unsigned long ulFlags);
extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn,
unsigned long ulXClk);
extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags);
extern void CameraDMAEnable(unsigned long ulBase);
extern void CameraDMADisable(unsigned long ulBase);
extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold);
extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void CameraIntUnregister(unsigned long ulBase);
extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long CameraIntStatus(unsigned long ulBase);
extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate);
extern void CameraCaptureStart(unsigned long ulBase);
extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer,
unsigned char ucSize);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__CAMERA_H__

413
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// cpu.c
//
// Instruction wrappers for special CPU instructions needed by the
//
//
//*****************************************************************************
#include "cpu.h"
//*****************************************************************************
//
// Wrapper function for the CPSID instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsid(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUcpsid(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" dsb \n"
" isb \n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function returning the state of PRIMASK (indicating whether
// interrupts are enabled or disabled).
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUprimask(void)
{
unsigned long ulRet;
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUprimask(void)
{
//
// Read PRIMASK and disable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK
// on entry.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUcpsie(void)
{
unsigned long ulRet;
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUcpsie(void)
{
//
// Read PRIMASK and enable interrupts.
//
__asm(" mrs r0, PRIMASK\n"
" cpsie i\n"
" dsb \n"
" isb \n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif
//*****************************************************************************
//
// Wrapper function for the WFI instruction.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n");
}
#endif
#if defined(ccs)
void
CPUwfi(void)
{
//
// Wait for the next interrupt.
//
__asm(" dsb \n"
" isb \n"
" wfi \n");
}
#endif
//*****************************************************************************
//
// Wrapper function for writing the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
void __attribute__((naked))
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n"
" bx lr\n");
}
#endif
#if defined(ewarm)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n");
}
#endif
#if defined(ccs)
void
CPUbasepriSet(unsigned long ulNewBasepri)
{
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" dsb \n"
" isb \n");
}
#endif
//*****************************************************************************
//
// Wrapper function for reading the BASEPRI register.
//
//*****************************************************************************
#if defined(gcc)
unsigned long __attribute__((naked))
CPUbasepriGet(void)
{
unsigned long ulRet;
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n"
: "=r" (ulRet));
//
// The return is handled in the inline assembly, but the compiler will
// still complain if there is not an explicit return here (despite the fact
// that this does not result in any code being produced because of the
// naked attribute).
//
return(ulRet);
}
#endif
#if defined(ewarm)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n");
//
// "Warning[Pe940]: missing return statement at end of non-void function"
// is suppressed here to avoid putting a "bx lr" in the inline assembly
// above and a superfluous return statement here.
//
#pragma diag_suppress=Pe940
}
#pragma diag_default=Pe940
#endif
#if defined(ccs)
unsigned long
CPUbasepriGet(void)
{
//
// Read BASEPRI
//
__asm(" mrs r0, BASEPRI\n"
" bx lr\n");
//
// The following keeps the compiler happy, because it wants to see a
// return value from this function. It will generate code to return
// a zero. However, the real return is the "bx lr" above, so the
// return(0) is never executed and the function returns with the value
// you expect in R0.
//
return(0);
}
#endif

0
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// crc.c
//
// Driver for the CRC module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup CRC_Cyclic_Redundancy_Check_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_dthe.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/crc.h"
#include "driverlib/debug.h"
//*****************************************************************************
//
//! Set the configuration of CRC functionality with the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32CRCConfig is the configuration of the CRC engine.
//!
//! This function configures the operation of the CRC engine within the EC
//! module. The configuration is specified with the \e ui32CRCConfig argument.
//! It is the logical OR of any of the following options:
//!
//! CRC Initialization Value
//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value
//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s'
//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s'
//!
//! Input Data Size
//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits
//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits
//!
//! Post Process Reverse/Inverse
//! - \b EC_CRC_CFG_RESINV - Result inverse enable
//! - \b EC_CRC_CFG_OBR - Output reverse enable
//!
//! Input Bit Reverse
//! - \b EC_CRC_CFG_IBR - Bit reverse enable
//!
//! Endian Control
//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word
//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word
//!
//! Operation Type
//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005
//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021
//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7
//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41
//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum
//!
//! \return None.
//
//*****************************************************************************
void
CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) ||
(ui32CRCConfig & CRC_CFG_INIT_0) ||
(ui32CRCConfig & CRC_CFG_INIT_1) ||
(ui32CRCConfig & CRC_CFG_SIZE_8BIT) ||
(ui32CRCConfig & CRC_CFG_SIZE_32BIT) ||
(ui32CRCConfig & CRC_CFG_RESINV) ||
(ui32CRCConfig & CRC_CFG_OBR) ||
(ui32CRCConfig & CRC_CFG_IBR) ||
(ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) ||
(ui32CRCConfig & CRC_CFG_ENDIAN_SHW) ||
(ui32CRCConfig & CRC_CFG_TYPE_P8005) ||
(ui32CRCConfig & CRC_CFG_TYPE_P1021) ||
(ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) ||
(ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) ||
(ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM));
//
// Write the control register with the configuration.
//
HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig;
}
//*****************************************************************************
//
//! Write the seed value for CRC operations in the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32Seed is the seed value.
//!
//! This function writes the seed value for use with CRC operations in the
//! EC module. This value is the start value for CRC operations. If this
//! value is not written, then the residual seed from the previous operation
//! is used as the starting value.
//!
//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is
//! set with the CRCConfigSet() function.
//
//*****************************************************************************
void
CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// Write the seed value to the seed register.
//
HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed;
}
//*****************************************************************************
//
//! Write data into the EC module for CRC operations.
//!
//! \param ui32Base is the base address of the EC module.
//! \param ui32Data is the data to be written.
//!
//! This function writes either 8 or 32 bits of data into the EC module for
//! CRC operations. The distinction between 8 and 32 bits of data is made
//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag
//! is set using the CRCConfigSet() function.
//!
//! When writing 8 bits of data, ensure the data is in the least signficant
//! byte position. The remaining bytes should be written with zero. For
//! example, when writing 0xAB, \e ui32Data should be 0x000000AB.
//!
//! \return None
//
//*****************************************************************************
void
CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// Write the data
//
HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data;
}
//*****************************************************************************
//
//! Reads the result of a CRC operation in the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//!
//! This function reads either the unmodified CRC result or the post
//! processed CRC result from the EC module. The post-processing options
//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR
//! parameters in the CRCConfigSet() function.
//!
//! \return The CRC result.
//
//*****************************************************************************
uint32_t
CRCResultRead(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// return value.
//
return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP));
}
//*****************************************************************************
//
//! Process data to generate a CRC with the EC module.
//!
//! \param ui32Base is the base address of the EC module.
//! \param puiDataIn is a pointer to an array of data that is processed.
//! \param ui32DataLength is the number of data items that are processed
//! to produce the CRC.
//! \param ui32Config the config parameter to determine the CRC mode
//!
//! This function processes an array of data to produce a CRC result.
//! This function takes the CRC mode as the parameter.
//!
//! The data in the array pointed to be \e pui32DataIn is either an array
//! of bytes or an array or words depending on the selection of the input
//! data size options \b EC_CRC_CFG_SIZE_8BIT and
//! \b EC_CRC_CFG_SIZE_32BIT.
//!
//! This function returns either the unmodified CRC result or the
//! post- processed CRC result from the EC module. The post-processing
//! options are selectable through \b EC_CRC_CFG_RESINV and
//! \b EC_CRC_CFG_OBR parameters.
//!
//! \return The CRC result.
//
//*****************************************************************************
uint32_t
CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
uint32_t ui32DataLength, uint32_t ui32Config)
{
uint8_t *pui8DataIn;
uint32_t *pui32DataIn;
//
// Check the arguments.
//
ASSERT(ui32Base == DTHE_BASE);
//
// See if the CRC is operating in 8-bit or 32-bit mode.
//
if(ui32Config & DTHE_CRC_CTRL_SIZE)
{
//
// The CRC is operating in 8-bit mode, so create an 8-bit pointer to
// the data.
//
pui8DataIn = (uint8_t *)puiDataIn;
//
// Loop through the input data.
//
while(ui32DataLength--)
{
//
// Write the next data byte.
//
HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++;
}
}
else
{
//
// The CRC is operating in 32-bit mode, so loop through the input data.
//
pui32DataIn = (uint32_t *)puiDataIn;
while(ui32DataLength--)
{
//
// Write the next data word.
//
HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++;
}
}
//
// Return the result.
//
return(CRCResultRead(ui32Base));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// crc.h
//
// Defines and Macros for CRC module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_CRC_H__
#define __DRIVERLIB_CRC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used in the ui32Config argument of the
// ECConfig function.
//
//*****************************************************************************
#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed
#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s'
#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s'
#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size
#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size
#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable
#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable
#define CRC_CFG_IBR 0x00000080 // Bit reverse enable
#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word
#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word
#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005
#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021
#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7
#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41
#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum
//*****************************************************************************
//
// Function prototypes.
//
//*****************************************************************************
extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig);
extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn,
uint32_t ui32DataLength, uint32_t ui32Config);
extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data);
extern uint32_t CRCResultRead(uint32_t ui32Base);
extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_CRC_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/debug.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// debug.h
//
// Macros for assisting debug of the driver library.
//
//*****************************************************************************
#ifndef __DEBUG_H__
#define __DEBUG_H__
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build.
//
//*****************************************************************************
extern void __error__(char *pcFilename, unsigned long ulLine);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#define ASSERT(expr) \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
#else
#define ASSERT(expr)
#endif
#endif // __DEBUG_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// des.c
//
// Driver for the DES data transformation.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup DES_Data_Encryption_Standard_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_des.h"
#include "inc/hw_dthe.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "des.h"
#include "interrupt.h"
//*****************************************************************************
//
//! Configures the DES module for operation.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Config is the configuration of the DES module.
//!
//! This function configures the DES module for operation.
//!
//! The \e ui32Config parameter is a bit-wise OR of a number of configuration
//! flags. The valid flags are grouped below based on their function.
//!
//! The direction of the operation is specified with one of the following two
//! flags. Only one is permitted.
//!
//! - \b DES_CFG_DIR_ENCRYPT - Encryption
//! - \b DES_CFG_DIR_DECRYPT - Decryption
//!
//! The operational mode of the DES engine is specified with one of the
//! following flags. Only one is permitted.
//!
//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode
//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode
//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode
//!
//! The selection of single DES or triple DES is specified with one of the
//! following two flags. Only one is permitted.
//!
//! - \b DES_CFG_SINGLE - Single DES
//! - \b DES_CFG_TRIPLE - Triple DES
//!
//! \return None.
//
//*****************************************************************************
void
DESConfigSet(uint32_t ui32Base, uint32_t ui32Config)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Backup the save context field.
//
ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT);
//
// Write the control register.
//
HWREG(ui32Base + DES_O_CTRL) = ui32Config;
}
//*****************************************************************************
//
//! Sets the key used for DES operations.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Key is a pointer to an array that holds the key
//!
//! This function sets the key used for DES operations.
//!
//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or
//! 192 bits (6 words) if triple DES is being used.
//!
//! \return None.
//
//*****************************************************************************
void
DESKeySet(uint32_t ui32Base, uint8_t *pui8Key)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Write the first part of the key.
//
HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0));
HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4));
//
// If we are performing triple DES, then write the key registers for
// the second and third rounds.
//
if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE)
{
HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8));
HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12));
HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16));
HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20));
}
}
//*****************************************************************************
//
//! Sets the initialization vector in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to
//! be written into the initialization vectors registers.
//!
//! This function sets the initialization vector in the DES module. It returns
//! true if the registers were successfully written. If the context registers
//! cannot be written at the time the function was called, then false is
//! returned.
//!
//! \return True or false.
//
//*****************************************************************************
bool
DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Check to see if context registers can be overwritten. If not, return
// false.
//
if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0)
{
return(false);
}
//
// Write the initialization vector registers.
//
HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0));
HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4));
//
// Return true to indicate the write was successful.
//
return(true);
}
//*****************************************************************************
//
//! Sets the crytographic data length in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Length is the length of the data in bytes.
//!
//! This function writes the cryptographic data length into the DES module.
//! When this register is written, the engine is triggersed to start using
//! this context.
//!
//! \note Data lengths up to (2^32 - 1) bytes are allowed.
//!
//! \return None.
//
//*****************************************************************************
void
DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Write the length register.
//
HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
}
//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Dest is a pointer to an array of 2 words.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function returns true if the data was ready when the function was
//! called. If the data was not ready, false is returned.
//!
//! \return True or false.
//
//*****************************************************************************
bool
DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
{
volatile uint32_t pui32Dest[2];
uint8_t ui8BytCnt;
uint8_t *pui8DestTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return(false);
}
//
// Check to see if the data is ready to be read.
//
if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
return(false);
}
//
// Read two words of data from the data registers.
//
pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
//
//Copy the data to a block memory
//
pui8DestTemp = (uint8_t *)pui32Dest;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
}
//
// Return true to indicate a successful write.
//
return(true);
}
//*****************************************************************************
//
//! Reads plaintext/ciphertext from data registers with blocking.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Dest is a pointer to an array of bytes.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function waits until the DES module is finished and encrypted or
//! decrypted data is ready. The output data is then stored in the pui8Dest
//! array.
//!
//! \return None
//
//*****************************************************************************
void
DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length)
{
volatile uint32_t pui32Dest[2];
uint8_t ui8BytCnt;
uint8_t *pui8DestTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return;
}
//
// Wait for data output to be ready.
//
while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0)
{
}
//
// Read two words of data from the data registers.
//
pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L);
pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H);
//
//Copy the data to a block memory
//
pui8DestTemp = (uint8_t *)pui32Dest;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt);
}
}
//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of 2 words.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function returns false if the DES module is not ready to accept
//! data. It returns true if the data was written successfully.
//!
//! \return true or false.
//
//*****************************************************************************
bool
DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
{
volatile uint32_t pui32Src[2]={0,0};
uint8_t ui8BytCnt;
uint8_t *pui8SrcTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return(false);
}
//
// Check if the DES module is ready to encrypt or decrypt data. If it
// is not, return false.
//
if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))))
{
return(false);
}
//
// Copy the data to a block memory
//
pui8SrcTemp = (uint8_t *)pui32Src;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
}
//
// Write the data.
//
HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
//
// Return true to indicate a successful write.
//
return(true);
}
//*****************************************************************************
//
//! Writes plaintext/ciphertext to data registers without blocking
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of bytes.
//! \param ui8Length the length can be from 1 to 8
//!
//! This function waits until the DES module is ready before writing the
//! data contained in the pui8Src array.
//!
//! \return None.
//
//*****************************************************************************
void
DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length)
{
volatile uint32_t pui32Src[2]={0,0};
uint8_t ui8BytCnt;
uint8_t *pui8SrcTemp;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
if((ui8Length == 0)||(ui8Length>8))
{
return;
}
//
// Wait for the input ready bit to go high.
//
while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0)
{
}
//
//Copy the data to a block memory
//
pui8SrcTemp = (uint8_t *)pui32Src;
for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++)
{
*(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt);
}
//
// Write the data.
//
HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0];
HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1];
}
//*****************************************************************************
//
//! Processes blocks of data through the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pui8Src is a pointer to an array of words that contains the
//! source data for processing.
//! \param pui8Dest is a pointer to an array of words consisting of the
//! processed data.
//! \param ui32Length is the length of the cryptographic data in bytes.
//! It must be a multiple of eight.
//!
//! This function takes the data contained in the pui8Src array and processes
//! it using the DES engine. The resulting data is stored in the
//! pui8Dest array. The function blocks until all of the data has been
//! processed. If processing is successful, the function returns true.
//!
//! \note This functions assumes that the DES module has been configured,
//! and initialization values and keys have been written.
//!
//! \return true or false.
//
//*****************************************************************************
bool
DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest,
uint32_t ui32Length)
{
uint32_t ui32Count, ui32BlkCount, ui32ByteCount;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Length % 8) == 0);
//
// Write the length register first. This triggers the engine to start
// using this context.
//
HWREG(ui32Base + DES_O_LENGTH) = ui32Length;
//
// Now loop until the blocks are written.
//
ui32BlkCount = ui32Length/8;
for(ui32Count = 0; ui32Count <ui32BlkCount; ui32Count ++)
{
//
// Check if the input ready is fine
//
while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Write the data registers.
//
DESDataWriteNonBlocking(ui32Base, pui8Src + ui32Count*8 ,8);
//
// Wait for the output ready
//
while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Read the data registers.
//
DESDataReadNonBlocking(ui32Base, pui8Dest + ui32Count*8 ,8);
}
//
//Now handle the residue bytes
//
ui32ByteCount = ui32Length%8;
if(ui32ByteCount)
{
//
// Check if the input ready is fine
//
while((DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Write the data registers.
//
DESDataWriteNonBlocking(ui32Base, pui8Src + (8*ui32BlkCount) ,
ui32ByteCount);
//
// Wait for the output ready
//
while((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0)
{
}
//
// Read the data registers.
//
DESDataReadNonBlocking(ui32Base, pui8Dest + (8*ui32BlkCount) ,
ui32ByteCount);
}
//
// Return true to indicate the process was successful.
//
return(true);
}
//*****************************************************************************
//
//! Returns the current interrupt status of the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This function gets the current interrupt status of the DES module.
//! The value returned is a logical OR of the following values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT_INT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return A bit mask of the current interrupt status.
//
//*****************************************************************************
uint32_t
DESIntStatus(uint32_t ui32Base, bool bMasked)
{
uint32_t ui32IntStatus;
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Read the status register and return the value.
//
if(bMasked)
{
ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
ui32IntStatus &= HWREG(ui32Base + DES_O_IRQENABLE);
ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0x7) << 16);
return(ui32IntStatus);
}
else
{
ui32IntStatus = HWREG(ui32Base + DES_O_IRQSTATUS);
ui32IntStatus |= ((HWREG(DTHE_BASE + DTHE_O_DES_MIS) & 0xD) << 16);
return(ui32IntStatus);
}
}
//*****************************************************************************
//
//! Enables interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be enabled.
//!
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return None.
//
//*****************************************************************************
void
DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DATA_IN) ||
(ui32IntFlags & DES_INT_DATA_OUT) ||
(ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
//
// Enable the interrupts from the flags.
//
HWREG(DTHE_BASE + DTHE_O_DES_IM) &= ~((ui32IntFlags & 0x00070000) >> 16);
HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff;
}
//*****************************************************************************
//
//! Disables interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
//!
//! This function disables interrupt sources in the DES module.
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DATA_IN - Data input interrupt
//! - \b DES_INT_DATA_OUT - Data output interrupt
//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt
//!
//! \return None.
//
//*****************************************************************************
void
DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DATA_IN) ||
(ui32IntFlags & DES_INT_DATA_OUT) ||
(ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
//
// Clear the interrupts from the flags.
//
HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16);
HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff);
}
//*****************************************************************************
//
//! Clears interrupts in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32IntFlags is a bit mask of the interrupts to be disabled.
//!
//! This function disables interrupt sources in the DES module.
//! \e ui32IntFlags should be a logical OR of one or more of the following
//! values:
//!
//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt
//! - \b DES_INT_DMA_DATA_IN - Data input interrupt
//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt
//!
//! \note The DMA done interrupts are the only interrupts that can be cleared.
//! The remaining interrupts can be disabled instead using DESIntDisable().
//!
//! \return None.
//
//*****************************************************************************
void
DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_IN) ||
(ui32IntFlags & DES_INT_DMA_DATA_OUT));
HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled DES interrupts occur.
//!
//! This function registers the interrupt handler in the interrupt vector
//! table, and enables DES interrupts on the interrupt controller; specific DES
//! interrupt sources must be enabled using DESIntEnable(). The interrupt
//! handler being registered must clear the source of the interrupt using
//! DESIntClear().
//!
//! If the application is using a static interrupt vector table stored in
//! flash, then it is not necessary to register the interrupt handler this way.
//! Instead, IntEnable() should be used to enable DES interrupts on the
//! interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Register the interrupt handler.
//
IntRegister(INT_DES, pfnHandler);
//
// Enable the interrupt.
//
IntEnable(INT_DES);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//!
//! This function unregisters the previously registered interrupt handler and
//! disables the interrupt in the interrupt controller.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
DESIntUnregister(uint32_t ui32Base)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
//
// Disable the interrupt.
//
IntDisable(INT_DES);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_DES);
}
//*****************************************************************************
//
//! Enables DMA request sources in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Flags is a bit mask of the DMA requests to be enabled.
//!
//! This function enables DMA request sources in the DES module. The
//! \e ui32Flags parameter should be the logical OR of any of the following:
//!
//! - \b DES_DMA_CONTEXT_IN - Context In
//! - \b DES_DMA_DATA_OUT - Data Out
//! - \b DES_DMA_DATA_IN - Data In
//!
//! \return None.
//
//*****************************************************************************
void
DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
(ui32Flags & DES_DMA_DATA_OUT) ||
(ui32Flags & DES_DMA_DATA_IN));
//
// Set the data in and data out DMA request enable bits.
//
HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags;
}
//*****************************************************************************
//
//! Disables DMA request sources in the DES module.
//!
//! \param ui32Base is the base address of the DES module.
//! \param ui32Flags is a bit mask of the DMA requests to be disabled.
//!
//! This function disables DMA request sources in the DES module. The
//! \e ui32Flags parameter should be the logical OR of any of the following:
//!
//! - \b DES_DMA_CONTEXT_IN - Context In
//! - \b DES_DMA_DATA_OUT - Data Out
//! - \b DES_DMA_DATA_IN - Data In
//!
//! \return None.
//
//*****************************************************************************
void
DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags)
{
//
// Check the arguments.
//
ASSERT(ui32Base == DES_BASE);
ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) ||
(ui32Flags & DES_DMA_DATA_OUT) ||
(ui32Flags & DES_DMA_DATA_IN));
//
// Disable the DMA sources.
//
HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

144
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// des.h
//
// Defines and Macros for the DES module.
//
//*****************************************************************************
#ifndef __DRIVERLIB_DES_H__
#define __DRIVERLIB_DES_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the direction with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_DIR_DECRYPT 0x00000000
#define DES_CFG_DIR_ENCRYPT 0x00000004
//*****************************************************************************
//
// The following defines are used to specify the operational with the
// ui32Config argument in the DESConfig() function. Only one is permitted.
//
//*****************************************************************************
#define DES_CFG_MODE_ECB 0x00000000
#define DES_CFG_MODE_CBC 0x00000010
#define DES_CFG_MODE_CFB 0x00000020
//*****************************************************************************
//
// The following defines are used to select between single DES and triple DES
// with the ui32Config argument in the DESConfig() function. Only one is
// permitted.
//
//*****************************************************************************
#define DES_CFG_SINGLE 0x00000000
#define DES_CFG_TRIPLE 0x00000008
//*****************************************************************************
//
// The following defines are used with the DESIntEnable(), DESIntDisable() and
// DESIntStatus() functions.
//
//*****************************************************************************
#define DES_INT_CONTEXT_IN 0x00000001
#define DES_INT_DATA_IN 0x00000002
#define DES_INT_DATA_OUT 0x00000004
#define DES_INT_DMA_CONTEXT_IN 0x00010000
#define DES_INT_DMA_DATA_IN 0x00020000
#define DES_INT_DMA_DATA_OUT 0x00040000
//*****************************************************************************
//
// The following defines are used with the DESEnableDMA() and DESDisableDMA()
// functions.
//
//*****************************************************************************
#define DES_DMA_CONTEXT_IN 0x00000080
#define DES_DMA_DATA_OUT 0x00000040
#define DES_DMA_DATA_IN 0x00000020
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest,
uint8_t ui8Length);
extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t *pui8Dest, uint32_t ui32Length);
extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src,
uint8_t ui8Length);
extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags);
extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked);
extern void DESIntUnregister(uint32_t ui32Base);
extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata);
extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key);
extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_DES_H__

864
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// flash.c
//
// Driver for programming the on-chip flash.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup flash_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_flash_ctrl.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_gprcm.h"
#include "inc/hw_hib1p2.h"
#include "inc/hw_hib3p3.h"
#include "inc/hw_common_reg.h"
#include "inc/hw_stack_die_ctrl.h"
#include "debug.h"
#include "flash.h"
#include "utils.h"
#include "interrupt.h"
#define HAVE_WRITE_BUFFER 1
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Program Enable (FMPPE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPPERegs[] =
{
FLASH_FMPPE0,
FLASH_FMPPE1,
FLASH_FMPPE2,
FLASH_FMPPE3,
FLASH_FMPPE4,
FLASH_FMPPE5,
FLASH_FMPPE6,
FLASH_FMPPE7,
FLASH_FMPPE8,
FLASH_FMPPE9,
FLASH_FMPPE10,
FLASH_FMPPE11,
FLASH_FMPPE12,
FLASH_FMPPE13,
FLASH_FMPPE14,
FLASH_FMPPE15
};
//*****************************************************************************
//
// An array that maps the specified memory bank to the appropriate Flash
// Memory Protection Read Enable (FMPRE) register.
//
//*****************************************************************************
static const unsigned long g_pulFMPRERegs[] =
{
FLASH_FMPRE0,
FLASH_FMPRE1,
FLASH_FMPRE2,
FLASH_FMPRE3,
FLASH_FMPRE4,
FLASH_FMPRE5,
FLASH_FMPRE6,
FLASH_FMPRE7,
FLASH_FMPRE8,
FLASH_FMPRE9,
FLASH_FMPRE10,
FLASH_FMPRE11,
FLASH_FMPRE12,
FLASH_FMPRE13,
FLASH_FMPRE14,
FLASH_FMPRE15,
};
//*****************************************************************************
//
//! Flash Disable
//!
//! This function Disables the internal Flash.
//!
//! \return None.
//
//*****************************************************************************
void
FlashDisable()
{
//
// Wait for Flash Busy to get cleared
//
while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE)
& GPRCM_TOP_DIE_ENABLE_FLASH_BUSY))
{
}
//
// Assert reset
//
HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
//
// Disable TDFlash
//
HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
//
// 50 usec Delay Loop
//
UtilsDelay((50*80)/3);
}
//*****************************************************************************
//
//! Erases a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
//
//*****************************************************************************
long
FlashErase(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
// Erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC)
= FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
//
// Wait until the block has been erased.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Erases a block of flash but does not wait for completion.
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 2 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return None.
//
//*****************************************************************************
void
FlashEraseNonBlocking(unsigned long ulAddress)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1)));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller to erase the block.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE;
}
//*****************************************************************************
//
//! Erases a complele flash at shot.
//!
//! This function erases a complele flash at shot
//!
//! \return Returns 0 on success, or -1 if the block is write-protected.
//
//*****************************************************************************
long
FlashMassErase()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
//
// Wait until mass erase completes.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1)
{
}
//
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)
& (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_ERRIS))
{
return -1;
}
//
// Success.
//
return 0;
}
//*****************************************************************************
//
//! Erases a complele flash at shot but does not wait for completion.
//!
//!
//! This function will not return until the Flash has been erased.
//!
//! \return None.
//
//*****************************************************************************
void
FlashMassEraseNonBlocking()
{
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) =
(FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_ERMISC);
//
// Command the flash controller for mass erase.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) =
FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1;
}
//*****************************************************************************
//
//! Programs flash.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times will result in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
//*****************************************************************************
long
FlashProgram(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words. for 1 MB
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) ||
(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN
+ (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2)
= FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
//
// Wait until the write buffer has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF)
{
}
}
}
#else
{
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Program the next word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
//
// Wait until the word has been programmed.
//
while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE)
{
}
//
// Increment to the next word.
//
pulData++;
ulAddress += 4;
ulCount -= 4;
}
}
#endif
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS |
FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS))
{
return(-1);
}
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Programs flash but does not poll for completion.
//!
//! \param pulData is a pointer to the data to be programmed.
//! \param ulAddress is the starting address in flash to be programmed. Must
//! be a multiple of four.
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will start programming one or more words into the on-chip
//! flash and return immediately. The number of words that can be programmed
//! in a single call depends the part on which the function is running. For
//! parts without support for a flash write buffer, only a single word may be
//! programmed on each call to this function (\e ulCount must be 1). If a
//! write buffer is present, up to 32 words may be programmed on condition
//! that the block being programmed does not straddle a 32 word address
//! boundary. For example, wherease 32 words can be programmed if the address
//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could
//! be programmed at 0x104 since attempting to write 32 would cross the 32
//! word boundary at 0x180.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will return immediately after commanding the erase operation.
//! Applications making use of the function can determine completion state by
//! using a flash interrupt handler or by polling FlashIntStatus.
//!
//! \return 0 if the write was started successfully, -1 if there was an error.
//
//*****************************************************************************
long
FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount)
{
//
// Check the arguments.
//
ASSERT(!(ulAddress & 3));
ASSERT(!(ulCount & 3));
//
// Clear the flash access and error interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)
= (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC |
FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
//
#if HAVE_WRITE_BUFFER
{
//
// Make sure the address/count specified doesn't straddle a 32 word
// boundary.
//
if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F))
{
return(-1);
}
//
// Loop over the words to be programmed.
//
while(ulCount)
{
//
// Set the address of this block of words.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F);
//
// Loop over the words in this 32-word block.
//
while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) &&
(ulCount != 0))
{
//
// Write this word into the write buffer.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++;
ulAddress += 4;
ulCount -= 4;
}
//
// Program the contents of the write buffer into flash.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF;
}
}
#else
{
//
// We don't have a write buffer so we can only write a single word.
//
if(ulCount > 1)
{
return(-1);
}
//
// Write a single word.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData;
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE;
}
#endif
//
// Success.
//
return(0);
}
//*****************************************************************************
//
//! Gets the protection setting for a block of flash.
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
//! processor and debugger data reads are not allowed.
//!
//! \return Returns the protection setting for this block. See
//! FlashProtectSet() for possible values.
//
//*****************************************************************************
tFlashProtection
FlashProtectGet(unsigned long ulAddress)
{
unsigned long ulFMPRE, ulFMPPE;
unsigned long ulBank;
//
// Check the argument.
//
ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1)));
//
// Calculate the Flash Bank from Base Address, and mask off the Bank
// from ulAddress for subsequent reference.
//
ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16);
ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1);
//
// Read the appropriate flash protection registers for the specified
// flash bank.
//
ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]);
ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]);
//
// Check the appropriate protection bits for the block of memory that
// is specified by the address.
//
switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) &
FLASH_FMP_BLOCK_0) << 1) |
((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0))
{
//
// This block is marked as execute only (that is, it can not be erased
// or programmed, and the only reads allowed are via the instruction
// fetch interface).
//
case 0:
case 1:
{
return(FlashExecuteOnly);
}
//
// This block is marked as read only (that is, it can not be erased or
// programmed).
//
case 2:
{
return(FlashReadOnly);
}
//
// This block is read/write; it can be read, erased, and programmed.
//
case 3:
default:
{
return(FlashReadWrite);
}
}
}
//*****************************************************************************
//
//! Registers an interrupt handler for the flash interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(INT_FLASH, pfnHandler);
//
// Enable the flash interrupt.
//
IntEnable(INT_FLASH);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntUnregister(void)
{
//
// Disable the interrupt.
//
IntDisable(INT_FLASH);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_FLASH);
}
//*****************************************************************************
//
//! Enables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntEnable(unsigned long ulIntFlags)
{
//
// Enable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables individual flash controller interrupt sources.
//!
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntDisable(unsigned long ulIntFlags)
{
//
// Disable the specified interrupts.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS.
//
//*****************************************************************************
unsigned long
FlashIntStatus(tBoolean bMasked)
{
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC));
}
else
{
return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS));
}
}
//*****************************************************************************
//
//! Clears flash controller interrupt sources.
//!
//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared.
//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
FlashIntClear(unsigned long ulIntFlags)
{
//
// Clear the flash interrupt.
//
HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

0
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@ -0,0 +1,717 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// gpio.c
//
// Driver for the GPIO module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup GPIO_General_Purpose_InputOutput_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_common_reg.h"
#include "debug.h"
#include "gpio.h"
#include "interrupt.h"
//*****************************************************************************
//
//! \internal
//! Checks a GPIO base address.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function determines if a GPIO port base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
GPIOBaseValid(unsigned long ulPort)
{
return((ulPort == GPIOA0_BASE) ||
(ulPort == GPIOA1_BASE) ||
(ulPort == GPIOA2_BASE) ||
(ulPort == GPIOA3_BASE) ||
(ulPort == GPIOA4_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the GPIO interrupt number.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! Given a GPIO base address, returns the corresponding interrupt number.
//!
//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid.
//
//*****************************************************************************
static long
GPIOGetIntNumber(unsigned long ulPort)
{
unsigned int ulInt;
//
// Determine the GPIO interrupt number for the given module.
//
switch(ulPort)
{
case GPIOA0_BASE:
{
ulInt = INT_GPIOA0;
break;
}
case GPIOA1_BASE:
{
ulInt = INT_GPIOA1;
break;
}
case GPIOA2_BASE:
{
ulInt = INT_GPIOA2;
break;
}
case GPIOA3_BASE:
{
ulInt = INT_GPIOA3;
break;
}
default:
{
return(-1);
}
}
//
// Return GPIO interrupt number.
//
return(ulInt);
}
//*****************************************************************************
//
//! Sets the direction and mode of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulPinIO is the pin direction and/or mode.
//!
//! This function will set the specified pin(s) on the selected GPIO port
//! as either an input or output under software control, or it will set the
//! pin to be under hardware control.
//!
//! The parameter \e ulPinIO is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_DIR_MODE_IN
//! - \b GPIO_DIR_MODE_OUT
//!
//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as
//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin
//! will be programmed as a software controlled output.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note GPIOPadConfigSet() must also be used to configure the corresponding
//! pad(s) in order for them to propagate the signal to/from the GPIO.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulPinIO)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT));
//
// Set the pin direction and mode.
//
HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the direction and mode of a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the direction and control mode for a specified pin on
//! the selected GPIO port. The pin can be configured as either an input or
//! output under software control, or it can be under hardware control. The
//! type of control and direction are returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIODirModeSet().
//
//*****************************************************************************
unsigned long
GPIODirModeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulDir;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
//
ucPin = 1 << ucPin;
//
// Return the pin direction and mode.
//
ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR);
return(((ulDir & ucPin) ? 1 : 0));
}
//*****************************************************************************
//
//! Sets the interrupt type for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ulIntType specifies the type of interrupt trigger mechanism.
//!
//! This function sets up the various interrupt trigger mechanisms for the
//! specified pin(s) on the selected GPIO port.
//!
//! The parameter \e ulIntType is an enumerated data type that can be one of
//! the following values:
//!
//! - \b GPIO_FALLING_EDGE
//! - \b GPIO_RISING_EDGE
//! - \b GPIO_BOTH_EDGES
//! - \b GPIO_LOW_LEVEL
//! - \b GPIO_HIGH_LEVEL
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \note In order to avoid any spurious interrupts, the user must
//! ensure that the GPIO inputs remain stable for the duration of
//! this function.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
unsigned long ulIntType)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT((ulIntType == GPIO_FALLING_EDGE) ||
(ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) ||
(ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL));
//
// Set the pin interrupt type.
//
HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ?
(HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ?
(HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins)));
HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ?
(HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) :
(HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins)));
}
//*****************************************************************************
//
//! Gets the interrupt type for a pin.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPin is the pin number.
//!
//! This function gets the interrupt type for a specified pin on the selected
//! GPIO port. The pin can be configured as a falling edge, rising edge, or
//! both edge detected interrupt, or it can be configured as a low level or
//! high level detected interrupt. The type of interrupt detection mechanism
//! is returned as an enumerated data type.
//!
//! \return Returns one of the enumerated data types described for
//! GPIOIntTypeSet().
//
//*****************************************************************************
unsigned long
GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin)
{
unsigned long ulIBE, ulIS, ulIEV;
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
ASSERT(ucPin < 8);
//
// Convert from a pin number to a bit position.
//
ucPin = 1 << ucPin;
//
// Return the pin interrupt type.
//
ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE);
ulIS = HWREG(ulPort + GPIO_O_GPIO_IS);
ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV);
return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) |
((ulIEV & ucPin) ? 4 : 0));
}
//*****************************************************************************
//
//! Enables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to enable.
//!
//! This function enables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Enable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags;
}
//*****************************************************************************
//
//! Disables the specified GPIO interrupts.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is the bit mask of the interrupt sources to disable.
//!
//! This function disables the indicated GPIO interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done
//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0.
//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1.
//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2.
//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3.
//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4.
//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5.
//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6.
//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Disable the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags);
}
//*****************************************************************************
//
//! Gets interrupt status for the specified GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param bMasked specifies whether masked or raw interrupt status is
//! returned.
//!
//! If \e bMasked is set as \b true, then the masked interrupt status is
//! returned; otherwise, the raw interrupt status will be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in GPIOIntEnable().
//
//*****************************************************************************
long
GPIOIntStatus(unsigned long ulPort, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the interrupt status.
//
if(bMasked)
{
return(HWREG(ulPort + GPIO_O_GPIO_MIS));
}
else
{
return(HWREG(ulPort + GPIO_O_GPIO_RIS));
}
}
//*****************************************************************************
//
//! Clears the interrupt for the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! Clears the interrupt for the specified pin(s).
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to GPIOIntEnable().
//!
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Clear the interrupts.
//
HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags;
}
//*****************************************************************************
//
//! Registers an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling
//! function.
//!
//! This function will ensure that the interrupt handler specified by
//! \e pfnIntHandler is called when an interrupt is detected from the selected
//! GPIO port. This function will also enable the corresponding GPIO interrupt
//! in the interrupt controller; individual pin interrupts and interrupt
//! sources must be enabled with GPIOIntEnable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void))
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Register the interrupt handler.
//
IntRegister(ulPort, pfnIntHandler);
//
// Enable the GPIO interrupt.
//
IntEnable(ulPort);
}
//*****************************************************************************
//
//! Removes an interrupt handler for a GPIO port.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function will unregister the interrupt handler for the specified
//! GPIO port. This function will also disable the corresponding
//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts
//! and interrupt sources must be disabled with GPIOIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOIntUnregister(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Get the interrupt number associated with the specified GPIO.
//
ulPort = GPIOGetIntNumber(ulPort);
//
// Disable the GPIO interrupt.
//
IntDisable(ulPort);
//
// Unregister the interrupt handler.
//
IntUnregister(ulPort);
}
//*****************************************************************************
//
//! Reads the values present of the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//!
//! The values at the specified pin(s) are read, as specified by \e ucPins.
//! Values are returned for both input and output pin(s), and the value
//! for pin(s) that are not specified by \e ucPins are set to 0.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return Returns a bit-packed byte providing the state of the specified
//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents
//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins
//! is returned as a 0. Bits 31:8 should be ignored.
//
//*****************************************************************************
long
GPIOPinRead(unsigned long ulPort, unsigned char ucPins)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Return the pin value(s).
//
return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))));
}
//*****************************************************************************
//
//! Writes a value to the specified pin(s).
//!
//! \param ulPort is the base address of the GPIO port.
//! \param ucPins is the bit-packed representation of the pin(s).
//! \param ucVal is the value to write to the pin(s).
//!
//! Writes the corresponding bit values to the output pin(s) specified by
//! \e ucPins. Writing to a pin configured as an input pin has no effect.
//!
//! The pin(s) are specified using a bit-packed byte, where each bit that is
//! set identifies the pin to be accessed, and where bit 0 of the byte
//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on.
//!
//! \return None.
//
//*****************************************************************************
void
GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Write the pins.
//
HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal;
}
//*****************************************************************************
//
//! Enables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function enables a GPIO port to be used as a trigger to start a uDMA
//! transaction. The GPIO pin will still generate interrupts if the interrupt is
//! enabled for the selected pin.
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerEnable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8;
}
}
//*****************************************************************************
//
//! Disables a GPIO port as a trigger to start a DMA transaction.
//!
//! \param ulPort is the base address of the GPIO port.
//!
//! This function disables a GPIO port to be used as a trigger to start a uDMA
//! transaction. This function can be used to disable this feature if it was
//! enabled via a call to GPIODMATriggerEnable().
//!
//! \return None.
//
//*****************************************************************************
void
GPIODMATriggerDisable(unsigned long ulPort)
{
//
// Check the arguments.
//
ASSERT(GPIOBaseValid(ulPort));
//
// Set the pin as a DMA trigger.
//
if(ulPort == GPIOA0_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1;
}
else if(ulPort == GPIOA1_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2;
}
else if(ulPort == GPIOA2_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4;
}
else if(ulPort == GPIOA3_BASE)
{
HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8;
}
}
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.c
//
// Driver for the Apps-NWP spinlock
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup HwSpinLock_api
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
#include "inc/hw_common_reg.h"
#include "hwspinlock.h"
//*****************************************************************************
// Global semaphore register list
//*****************************************************************************
static const uint32_t HwSpinLock_RegLst[]=
{
COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register
};
//*****************************************************************************
//
//! Acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function acquires specified spin lock and will not retun util the
//! specified lock is acquired.
//!
//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0.
//!
//! return None.
//
//*****************************************************************************
void HwSpinLockAcquire(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Retry untill we succeed
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) );
}
//*****************************************************************************
//
//! Try to acquire specified spin lock.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param ui32Retry is the number of reties.
//!
//! This function tries acquire specified spin lock in \e ui32Retry retries.
//!
//! The parameter \e ui32Retry can be any value between 0 and 2^32.
//!
//! return Returns 0 on success, -1 otherwise.
//
//*****************************************************************************
int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
uint32_t ui32RegAddr;
//
// Extract the bit position from the
// LockID
//
ui32BitPos = ((ui32LockID >> 16) & 0x0FFF);
ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF];
//
// Set the corresponding
// ownership bits to 'b01
//
ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos));
//
// Check for 0 retry.
//
if(ui32Retry == 0)
{
ui32Retry = 1;
}
//
// Retry the number of times specified
//
do
{
HWREG(ui32RegAddr) = ui32SemVal;
ui32Retry--;
}
while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry );
//
// Check the semaphore status
//
if(HWREG(ui32RegAddr) & (1 << ui32BitPos ))
{
return 0;
}
else
{
return -1;
}
}
//*****************************************************************************
//
//! Release a previously owned spin lock
//!
//! \param ui32LockID is one of the valid spin lock.
//!
//! This function releases previously owned spin lock.
//!
//! \return None.
//
//*****************************************************************************
void HwSpinLockRelease(uint32_t ui32LockID)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// Release the spin lock, only if already owned
//
if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos ))
{
ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos));
HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal;
}
}
//*****************************************************************************
//
//! Get the current or previous ownership status.
//!
//! \param ui32LockID is one of the valid spin lock.
//! \param bCurrentStatus is \b true for current status, \b flase otherwise
//!
//! This function gets the current or previous ownership status of the
//! specified spin lock based on \e bCurrentStatus parameter.
//!
//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or
//! \b HWSPINLOCK_OWNER_NONE.
//
//*****************************************************************************
uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus)
{
uint32_t ui32BitPos;
uint32_t ui32SemVal;
if(bCurrentStatus)
{
//
// Extract the bit position from the
// lock id.
//
ui32BitPos = ((ui32LockID >> 16) & 0x00FF);
//
// return semaphore
//
return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 );
}
else
{
//
// Extract the bit position
//
ui32BitPos = ((ui32LockID >> 24) & 0xFF);
//
// Identify which register to read
//
if(ui32LockID & 0xF > 4)
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3);
}
else
{
ui32SemVal = ((HWREG(COMMON_REG_BASE +
COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3);
}
//
// return the owner
//
return ui32SemVal;
}
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hwspinlock.h
//
// Prototypes for the Apps-NWP spinlock.
//
//*****************************************************************************
#ifndef __HWSPINLOCK_H__
#define __HWSPINLOCK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// values that can be passed to API as ui32LockID parameter
//*****************************************************************************
#define HWSPINLOCK_SSPI 0x02000000
//*****************************************************************************
// Values that are returned from HwSpinLockTest()
//*****************************************************************************
#define HWSPINLOCK_OWNER_APPS 0x00000001
#define HWSPINLOCK_OWNER_NWP 0x00000002
#define HWSPINLOCK_OWNER_NONE 0x00000000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void HwSpinLockAcquire(uint32_t ui32LockID);
extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry);
extern void HwSpinLockRelease(uint32_t ui32LockID);
extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __HWSPINLOCK_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.c Executable file
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2c.h
//
// Prototypes for the I2C Driver.
//
//*****************************************************************************
#ifndef __DRIVERLIB_I2C_H__
#define __DRIVERLIB_I2C_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
// Interrupt defines.
//
//*****************************************************************************
#define I2C_INT_MASTER 0x00000001
#define I2C_INT_SLAVE 0x00000002
//*****************************************************************************
//
// I2C Master commands.
//
//*****************************************************************************
#define I2C_MASTER_CMD_SINGLE_SEND \
0x00000007
#define I2C_MASTER_CMD_SINGLE_RECEIVE \
0x00000007
#define I2C_MASTER_CMD_BURST_SEND_START \
0x00000003
#define I2C_MASTER_CMD_BURST_SEND_CONT \
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
0x0000000b
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \
0x00000009
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \
0x00000013
#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \
0x00000046
#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \
0x00000046
#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \
0x00000042
#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \
0x00000040
#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \
0x0000004a
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \
0x00000048
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \
0x00000044
#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \
0x00000004
//*****************************************************************************
//
// I2C Master glitch filter configuration.
//
//*****************************************************************************
#define I2C_MASTER_GLITCH_FILTER_DISABLED \
0
#define I2C_MASTER_GLITCH_FILTER_1 \
0x00010000
#define I2C_MASTER_GLITCH_FILTER_2 \
0x00020000
#define I2C_MASTER_GLITCH_FILTER_3 \
0x00030000
#define I2C_MASTER_GLITCH_FILTER_4 \
0x00040000
#define I2C_MASTER_GLITCH_FILTER_8 \
0x00050000
#define I2C_MASTER_GLITCH_FILTER_16 \
0x00060000
#define I2C_MASTER_GLITCH_FILTER_32 \
0x00070000
//*****************************************************************************
//
// I2C Master error status.
//
//*****************************************************************************
#define I2C_MASTER_ERR_NONE 0
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004
#define I2C_MASTER_ERR_DATA_ACK 0x00000008
#define I2C_MASTER_ERR_ARB_LOST 0x00000010
#define I2C_MASTER_ERR_CLK_TOUT 0x00000080
//*****************************************************************************
//
// I2C Slave action requests
//
//*****************************************************************************
#define I2C_SLAVE_ACT_NONE 0
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
// Miscellaneous I2C driver definitions.
//
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_RX_FIFO_FULL \
0x00000800 // RX FIFO Full Interrupt
#define I2C_MASTER_INT_TX_FIFO_EMPTY \
0x00000400 // TX FIFO Empty Interrupt
#define I2C_MASTER_INT_RX_FIFO_REQ \
0x00000200 // RX FIFO Request Interrupt
#define I2C_MASTER_INT_TX_FIFO_REQ \
0x00000100 // TX FIFO Request Interrupt
#define I2C_MASTER_INT_ARB_LOST \
0x00000080 // Arb Lost Interrupt
#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt
#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt
#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt
#define I2C_MASTER_INT_TX_DMA_DONE \
0x00000008 // TX DMA Complete Interrupt
#define I2C_MASTER_INT_RX_DMA_DONE \
0x00000004 // RX DMA Complete Interrupt
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave interrupts.
//
//*****************************************************************************
#define I2C_SLAVE_INT_RX_FIFO_FULL \
0x00000100 // RX FIFO Full Interrupt
#define I2C_SLAVE_INT_TX_FIFO_EMPTY \
0x00000080 // TX FIFO Empty Interrupt
#define I2C_SLAVE_INT_RX_FIFO_REQ \
0x00000040 // RX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_FIFO_REQ \
0x00000020 // TX FIFO Request Interrupt
#define I2C_SLAVE_INT_TX_DMA_DONE \
0x00000010 // TX DMA Complete Interrupt
#define I2C_SLAVE_INT_RX_DMA_DONE \
0x00000008 // RX DMA Complete Interrupt
#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt
#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt
#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt
//*****************************************************************************
//
// I2C Slave FIFO configuration macros.
//
//*****************************************************************************
#define I2C_SLAVE_TX_FIFO_ENABLE \
0x00000002
#define I2C_SLAVE_RX_FIFO_ENABLE \
0x00000004
//*****************************************************************************
//
// I2C FIFO configuration macros.
//
//*****************************************************************************
#define I2C_FIFO_CFG_TX_MASTER 0x00000000
#define I2C_FIFO_CFG_TX_SLAVE 0x00008000
#define I2C_FIFO_CFG_RX_MASTER 0x00000000
#define I2C_FIFO_CFG_RX_SLAVE 0x80000000
#define I2C_FIFO_CFG_TX_MASTER_DMA \
0x00002000
#define I2C_FIFO_CFG_TX_SLAVE_DMA \
0x0000a000
#define I2C_FIFO_CFG_RX_MASTER_DMA \
0x20000000
#define I2C_FIFO_CFG_RX_SLAVE_DMA \
0xa0000000
#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001
#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002
#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003
#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004
#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005
#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006
#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007
#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008
#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000
#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000
#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000
#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000
#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000
#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000
#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000
#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000
#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000
//*****************************************************************************
//
// I2C FIFO status.
//
//*****************************************************************************
#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \
0x00040000
#define I2C_FIFO_RX_FULL 0x00020000
#define I2C_FIFO_RX_EMPTY 0x00010000
#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \
0x00000004
#define I2C_FIFO_TX_FULL 0x00000002
#define I2C_FIFO_TX_EMPTY 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void));
extern void I2CIntUnregister(uint32_t ui32Base);
extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CTxFIFOFlush(uint32_t ui32Base);
extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CRxFIFOFlush(uint32_t ui32Base);
extern uint32_t I2CFIFOStatus(uint32_t ui32Base);
extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data);
extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base,
uint8_t ui8Data);
extern uint32_t I2CFIFODataGet(uint32_t ui32Base);
extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base,
uint8_t *pui8Data);
extern void I2CMasterBurstLengthSet(uint32_t ui32Base,
uint8_t ui8Length);
extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base);
extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base,
uint32_t ui32Config);
extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config);
extern void I2CSlaveFIFODisable(uint32_t ui32Base);
extern bool I2CMasterBusBusy(uint32_t ui32Base);
extern bool I2CMasterBusy(uint32_t ui32Base);
extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd);
extern uint32_t I2CMasterDataGet(uint32_t ui32Base);
extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CMasterDisable(uint32_t ui32Base);
extern void I2CMasterEnable(uint32_t ui32Base);
extern uint32_t I2CMasterErr(uint32_t ui32Base);
extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk,
bool bFast);
extern void I2CMasterIntClear(uint32_t ui32Base);
extern void I2CMasterIntDisable(uint32_t ui32Base);
extern void I2CMasterIntEnable(uint32_t ui32Base);
extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked);
extern void I2CMasterIntEnableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern void I2CMasterIntClearEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value);
extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable);
extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK);
extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base);
extern void I2CMasterSlaveAddrSet(uint32_t ui32Base,
uint8_t ui8SlaveAddr,
bool bReceive);
extern uint32_t I2CSlaveDataGet(uint32_t ui32Base);
extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data);
extern void I2CSlaveDisable(uint32_t ui32Base);
extern void I2CSlaveEnable(uint32_t ui32Base);
extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr);
extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum,
uint8_t ui8SlaveAddr);
extern void I2CSlaveIntClear(uint32_t ui32Base);
extern void I2CSlaveIntDisable(uint32_t ui32Base);
extern void I2CSlaveIntEnable(uint32_t ui32Base);
extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void I2CSlaveIntDisableEx(uint32_t ui32Base,
uint32_t ui32IntFlags);
extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags);
extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked);
extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base,
bool bMasked);
extern uint32_t I2CSlaveStatus(uint32_t ui32Base);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_I2C_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// i2s.h
//
// Defines and Macros for the I2S.
//
//*****************************************************************************
#ifndef __I2S_H__
#define __I2S_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// I2S DMA ports.
//
//*****************************************************************************
#define I2S_TX_DMA_PORT 0x4401E200
#define I2S_RX_DMA_PORT 0x4401E280
//*****************************************************************************
//
// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter.
//
//*****************************************************************************
#define I2S_SLOT_SIZE_8 0x00300032
#define I2S_SLOT_SIZE_16 0x00700074
#define I2S_SLOT_SIZE_24 0x00B000B6
#define I2S_PORT_CPU 0x00080008
#define I2S_PORT_DMA 0x00000000
#define I2S_MODE_MASTER 0x00000000
#define I2S_MODE_SLAVE 0x00008000
//*****************************************************************************
//
// Values that can be passed as ulDataLine parameter.
//
//*****************************************************************************
#define I2S_DATA_LINE_0 0x00000001
#define I2S_DATA_LINE_1 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulSerMode
// parameter.
//
//*****************************************************************************
#define I2S_SER_MODE_TX 0x00000001
#define I2S_SER_MODE_RX 0x00000002
#define I2S_SER_MODE_DISABLE 0x00000000
//*****************************************************************************
//
// Values that can be passed to I2SSerializerConfig() as the ulInActState
// parameter.
//
//*****************************************************************************
#define I2S_INACT_TRI_STATE 0x00000000
#define I2S_INACT_LOW_LEVEL 0x00000008
#define I2S_INACT_HIGH_LEVEL 0x0000000C
//*****************************************************************************
//
// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the
// ulIntFlags parameter.
//
//*****************************************************************************
#define I2S_INT_XUNDRN 0x00000001
#define I2S_INT_XSYNCERR 0x00000002
#define I2S_INT_XLAST 0x00000010
#define I2S_INT_XDATA 0x00000020
#define I2S_INT_XSTAFRM 0x00000080
#define I2S_INT_XDMA 0x80000000
#define I2S_INT_ROVRN 0x00010000
#define I2S_INT_RSYNCERR 0x00020000
#define I2S_INT_RLAST 0x00100000
#define I2S_INT_RDATA 0x00200000
#define I2S_INT_RSTAFRM 0x00800000
#define I2S_INT_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet
//
//*****************************************************************************
#define I2S_ACT_SLOT_EVEN 0x00000001
#define I2S_ACT_SLOT_ODD 0x00000002
//*****************************************************************************
//
// Values that can be passed to I2SIntClear() as the
// ulIntFlags parameter and returned from I2SIntStatus().
//
//*****************************************************************************
#define I2S_STS_XERR 0x00000100
#define I2S_STS_XDMAERR 0x00000080
#define I2S_STS_XSTAFRM 0x00000040
#define I2S_STS_XDATA 0x00000020
#define I2S_STS_XLAST 0x00000010
#define I2S_STS_XSYNCERR 0x00000002
#define I2S_STS_XUNDRN 0x00000001
#define I2S_STS_XDMA 0x80000000
#define I2S_STS_RERR 0x01000000
#define I2S_STS_RDMAERR 0x00800000
#define I2S_STS_RSTAFRM 0x00400000
#define I2S_STS_RDATA 0x00200000
#define I2S_STS_RLAST 0x00100000
#define I2S_STS_RSYNCERR 0x00020000
#define I2S_STS_ROVERN 0x00010000
#define I2S_STS_RDMA 0x40000000
//*****************************************************************************
//
// Values that can be passed to I2SEnable() as the ulMode parameter.
//
//*****************************************************************************
#define I2S_MODE_TX_ONLY 0x00000001
#define I2S_MODE_TX_RX_SYNC 0x00000003
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void I2SEnable(unsigned long ulBase, unsigned long ulMode);
extern void I2SDisable(unsigned long ulBase);
extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulData);
extern long I2SDataPutNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long ulData);
extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine,
unsigned long *pulData);
extern long I2SDataGetNonBlocking(unsigned long ulBase,
unsigned long ulDataLine, unsigned long *pulData);
extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk,
unsigned long ulBitClk, unsigned long ulConfig);
extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulWordsPerTransfer);
extern void I2STxFIFODisable(unsigned long ulBase);
extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel,
unsigned long ulWordsPerTransfer);
extern void I2SRxFIFODisable(unsigned long ulBase);
extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase);
extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase);
extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine,
unsigned long ulSerMode, unsigned long ulInActState);
extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long I2SIntStatus(unsigned long ulBase);
extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void I2SIntUnregister(unsigned long ulBase);
extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif //__I2S_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// interrupt.c
//
// Driver for the NVIC Interrupt Controller.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup interrupt_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
#include "interrupt.h"
//*****************************************************************************
//
// This is a mapping between priority grouping encodings and the number of
// preemption priority bits.
//
//*****************************************************************************
static const unsigned long g_pulPriority[] =
{
NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6,
NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3,
NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1
};
//*****************************************************************************
//
// This is a mapping between interrupt number and the register that contains
// the priority encoding for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37,
NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43,
NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4,
NVIC_UNPEND5
};
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler for all interrupts. It simply loops
//! forever so that the system state is preserved for observation by a
//! debugger. Since interrupts should be disabled before unregistering the
//! corresponding handler, this should never be called.
//!
//! \return None.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
//
// Go into an infinite loop.
//
while(1)
{
}
}
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterEnable(void)
{
//
// Enable processor interrupts.
//
return(CPUcpsie());
}
//*****************************************************************************
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
tBoolean
IntMasterDisable(void)
{
//
// Disable processor interrupts.
//
return(CPUcpsid());
}
//*****************************************************************************
//
//! Sets the NVIC VTable base.
//!
//! \param ulVtableBase specifies the new base address of VTable
//!
//! This function is used to specify a new base address for the VTable.
//! This function must be called before using IntRegister() for registering
//! any interrupt handler.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntVTableBaseSet(unsigned long ulVtableBase)
{
HWREG(NVIC_VTABLE) = ulVtableBase;
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param pfnHandler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//!
//!
//! \return None.
//
//*****************************************************************************
void
IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
IntUnregister(unsigned long ulInterrupt)
{
unsigned long *ulNvicTbl;
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE);
ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler;
}
//*****************************************************************************
//
//! Sets the priority grouping of the interrupt controller.
//!
//! \param ulBits specifies the number of bits of preemptable priority.
//!
//! This function specifies the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification. The range of
//! the grouping values are dependent upon the hardware implementation; on
//! the CC3200 , three bits are available for hardware interrupt
//! prioritization and therefore priority grouping values of three through
//! seven have the same effect.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityGroupingSet(unsigned long ulBits)
{
//
// Check the arguments.
//
ASSERT(ulBits < NUM_PRIORITY);
//
// Set the priority grouping.
//
HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits];
}
//*****************************************************************************
//
//! Gets the priority grouping of the interrupt controller.
//!
//! This function returns the split between preemptable priority levels and
//! subpriority levels in the interrupt priority specification.
//!
//! \return The number of bits of preemptable priority.
//
//*****************************************************************************
unsigned long
IntPriorityGroupingGet(void)
{
unsigned long ulLoop, ulValue;
//
// Read the priority grouping.
//
ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M;
//
// Loop through the priority grouping values.
//
for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++)
{
//
// Stop looping if this value matches.
//
if(ulValue == g_pulPriority[ulLoop])
{
break;
}
}
//
// Return the number of priority bits.
//
return(ulLoop);
}
//*****************************************************************************
//
//! Sets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//! \param ucPriority specifies the priority of the interrupt.
//!
//! This function is used to set the priority of an interrupt. When multiple
//! interrupts are asserted simultaneously, the ones with the highest priority
//! are processed before the lower priority interrupts. Smaller numbers
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any prioritization must be performed in
//! those bits. The remaining bits can be used to sub-prioritize the interrupt
//! sources, and may be used by the hardware priority mechanism on a future
//! part. This arrangement allows priorities to migrate to different NVIC
//! implementations without changing the gross prioritization of the
//! interrupts.
//!
//! The parameter \e ucPriority can be any one of the following
//! -\b INT_PRIORITY_LVL_0
//! -\b INT_PRIORITY_LVL_1
//! -\b INT_PRIORITY_LVL_2
//! -\b INT_PRIORITY_LVL_3
//! -\b INT_PRIORITY_LVL_4
//! -\b INT_PRIORITY_LVL_5
//! -\b INT_PRIORITY_LVL_6
//! -\b INT_PRIORITY_LVL_7
//!
//! \return None.
//
//*****************************************************************************
void
IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority)
{
unsigned long ulTemp;
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Set the interrupt priority.
//
ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]);
ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3)));
ulTemp |= ucPriority << (8 * (ulInterrupt & 3));
HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp;
}
//*****************************************************************************
//
//! Gets the priority of an interrupt.
//!
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function gets the priority of an interrupt. See IntPrioritySet() for
//! a definition of the priority value.
//!
//! \return Returns the interrupt priority, or -1 if an invalid interrupt was
//! specified.
//
//*****************************************************************************
long
IntPriorityGet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS));
//
// Return the interrupt priority.
//
return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) &
0xFF);
}
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntEnable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to enable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Enable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Enable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Enable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Enable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! \return None.
//
//*****************************************************************************
void
IntDisable(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to disable.
//
if(ulInterrupt == FAULT_MPU)
{
//
// Disable the MemManage interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_BUS)
{
//
// Disable the bus fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_USAGE)
{
//
// Disable the usage fault interrupt.
//
HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Disable the System Tick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Pends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendSet(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to pend.
//
if(ulInterrupt == FAULT_NMI)
{
//
// Pend the NMI interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_PENDSV)
{
//
// Pend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Pend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
__asm(" dsb ");
__asm(" isb ");
}
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
__asm(" dsb ");
__asm(" isb ");
}
}
//*****************************************************************************
//
//! Unpends an interrupt.
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//!
//! \return None.
//
//*****************************************************************************
void
IntPendClear(unsigned long ulInterrupt)
{
//
// Check the arguments.
//
ASSERT(ulInterrupt < NUM_INTERRUPTS);
//
// Determine the interrupt to unpend.
//
if(ulInterrupt == FAULT_PENDSV)
{
//
// Unpend the PendSV interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV;
}
else if(ulInterrupt == FAULT_SYSTICK)
{
//
// Unpend the SysTick interrupt.
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
//*****************************************************************************
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return None.
//
//*****************************************************************************
void
IntPriorityMaskSet(unsigned long ulPriorityMask)
{
CPUbasepriSet(ulPriorityMask);
}
//*****************************************************************************
//
//! Gets the priority masking level
//!
//! This function gets the current setting of the interrupt priority masking
//! level. The value returned is the priority level such that all interrupts
//! of that and lesser priority are masked. A value of 0 means that priority
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! priority level (where N is 3), so any
//! prioritization must be performed in those bits.
//!
//! \return Returns the value of the interrupt priority level mask.
//
//*****************************************************************************
unsigned long
IntPriorityMaskGet(void)
{
return(CPUbasepriGet());
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.h Normal file → Executable file
View file

4
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.c Normal file → Executable file
View file

@ -243,7 +243,7 @@ unsigned long PinDirModeGet(unsigned long ulPin)
//
//*****************************************************************************
void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType)
unsigned long *pulPinType)
{
unsigned long ulPad;
@ -354,7 +354,7 @@ void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
// Write the configuration
//
HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) |
(ulPinStrength | ulPinType ));
(ulPinStrength | ulPinType ));
}

2
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.h Normal file → Executable file
View file

@ -164,7 +164,7 @@ extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
extern unsigned long PinDirModeGet(unsigned long ulPin);
extern unsigned long PinModeGet(unsigned long ulPin);
extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
unsigned long *pulPinType);
unsigned long *pulPinType);
extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
unsigned long ulPinType);
extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.c Normal file → Executable file
View file

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.h Normal file → Executable file
View file

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom.h Normal file → Executable file
View file

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_map.h Normal file → Executable file
View file

2
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_patch.h Normal file → Executable file
View file

@ -108,6 +108,8 @@
#undef ROM_PRCMIORetentionEnable
#undef ROM_PRCMIORetentionDisable
#undef ROM_PRCMCC3200MCUInit
#undef ROM_SHAMD5ConfigSet
#undef ROM_SHAMD5HMACKeySet
#endif
#endif // __ROM_PATCH_H__

745
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.c Executable file
View file

@ -0,0 +1,745 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// sdhost.c
//
// Driver for the SD Host (SDHost) Interface
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup Secure_Digital_Host_api
//! @{
//
//*****************************************************************************
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_mmchs.h"
#include "inc/hw_ints.h"
#include "inc/hw_apps_config.h"
#include "interrupt.h"
#include "sdhost.h"
//*****************************************************************************
//
//! Configures SDHost module.
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function configures the SDHost module, enabling internal sub-modules.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostInit(unsigned long ulBase)
{
//
// Assert module reset
//
HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2;
//
// Wait for soft reset to complete
//
while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) )
{
}
//
// Assert internal reset
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24);
//
// Wait for Reset to complete
//
while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) )
{
}
//
// Set capability register, 1.8 and 3.0 V
//
HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24);
//
// Select bus voltage, 3.0 V
//
HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9;
//
// Power up the bus
//
HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8;
//
// Wait for power on
//
while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) )
{
}
HWREG(ulBase + MMCHS_O_CON) |= 1 << 21;
//
// Un-mask all events
//
HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF;
}
//*****************************************************************************
//
//! Resets SDHost command line
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function assers a soft reset for the command line
//!
//! \return None.
//
//*****************************************************************************
void
SDHostCmdReset(unsigned long ulBase)
{
HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25;
while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) )
{
}
}
//*****************************************************************************
//
//! Sends command over SDHost interface
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulCmd is the command to send.
//! \param ulArg is the argument for the command.
//!
//! This function send command to the attached card over the SDHost interface.
//!
//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63.
//! It can be logically ORed with one or more of the following:
//! - \b SDHOST_MULTI_BLK for multi-block transfer
//! - \b SDHOST_WR_CMD if command is followed by write data
//! - \b SDHOST_RD_CMD if command is followed by read data
//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request.
//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected
//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected
//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected
//!
//! The parameter \e ulArg is the argument for the command
//!
//! \return Returns 0 on success, -1 otherwise.
//
//*****************************************************************************
long
SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg)
{
//
// Set Data Timeout
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000;
//
// Check for cmd inhabit
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1))
{
return -1;
}
//
// Set the argument
//
HWREG(ulBase + MMCHS_O_ARG) = ulArg;
//
// Send the command
//
HWREG(ulBase + MMCHS_O_CMD) = ulCmd;
return 0;
}
//*****************************************************************************
//
//! Writes a data word into the SDHost write buffer.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulData is data word to be transfered.
//!
//! This function writes a single data word into the SDHost write buffer. The
//! function returns \b true if there was a space available in the buffer else
//! returns \b false.
//!
//! \return Return \b true on success, \b false otherwise.
//
//*****************************************************************************
tBoolean
SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData)
{
//
// See if there is a space in the write buffer
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
{
//
// Write the data into the buffer
//
HWREG(ulBase + MMCHS_O_DATA) = ulData;
//
// Success.
//
return(true);
}
else
{
//
// No free sapce, failure.
//
return(false);
}
}
//*****************************************************************************
//
//! Waits to write a data word into the SDHost write buffer.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulData is data word to be transfered.
//!
//! This function writes \e ulData into the SDHost write buffer. If there is no
//! space in the write buffer this function waits until there is a space
//! available before returning.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostDataWrite(unsigned long ulBase, unsigned long ulData)
{
//
// Wait until space is available
//
while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) )
{
}
//
// Write the data
//
HWREG(ulBase + MMCHS_O_DATA) = ulData;
}
//*****************************************************************************
//
//! Waits for a data word from the SDHost read buffer
//!
//! \param ulBase is the base address of SDHost module.
//! \param pulData is pointer to read data variable.
//!
//! This function reads a single data word from the SDHost read buffer. If there
//! is no data available in the buffer the function will wait until a data
//! word is received before returning.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostDataRead(unsigned long ulBase, unsigned long *pulData)
{
//
// Wait until data is available
//
while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
{
}
//
// Read the data
//
*pulData = HWREG(ulBase + MMCHS_O_DATA);
}
//*****************************************************************************
//
//! Reads single data word from the SDHost read buffer
//!
//! \param ulBase is the base address of SDHost module.
//! \param pulData is pointer to read data variable.
//!
//! This function reads a data word from the SDHost read buffer. The
//! function returns \b true if there was data available in to buffer else
//! returns \b false.
//!
//! \return Return \b true on success, \b false otherwise.
//
//*****************************************************************************
tBoolean
SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData)
{
//
// See if there is any data in the read buffer.
//
if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) )
{
//
// Read the data word.
//
*pulData = HWREG(ulBase + MMCHS_O_DATA);
//
// Success
//
return(true);
}
else
{
//
// No data available, failure.
//
return(false);
}
}
//*****************************************************************************
//
//! Registers the interrupt handler for SDHost interrupt
//!
//! \param ulBase is the base address of SDHost module
//! \param pfnHandler is a pointer to the function to be called when the
//! SDHost interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! function enables the global interrupt in the interrupt controller; specific
//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Register the interrupt handler.
//
IntRegister(INT_MMCHS, pfnHandler);
//
// Enable the SDHost interrupt.
//
IntEnable(INT_MMCHS);
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for SDHost interrupt
//!
//! \param ulBase is the base address of SDHost module
//!
//! This function does the actual unregistering of the interrupt handler. It
//! clears the handler to be called when a SDHost interrupt occurs. This
//! function also masks off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntUnregister(unsigned long ulBase)
{
//
// Disable the SDHost interrupt.
//
IntDisable(INT_MMCHS);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_MMCHS);
}
//*****************************************************************************
//
//! Enable individual interrupt source for the specified SDHost
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function enables the indicated SDHost interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//! - \b SDHOST_INT_CC Command Complete interrupt
//! - \b SDHOST_INT_TC Transfer Complete interrupt
//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt
//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt
//! - \b SDHOST_INT_ERRI Error interrupt
//! - \b SDHOST_INT_CTO Command Timeout error interrupt
//! - \b SDHOST_INT_CEB Command End Bit error interrupt
//! - \b SDHOST_INT_DTO Data Timeout error interrupt
//! - \b SDHOST_INT_DCRC Data CRC error interrupt
//! - \b SDHOST_INT_DEB Data End Bit error
//! - \b SDHOST_INT_CERR Cart Status Error interrupt
//! - \b SDHOST_INT_BADA Bad Data error interrupt
//! - \b SDHOST_INT_DMARD Read DMA done interrupt
//! - \b SDHOST_INT_DMAWR Write DMA done interrupt
//!
//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus()
//! and is internally logical OR of all error status bits. Setting this bit
//! alone as \e ulIntFlags doesn't generates any interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Enable DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) =
(ulIntFlags >> 30);
//
// Enable the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Enable individual interrupt source for the specified SDHost
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! This function disables the indicated SDHost interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to SDHostIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Disable DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) =
(ulIntFlags >> 30);
//
// Disable the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Gets the current interrupt status.
//!
//! \param ulBase is the base address of SDHost module.
//!
//! This function returns the interrupt status for the specified SDHost.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in SDHostIntEnable().
//
//*****************************************************************************
unsigned long
SDHostIntStatus(unsigned long ulBase)
{
unsigned long ulIntStatus;
//
// Get DMA done interrupt status
//
ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW);
ulIntStatus = (ulIntStatus << 30);
//
// Return the status of individual interrupt sources
//
ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF);
return(ulIntStatus);
}
//*****************************************************************************
//
//! Clears the individual interrupt sources.
//!
//! \param ulBase is the base address of SDHost module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SDHost interrupt sources are cleared, so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being recognized again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to SDHostIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags)
{
//
// Clear DMA done interrupts
//
HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) =
(ulIntFlags >> 30);
//
// Clear the individual interrupt sources
//
HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF);
}
//*****************************************************************************
//
//! Sets the card status error mask.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulErrMask is the bit mask of card status errors to be enabled
//!
//! This function sets the card status error mask for response type R1, R1b,
//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card
//! status errors to be enabled, if the corresponding bits in the 'card status'
//! field of a respose are set then the host controller indicates a card error
//! interrupt status. Only bits referenced as type E (error) in status field in
//! the response can set a card status error.
//!
//! \return None
//
//*****************************************************************************
void
SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask)
{
//
// Set the card status error mask
//
HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask;
}
//*****************************************************************************
//
//! Gets the card status error mask.
//!
//! \param ulBase is the base address of SDHost module
//!
//! This function gets the card status error mask for response type R1, R1b,
//! R5, R5b and R6 response.
//!
//! \return Returns the current card status error.
//
//*****************************************************************************
unsigned long
SDHostCardErrorMaskGet(unsigned long ulBase)
{
//
// Return the card status error mask
//
return(HWREG(ulBase + MMCHS_O_CSRE));
}
//*****************************************************************************
//
//! Sets the SD Card clock.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulSDHostClk is the rate of clock supplied to SDHost module
//! \param ulCardClk is the required SD interface clock
//!
//! This function configures the SDHost interface to supply the specified clock
//! to the connected card.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
unsigned long ulCardClk)
{
unsigned long ulDiv;
//
// Disable card clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4;
//
// Enable internal clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1;
ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF);
//
// Set clock divider,
//
HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) &
~0x0000FFC0)| (ulDiv) << 6);
//
// Wait for clock to stablize
//
while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) )
{
}
//
// Enable card clock
//
HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4;
}
//*****************************************************************************
//
//! Get the response for the last command.
//!
//! \param ulBase is the base address of SDHost module
//! \param ulRespnse is 128-bit response.
//!
//! This function gets the response from the SD card for the last command
//! send.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4])
{
//
// Read the responses.
//
ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10);
ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32);
ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54);
ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76);
}
//*****************************************************************************
//
//! Set the block size for data transfer
//!
//! \param ulBase is the base address of SDHost module
//! \param ulBlkSize is the transfer block size in bytes
//!
//! This function sets the block size the data transfer.
//!
//! The parameter \e ulBlkSize is size of each data block in bytes.
//! This should be in range 0 - 2^10.
//!
//! \return None.
//
//*****************************************************************************
void
SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize)
{
//
// Set the block size
//
HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)|
(ulBlkSize & 0xFFF));
}
//*****************************************************************************
//
//! Set the block size and count for data transfer
//!
//! \param ulBase is the base address of SDHost module
//! \param ulBlkCount is the number of blocks
//!
//! This function sets block count for the data transfer. This needs to be set
//! for each block transfer. \sa SDHostBlockSizeSet()
//!
//! \return None.
//
//*****************************************************************************
void
SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount)
{
unsigned long ulRegVal;
//
// Read the current value
//
ulRegVal = HWREG(ulBase + MMCHS_O_BLK);
//
// Set the number of blocks
//
HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)|
(ulBlkCount << 16));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// sdhost.h
//
// Defines and Macros for the SDHost.
//
//*****************************************************************************
#ifndef __SDHOST_H__
#define __SDHOST_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
//{
#endif
//*****************************************************************************
// Values that can be passed to SDHostRespGet().
//*****************************************************************************
#define SDHOST_RESP_10 0x00000003
#define SDHOST_RESP_32 0x00000002
#define SDHOST_RESP_54 0x00000001
#define SDHOST_RESP_76 0x00000000
//*****************************************************************************
// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(),
// SDHostIntClear() ,and returned from SDHostIntStatus().
//*****************************************************************************
#define SDHOST_INT_CC 0x00000001
#define SDHOST_INT_TC 0x00000002
#define SDHOST_INT_BWR 0x00000010
#define SDHOST_INT_BRR 0x00000020
#define SDHOST_INT_ERRI 0x00008000
#define SDHOST_INT_CTO 0x00010000
#define SDHOST_INT_CEB 0x00040000
#define SDHOST_INT_DTO 0x00100000
#define SDHOST_INT_DCRC 0x00200000
#define SDHOST_INT_DEB 0x00400000
#define SDHOST_INT_CERR 0x10000000
#define SDHOST_INT_BADA 0x20000000
#define SDHOST_INT_DMARD 0x40000000
#define SDHOST_INT_DMAWR 0x80000000
//*****************************************************************************
// Values that can be passed to SDHostCmdSend().
//*****************************************************************************
#define SDHOST_CMD_0 0x00000000
#define SDHOST_CMD_1 0x01000000
#define SDHOST_CMD_2 0x02000000
#define SDHOST_CMD_3 0x03000000
#define SDHOST_CMD_4 0x04000000
#define SDHOST_CMD_5 0x05000000
#define SDHOST_CMD_6 0x06000000
#define SDHOST_CMD_7 0x07000000
#define SDHOST_CMD_8 0x08000000
#define SDHOST_CMD_9 0x09000000
#define SDHOST_CMD_10 0x0A000000
#define SDHOST_CMD_11 0x0B000000
#define SDHOST_CMD_12 0x0C000000
#define SDHOST_CMD_13 0x0D000000
#define SDHOST_CMD_14 0x0E000000
#define SDHOST_CMD_15 0x0F000000
#define SDHOST_CMD_16 0x10000000
#define SDHOST_CMD_17 0x11000000
#define SDHOST_CMD_18 0x12000000
#define SDHOST_CMD_19 0x13000000
#define SDHOST_CMD_20 0x14000000
#define SDHOST_CMD_21 0x15000000
#define SDHOST_CMD_22 0x16000000
#define SDHOST_CMD_23 0x17000000
#define SDHOST_CMD_24 0x18000000
#define SDHOST_CMD_25 0x19000000
#define SDHOST_CMD_26 0x1A000000
#define SDHOST_CMD_27 0x1B000000
#define SDHOST_CMD_28 0x1C000000
#define SDHOST_CMD_29 0x1D000000
#define SDHOST_CMD_30 0x1E000000
#define SDHOST_CMD_31 0x1F000000
#define SDHOST_CMD_32 0x20000000
#define SDHOST_CMD_33 0x21000000
#define SDHOST_CMD_34 0x22000000
#define SDHOST_CMD_35 0x23000000
#define SDHOST_CMD_36 0x24000000
#define SDHOST_CMD_37 0x25000000
#define SDHOST_CMD_38 0x26000000
#define SDHOST_CMD_39 0x27000000
#define SDHOST_CMD_40 0x28000000
#define SDHOST_CMD_41 0x29000000
#define SDHOST_CMD_42 0x2A000000
#define SDHOST_CMD_43 0x2B000000
#define SDHOST_CMD_44 0x2C000000
#define SDHOST_CMD_45 0x2D000000
#define SDHOST_CMD_46 0x2E000000
#define SDHOST_CMD_47 0x2F000000
#define SDHOST_CMD_48 0x30000000
#define SDHOST_CMD_49 0x31000000
#define SDHOST_CMD_50 0x32000000
#define SDHOST_CMD_51 0x33000000
#define SDHOST_CMD_52 0x34000000
#define SDHOST_CMD_53 0x35000000
#define SDHOST_CMD_54 0x36000000
#define SDHOST_CMD_55 0x37000000
#define SDHOST_CMD_56 0x38000000
#define SDHOST_CMD_57 0x39000000
#define SDHOST_CMD_58 0x3A000000
#define SDHOST_CMD_59 0x3B000000
#define SDHOST_CMD_60 0x3C000000
#define SDHOST_CMD_61 0x3D000000
#define SDHOST_CMD_62 0x3E000000
#define SDHOST_CMD_63 0x3F000000
//*****************************************************************************
// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend().
//*****************************************************************************
#define SDHOST_MULTI_BLK 0x00000022
#define SDHOST_DMA_EN 0x00000001
#define SDHOST_WR_CMD 0x00200000
#define SDHOST_RD_CMD 0x00200010
#define SDHOST_RESP_LEN_136 0x00010000
#define SDHOST_RESP_LEN_48 0x00020000
#define SDHOST_RESP_LEN_48B 0x00030000
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SDHostCmdReset(unsigned long ulBase);
extern void SDHostInit(unsigned long ulBase);
extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd,
unsigned ulArg);
extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void SDHostIntUnregister(unsigned long ulBase);
extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags);
extern unsigned long SDHostIntStatus(unsigned long ulBase);
extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags);
extern void SDHostCardErrorMaskSet(unsigned long ulBase,
unsigned long ulErrMask);
extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase);
extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk,
unsigned long ulCardClk);
extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]);
extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize);
extern void SDHostBlockCountSet(unsigned long ulBase,
unsigned short ulBlkCount);
extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase,
unsigned long ulData);
extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase,
unsigned long *pulData);
extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData);
extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
//}
#endif
#endif // __SDHOST_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/shamd5.c Executable file
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/shamd5.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// shamd5.h
//
// Defines and Macros for the SHA/MD5.
//
//*****************************************************************************
#ifndef __DRIVERLIB_SHAMD5_H__
#define __DRIVERLIB_SHAMD5_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// The following defines are used to specify the algorithm in use in the
// SHA/MD5 module.
//
//*****************************************************************************
#define SHAMD5_ALGO_MD5 0x00000000 // MD5
#define SHAMD5_ALGO_SHA1 0x00000002 // SHA-1
#define SHAMD5_ALGO_SHA224 0x00000004 // SHA-224
#define SHAMD5_ALGO_SHA256 0x00000006 // SHA-256
//*****************************************************************************
//
// The following definitions represent the number of bits to shift in order
// to configure the differnet bit fields in the SHAMD5_O_MODE register.
//
//*****************************************************************************
#define ALGO_CONSTANT_SHIFT 3
#define CLOSE_HASH_SHIFT 4
#define HMAC_KEY_PROC_SHIFT 5
#define HMAC_OUTER_HASH_SHIFT 7
//*****************************************************************************
//
// The following defines are used to represent the different interrupt sources
// in SHAMD5IntEnable(), SHAMD5IntDisable(), SHAMD5GetIntStatus(), and
// SHAMD5BlockOnIntStatus() functions.
//
//*****************************************************************************
#define SHAMD5_INT_CONTEXT_READY 0x00000008
#define SHAMD5_INT_PARTHASH_READY 0x00000004
#define SHAMD5_INT_INPUT_READY 0x00000002
#define SHAMD5_INT_OUTPUT_READY 0x00000001
#define SHAMD5_INT_DMA_CONTEXT_IN 0x00010000
#define SHAMD5_INT_DMA_DATA_IN 0x00020000
#define SHAMD5_INT_DMA_CONTEXT_OUT 0x00040000
//*****************************************************************************
//
// Function prototypes
//
//*****************************************************************************
extern void SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8_t closeHashFlag,
uint8_t HMACKeyFlag, uint8_t HMACOuterHashFlag);
extern bool SHAMD5DataProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5DataWrite(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5DataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5DMADisable(uint32_t ui32Base);
extern void SHAMD5DMAEnable(uint32_t ui32Base);
extern void SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length);
extern void SHAMD5HMACKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5HMACPPKeyGenerate(uint32_t ui32Base, uint8_t *pui8Key,
uint8_t *pui8PPKey);
extern void SHAMD5HMACPPKeySet(uint32_t ui32Base, uint8_t *pui8Src);
extern bool SHAMD5HMACProcess(uint32_t ui32Base, uint8_t *pui8DataSrc,
uint32_t ui32DataLength, uint8_t *pui8HashResult);
extern void SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags);
extern void SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void));
extern uint32_t SHAMD5IntStatus(uint32_t ui32Base, bool bMasked);
extern void SHAMD5IntUnregister(uint32_t ui32Base);
extern void SHAMD5ResultRead(uint32_t ui32Base, uint8_t *pui8Dest);
extern void SHAMD5ResultWrite(uint32_t ui32Base, uint8_t *pui8Src);
extern void SHAMD5ReadDigestCount(uint32_t ui32Base, uint32_t *count);
extern void SHAMD5WriteDigestCount(uint32_t ui32Base, uint32_t count);
extern void SHAMD5DataWriteMultiple(uint32_t ui32Base, uint8_t *pui8DataSrc, uint32_t ui32DataLength);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_SHAMD5_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/spi.c Executable file
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/spi.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// spi.h
//
// Defines and Macros for the SPI.
//
//*****************************************************************************
#ifndef __SPI_H__
#define __SPI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter
//*****************************************************************************
#define SPI_MODE_MASTER 0x00000000
#define SPI_MODE_SLAVE 0x00000004
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter
//*****************************************************************************
#define SPI_SUB_MODE_0 0x00000000
#define SPI_SUB_MODE_1 0x00000001
#define SPI_SUB_MODE_2 0x00000002
#define SPI_SUB_MODE_3 0x00000003
//*****************************************************************************
// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter
//*****************************************************************************
#define SPI_SW_CTRL_CS 0x01000000
#define SPI_HW_CTRL_CS 0x00000000
#define SPI_3PIN_MODE 0x02000000
#define SPI_4PIN_MODE 0x00000000
#define SPI_TURBO_ON 0x00080000
#define SPI_TURBO_OFF 0x00000000
#define SPI_CS_ACTIVEHIGH 0x00000000
#define SPI_CS_ACTIVELOW 0x00000040
#define SPI_WL_8 0x00000380
#define SPI_WL_16 0x00000780
#define SPI_WL_32 0x00000F80
//*****************************************************************************
// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable()
//*****************************************************************************
#define SPI_TX_FIFO 0x08000000
#define SPI_RX_FIFO 0x10000000
//*****************************************************************************
// Values that can be passed to SPIDMAEnable() and SPIDMADisable()
//*****************************************************************************
#define SPI_RX_DMA 0x00008000
#define SPI_TX_DMA 0x00004000
//*****************************************************************************
// Values that can be passed to SPIIntEnable(), SPIIntDiasble(),
// SPIIntClear() or returned from SPIStatus()
//*****************************************************************************
#define SPI_INT_DMATX 0x20000000
#define SPI_INT_DMARX 0x10000000
#define SPI_INT_EOW 0x00020000
#define SPI_INT_WKS 0x00010000
#define SPI_INT_RX_OVRFLOW 0x00000008
#define SPI_INT_RX_FULL 0x00000004
#define SPI_INT_TX_UDRFLOW 0x00000002
#define SPI_INT_TX_EMPTY 0x00000001
//*****************************************************************************
// Values that can be passed to SPITransfer()
//*****************************************************************************
#define SPI_CS_ENABLE 0x00000001
#define SPI_CS_DISABLE 0x00000002
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void SPIEnable(unsigned long ulBase);
extern void SPIDisable(unsigned long ulBase);
extern void SPIReset(unsigned long ulBase);
extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
unsigned long ulBitRate, unsigned long ulMode,
unsigned long ulSubMode, unsigned long ulConfig);
extern long SPIDataGetNonBlocking(unsigned long ulBase,
unsigned long * pulData);
extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData);
extern long SPIDataPutNonBlocking(unsigned long ulBase,
unsigned long ulData);
extern void SPIDataPut(unsigned long ulBase, unsigned long ulData);
extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
unsigned long ulRxLevel);
extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
unsigned long *pulRxLevel);
extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount);
extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void SPIIntUnregister(unsigned long ulBase);
extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags);
extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags);
extern void SPICSEnable(unsigned long ulBase);
extern void SPICSDisable(unsigned long ulBase);
extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout,
unsigned char *ucDin, unsigned long ulSize,
unsigned long ulFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SPI_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.c
//
// Driver for the SysTick timer in NVIC.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup systick_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "interrupt.h"
#include "systick.h"
//*****************************************************************************
//
//! Enables the SysTick counter.
//!
//! This function starts the SysTick counter. If an interrupt handler has been
//! registered, it is called when the SysTick counter rolls over.
//!
//! \note Calling this function causes the SysTick counter to (re)commence
//! counting from its current value. The counter is not automatically reloaded
//! with the period as specified in a previous call to SysTickPeriodSet(). If
//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be
//! written to force the reload. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the supplied period on the next
//! clock.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickEnable(void)
{
//
// Enable SysTick.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE;
}
//*****************************************************************************
//
//! Disables the SysTick counter.
//!
//! This function stops the SysTick counter. If an interrupt handler has been
//! registered, it is not called until SysTick is restarted.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickDisable(void)
{
//
// Disable SysTick.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE);
}
//*****************************************************************************
//
//! Registers an interrupt handler for the SysTick interrupt.
//!
//! \param pfnHandler is a pointer to the function to be called when the
//! SysTick interrupt occurs.
//!
//! This function registers the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntRegister(void (*pfnHandler)(void))
{
//
// Register the interrupt handler, returning an error if an error occurs.
//
IntRegister(FAULT_SYSTICK, pfnHandler);
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Unregisters the interrupt handler for the SysTick interrupt.
//!
//! This function unregisters the handler to be called when a SysTick interrupt
//! occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntUnregister(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
//
// Unregister the interrupt handler.
//
IntUnregister(FAULT_SYSTICK);
}
//*****************************************************************************
//
//! Enables the SysTick interrupt.
//!
//! This function enables the SysTick interrupt, allowing it to be
//! reflected to the processor.
//!
//! \note The SysTick interrupt handler is not required to clear the SysTick
//! interrupt source because it is cleared automatically by the NVIC when the
//! interrupt handler is called.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntEnable(void)
{
//
// Enable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
//*****************************************************************************
//
//! Disables the SysTick interrupt.
//!
//! This function disables the SysTick interrupt, preventing it from being
//! reflected to the processor.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickIntDisable(void)
{
//
// Disable the SysTick interrupt.
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
//*****************************************************************************
//
//! Sets the period of the SysTick counter.
//!
//! \param ulPeriod is the number of clock ticks in each period of the SysTick
//! counter and must be between 1 and 16,777,216, inclusive.
//!
//! This function sets the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \note Calling this function does not cause the SysTick counter to reload
//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT
//! register must be written. Any write to this register clears the SysTick
//! counter to 0 and causes a reload with the \e ulPeriod supplied here on
//! the next clock after SysTick is enabled.
//!
//! \return None.
//
//*****************************************************************************
void
SysTickPeriodSet(unsigned long ulPeriod)
{
//
// Check the arguments.
//
ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216));
//
// Set the period of the SysTick counter.
//
HWREG(NVIC_ST_RELOAD) = ulPeriod - 1;
}
//*****************************************************************************
//
//! Gets the period of the SysTick counter.
//!
//! This function returns the rate at which the SysTick counter wraps, which
//! equates to the number of processor clocks between interrupts.
//!
//! \return Returns the period of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickPeriodGet(void)
{
//
// Return the period of the SysTick counter.
//
return(HWREG(NVIC_ST_RELOAD) + 1);
}
//*****************************************************************************
//
//! Gets the current value of the SysTick counter.
//!
//! This function returns the current value of the SysTick counter, which is
//! a value between the period - 1 and zero, inclusive.
//!
//! \return Returns the current value of the SysTick counter.
//
//*****************************************************************************
unsigned long
SysTickValueGet(void)
{
//
// Return the current value of the SysTick counter.
//
return(HWREG(NVIC_ST_CURRENT));
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// systick.h
//
// Prototypes for the SysTick driver.
//
//*****************************************************************************
#ifndef __SYSTICK_H__
#define __SYSTICK_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void SysTickEnable(void);
extern void SysTickDisable(void);
extern void SysTickIntRegister(void (*pfnHandler)(void));
extern void SysTickIntUnregister(void);
extern void SysTickIntEnable(void);
extern void SysTickIntDisable(void);
extern void SysTickPeriodSet(unsigned long ulPeriod);
extern unsigned long SysTickPeriodGet(void);
extern unsigned long SysTickValueGet(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __SYSTICK_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// timer.h
//
// Prototypes for the timer module
//
//*****************************************************************************
#ifndef __TIMER_H__
#define __TIMER_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to TimerConfigure as the ulConfig parameter.
//
//*****************************************************************************
#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer
#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count
// timer
#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer
#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count
// timer
#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers
#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer
#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer
#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer
#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter
#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer
#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output
#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer
#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer
#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer
#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter
#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer
#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output
//*****************************************************************************
//
// Values that can be passed to TimerIntEnable, TimerIntDisable, and
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus.
//
//*****************************************************************************
#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt
#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt
#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt
#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt
//*****************************************************************************
//
// Values that can be passed to TimerControlEvent as the ulEvent parameter.
//
//*****************************************************************************
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges
//*****************************************************************************
//
// Values that can be passed to most of the timer APIs as the ulTimer
// parameter.
//
//*****************************************************************************
#define TIMER_A 0x000000ff // Timer A
#define TIMER_B 0x0000ff00 // Timer B
#define TIMER_BOTH 0x0000ffff // Timer Both
//*****************************************************************************
//
// Values that can be passed to TimerSynchronize as the ulTimers parameter.
//
//*****************************************************************************
#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A
#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B
#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A
#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B
#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A
#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B
#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A
#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B
//*****************************************************************************
//
// Values that can be passed to TimerDMAEventSet() or returned from
// TimerDMAEventGet().
//
//*****************************************************************************
#define TIMER_DMA_MODEMATCH_B 0x00000800
#define TIMER_DMA_CAPEVENT_B 0x00000400
#define TIMER_DMA_CAPMATCH_B 0x00000200
#define TIMER_DMA_TIMEOUT_B 0x00000100
#define TIMER_DMA_MODEMATCH_A 0x00000010
#define TIMER_DMA_CAPEVENT_A 0x00000004
#define TIMER_DMA_CAPMATCH_A 0x00000002
#define TIMER_DMA_TIMEOUT_A 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer);
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig);
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer,
tBoolean bInvert);
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulEvent);
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer,
tBoolean bStall);
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer);
extern unsigned long TimerValueGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer,
unsigned long ulValue);
extern unsigned long TimerMatchGet(unsigned long ulBase,
unsigned long ulTimer);
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer,
void (*pfnHandler)(void));
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer);
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent);
extern unsigned long TimerDMAEventGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __TIMER_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// udma.h
//
// Prototypes and macros for the uDMA controller.
//
//*****************************************************************************
#ifndef __UDMA_H__
#define __UDMA_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup uDMA_Micro_Direct_Memory_Access_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// A structure that defines an entry in the channel control table. These
// fields are used by the uDMA controller and normally it is not necessary for
// software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
//
// The ending source address of the data transfer.
//
volatile void *pvSrcEndAddr;
//
// The ending destination address of the data transfer.
//
volatile void *pvDstEndAddr;
//
// The channel control mode.
//
volatile unsigned long ulControl;
//
// An unused location.
//
volatile unsigned long ulSpare;
}
tDMAControlTable;
//*****************************************************************************
//
//! A helper macro for building scatter-gather task table entries.
//!
//! \param ulTransferCount is the count of items to transfer for this task.
//! \param ulItemSize is the bit size of the items to transfer for this task.
//! \param ulSrcIncrement is the bit size increment for source data.
//! \param pvSrcAddr is the starting address of the data to transfer.
//! \param ulDstIncrement is the bit size increment for destination data.
//! \param pvDstAddr is the starting address of the destination data.
//! \param ulArbSize is the arbitration size to use for the transfer task.
//! \param ulMode is the transfer mode for this task.
//!
//! This macro is intended to be used to help populate a table of uDMA tasks
//! for a scatter-gather transfer. This macro will calculate the values for
//! the fields of a task structure entry based on the input parameters.
//!
//! There are specific requirements for the values of each parameter. No
//! checking is done so it is up to the caller to ensure that correct values
//! are used for the parameters.
//!
//! The \e ulTransferCount parameter is the number of items that will be
//! transferred by this task. It must be in the range 1-1024.
//!
//! The \e ulItemSize parameter is the bit size of the transfer data. It must
//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32.
//!
//! The \e ulSrcIncrement parameter is the increment size for the source data.
//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16,
//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE.
//!
//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source
//! data.
//!
//! The \e ulDstIncrement parameter is the increment size for the destination
//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16,
//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE.
//!
//! The \e pvDstAddr parameter is a void pointer to the beginning of the
//! location where the data will be transferred.
//!
//! The \e ulArbSize parameter is the arbitration size for the transfer, and
//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on
//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in
//! powers of 2, from 1 to 1024.
//!
//! The \e ulMode parameter is the mode to use for this transfer task. It
//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO,
//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note
//! that normally all tasks will be one of the scatter-gather modes while the
//! last task is a task list will be AUTO or BASIC.
//!
//! This macro is intended to be used to initialize individual entries of
//! a structure of tDMAControlTable type, like this:
//!
//! \verbatim
//! tDMAControlTable MyTaskList[] =
//! {
//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8,
//! UDMA_SRC_INC_8, MySourceBuf,
//! UDMA_DST_INC_8, MyDestBuf,
//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER),
//! uDMATaskStructEntry(Task2Count, ... ),
//! }
//! \endverbatim
//!
//! \return Nothing; this is not a function.
//
//*****************************************************************************
#define uDMATaskStructEntry(ulTransferCount, \
ulItemSize, \
ulSrcIncrement, \
pvSrcAddr, \
ulDstIncrement, \
pvDstAddr, \
ulArbSize, \
ulMode) \
{ \
(((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \
((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \
((ulSrcIncrement) >> 26)) - 1]))), \
(((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \
((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \
((ulDstIncrement) >> 30)) - 1]))), \
(ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \
(((ulTransferCount) - 1) << 4) | \
((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \
((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \
(ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Flags that can be passed to uDMAChannelAttributeEnable(),
// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet().
//
//*****************************************************************************
#define UDMA_ATTR_USEBURST 0x00000001
#define UDMA_ATTR_ALTSELECT 0x00000002
#define UDMA_ATTR_HIGH_PRIORITY 0x00000004
#define UDMA_ATTR_REQMASK 0x00000008
#define UDMA_ATTR_ALL 0x0000000F
//*****************************************************************************
//
// DMA control modes that can be passed to uDMAModeSet() and returned
// uDMAModeGet().
//
//*****************************************************************************
#define UDMA_MODE_STOP 0x00000000
#define UDMA_MODE_BASIC 0x00000001
#define UDMA_MODE_AUTO 0x00000002
#define UDMA_MODE_PINGPONG 0x00000003
#define UDMA_MODE_MEM_SCATTER_GATHER \
0x00000004
#define UDMA_MODE_PER_SCATTER_GATHER \
0x00000006
#define UDMA_MODE_ALT_SELECT 0x00000001
//*****************************************************************************
//
// Flags to be OR'd with the channel ID to indicate if the primary or alternate
// control structure should be used.
//
//*****************************************************************************
#define UDMA_PRI_SELECT 0x00000000
#define UDMA_ALT_SELECT 0x00000020
//*****************************************************************************
//
// uDMA interrupt sources, to be passed to uDMAIntRegister() and
// uDMAIntUnregister().
//
//*****************************************************************************
#define UDMA_INT_SW INT_UDMA
#define UDMA_INT_ERR INT_UDMAERR
//*****************************************************************************
//*****************************************************************************
//
// Channel configuration values that can be passed to uDMAControlSet().
//
//*****************************************************************************
#define UDMA_DST_INC_8 0x00000000
#define UDMA_DST_INC_16 0x40000000
#define UDMA_DST_INC_32 0x80000000
#define UDMA_DST_INC_NONE 0xc0000000
#define UDMA_SRC_INC_8 0x00000000
#define UDMA_SRC_INC_16 0x04000000
#define UDMA_SRC_INC_32 0x08000000
#define UDMA_SRC_INC_NONE 0x0c000000
#define UDMA_SIZE_8 0x00000000
#define UDMA_SIZE_16 0x11000000
#define UDMA_SIZE_32 0x22000000
#define UDMA_ARB_1 0x00000000
#define UDMA_ARB_2 0x00004000
#define UDMA_ARB_4 0x00008000
#define UDMA_ARB_8 0x0000c000
#define UDMA_ARB_16 0x00010000
#define UDMA_ARB_32 0x00014000
#define UDMA_ARB_64 0x00018000
#define UDMA_ARB_128 0x0001c000
#define UDMA_ARB_256 0x00020000
#define UDMA_ARB_512 0x00024000
#define UDMA_ARB_1024 0x00028000
#define UDMA_NEXT_USEBURST 0x00000008
//*****************************************************************************
//
// Values that can be passed to uDMAChannelAssign() to select peripheral
// mapping for each channel. The channels named RESERVED may be assigned
// to a peripheral in future parts.
//
//*****************************************************************************
//
// Channel 0
//
#define UDMA_CH0_TIMERA0_A 0x00000000
#define UDMA_CH0_SHAMD5_CIN 0x00010000
#define UDMA_CH0_SW 0x00030000
//
// Channel 1
//
#define UDMA_CH1_TIMERA0_B 0x00000001
#define UDMA_CH1_SHAMD5_DIN 0x00010001
#define UDMA_CH1_SW 0x00030001
//
// Channel 2
//
#define UDMA_CH2_TIMERA1_A 0x00000002
#define UDMA_CH2_SHAMD5_COUT 0x00010002
#define UDMA_CH2_SW 0x00030002
//
// Channel 3
//
#define UDMA_CH3_TIMERA1_B 0x00000003
#define UDMA_CH3_DES_CIN 0x00010003
#define UDMA_CH3_SW 0x00030003
//
// Channel 4
//
#define UDMA_CH4_TIMERA2_A 0x00000004
#define UDMA_CH4_DES_DIN 0x00010004
#define UDMA_CH4_I2S_RX 0x00020004
#define UDMA_CH4_SW 0x00030004
//
// Channel 5
//
#define UDMA_CH5_TIMERA2_B 0x00000005
#define UDMA_CH5_DES_DOUT 0x00010005
#define UDMA_CH5_I2S_TX 0x00020005
#define UDMA_CH5_SW 0x00030005
//
// Channel 6
//
#define UDMA_CH6_TIMERA3_A 0x00000006
#define UDMA_CH6_GSPI_RX 0x00010006
#define UDMA_CH6_GPIOA2 0x00020006
#define UDMA_CH6_SW 0x00030006
//
// Channel 7
//
#define UDMA_CH7_TIMERA3_B 0x00000007
#define UDMA_CH7_GSPI_TX 0x00010007
#define UDMA_CH7_GPIOA3 0x00020007
#define UDMA_CH7_SW 0x00030007
//
// Channel 8
//
#define UDMA_CH8_UARTA0_RX 0x00000008
#define UDMA_CH8_TIMERA0_A 0x00010008
#define UDMA_CH8_TIMERA2_A 0x00020008
#define UDMA_CH8_SW 0x00030008
//
// Channel 9
//
#define UDMA_CH9_UARTA0_TX 0x00000009
#define UDMA_CH9_TIMERA0_B 0x00010009
#define UDMA_CH9_TIMERA2_B 0x00020009
#define UDMA_CH9_SW 0x00030009
//
// Channel 10
//
#define UDMA_CH10_UARTA1_RX 0x0000000A
#define UDMA_CH10_TIMERA1_A 0x0001000A
#define UDMA_CH10_TIMERA3_A 0x0002000A
#define UDMA_CH10_SW 0x0003000A
//
// Channel 11
//
#define UDMA_CH11_UARTA1_TX 0x0000000B
#define UDMA_CH11_TIMERA1_B 0x0001000B
#define UDMA_CH11_TIMERA3_B 0x0002000B
#define UDMA_CH11_SW 0x0003000B
//
// Channel 12
//
#define UDMA_CH12_LSPI_RX 0x0000000C
#define UDMA_CH12_SW 0x0003000C
//
// Channel 13
//
#define UDMA_CH13_LSPI_TX 0x0000000D
#define UDMA_CH13_SW 0x0003000D
//
// Channel 14
//
#define UDMA_CH14_ADC_CH0 0x0000000E
#define UDMA_CH14_SDHOST_RX 0x0002000E
#define UDMA_CH14_SW 0x0003000E
//
// Channel 15
//
#define UDMA_CH15_ADC_CH1 0x0000000F
#define UDMA_CH15_SDHOST_TX 0x0002000F
#define UDMA_CH15_SW 0x0003000F
//
// Channel 16
//
#define UDMA_CH16_ADC_CH2 0x00000010
#define UDMA_CH16_TIMERA2_A 0x00010010
#define UDMA_CH16_SW 0x00030010
//
// Channel 17
//
#define UDMA_CH17_ADC_CH3 0x00000011
#define UDMA_CH17_TIMERA2_B 0x00010011
#define UDMA_CH17_SW 0x00030011
//
// Channel 18
//
#define UDMA_CH18_GPIOA0 0x00000012
#define UDMA_CH18_AES_CIN 0x00010012
#define UDMA_CH18_I2S_RX 0x00020012
#define UDMA_CH18_SW 0x00030012
//
// Channel 19
//
#define UDMA_CH19_GPOIA1 0x00000013
#define UDMA_CH19_AES_COUT 0x00010013
#define UDMA_CH19_I2S_TX 0x00020013
#define UDMA_CH19_SW 0x00030013
//
// Channel 20
//
#define UDMA_CH20_GPIOA2 0x00000014
#define UDMA_CH20_AES_DIN 0x00010014
#define UDMA_CH20_SW 0x00030014
//
// Channel 21
//
#define UDMA_CH21_GPIOA3 0x00000015
#define UDMA_CH21_AES_DOUT 0x00010015
#define UDMA_CH21_SW 0x00030015
//
// Channel 22
//
#define UDMA_CH22_CAMERA 0x00000016
#define UDMA_CH22_GPIOA4 0x00010016
#define UDMA_CH22_SW 0x00030016
//
// Channel 23
//
#define UDMA_CH23_SDHOST_RX 0x00000017
#define UDMA_CH23_TIMERA3_A 0x00010017
#define UDMA_CH23_TIMERA2_A 0x00020017
#define UDMA_CH23_SW 0x00030017
//
// Channel 24
//
#define UDMA_CH24_SDHOST_TX 0x00000018
#define UDMA_CH24_TIMERA3_B 0x00010018
#define UDMA_CH24_TIMERA2_B 0x00020018
#define UDMA_CH24_SW 0x00030018
//
// Channel 25
//
#define UDMA_CH25_SSPI_RX 0x00000019
#define UDMA_CH25_I2CA0_RX 0x00010019
#define UDMA_CH25_SW 0x00030019
//
// Channel 26
//
#define UDMA_CH26_SSPI_TX 0x0000001A
#define UDMA_CH26_I2CA0_TX 0x0001001A
#define UDMA_CH26_SW 0x0003001A
//
// Channel 27
//
#define UDMA_CH27_GPIOA0 0x0001001B
#define UDMA_CH27_SW 0x0003001B
//
// Channel 28
//
#define UDMA_CH28_GPIOA1 0x0001001C
#define UDMA_CH28_SW 0x0003001C
//
// Channel 29
//
#define UDMA_CH29_GPIOA4 0x0000001D
#define UDMA_CH29_SW 0x0003001D
//
// Channel 30
//
#define UDMA_CH30_GSPI_RX 0x0000001E
#define UDMA_CH30_SDHOST_RX 0x0001001E
#define UDMA_CH30_I2CA0_RX 0x0002001E
#define UDMA_CH30_SW 0x0003001E
//
// Channel 31
//
#define UDMA_CH31_GSPI_TX 0x0000001F
#define UDMA_CH31_SDHOST_TX 0x0001001F
#define UDMA_CH31_I2CA0_RX 0x0002001F
#define UDMA_CH31_SW 0x0003001F
//*****************************************************************************
//
// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
//
//*****************************************************************************
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
// Pointer
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
// End Pointer
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
//
//*****************************************************************************
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
#define UDMA_SRCENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
//
//*****************************************************************************
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
#define UDMA_DSTENDP_ADDR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHCTL register.
//
//*****************************************************************************
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
#define UDMA_CHCTL_XFERMODE_STOP \
0x00000000 // Stop
#define UDMA_CHCTL_XFERMODE_BASIC \
0x00000001 // Basic
#define UDMA_CHCTL_XFERMODE_AUTO \
0x00000002 // Auto-Request
#define UDMA_CHCTL_XFERMODE_PINGPONG \
0x00000003 // Ping-Pong
#define UDMA_CHCTL_XFERMODE_MEM_SG \
0x00000004 // Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_MEM_SGA \
0x00000005 // Alternate Memory Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SG \
0x00000006 // Peripheral Scatter-Gather
#define UDMA_CHCTL_XFERMODE_PER_SGA \
0x00000007 // Alternate Peripheral
// Scatter-Gather
#define UDMA_CHCTL_XFERSIZE_S 4
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void uDMAEnable(void);
extern void uDMADisable(void);
extern unsigned long uDMAErrorStatusGet(void);
extern void uDMAErrorStatusClear(void);
extern void uDMAChannelEnable(unsigned long ulChannelNum);
extern void uDMAChannelDisable(unsigned long ulChannelNum);
extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum);
extern void uDMAControlBaseSet(void *pControlTable);
extern void *uDMAControlBaseGet(void);
extern void *uDMAControlAlternateBaseGet(void);
extern void uDMAChannelRequest(unsigned long ulChannelNum);
extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum,
unsigned long ulAttr);
extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum);
extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex,
unsigned long ulControl);
extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex,
unsigned long ulMode, void *pvSrcAddr,
void *pvDstAddr,
unsigned long ulTransferSize);
extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum,
unsigned ulTaskCount, void *pvTaskList,
unsigned long ulIsPeriphSG);
extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex);
extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex);
extern void uDMAIntRegister(unsigned long ulIntChannel,
void (*pfnHandler)(void));
extern void uDMAIntUnregister(unsigned long ulIntChannel);
extern unsigned long uDMAIntStatus(void);
extern void uDMAIntClear(unsigned long ulChanMask);
extern void uDMAChannelAssign(unsigned long ulMapping);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __UDMA_H__

0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.c Normal file → Executable file
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0
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.h Normal file → Executable file
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76
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/version.h Executable file
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@ -0,0 +1,76 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// version.h
//
// Contains Driverlib version details
//
//*****************************************************************************
#ifndef __DRIVERLIB_VERSION_H__
#define __DRIVERLIB_VERSION_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#define DRIVERLIB_MAJOR_VERSION_NUM 01
#define DRIVERLIB_MINOR_VERSION_NUM 51
#define DRIVERLIB_PATCH_VERSION_NUM 02
#define DRIVERLIB_BUILD_VERSION_NUM 00
#define DRIVERLIB_RELEASE_DAY 01
#define DRIVERLIB_RELEASE_MONTH 08
#define DRIVERLIB_RELEASE_YEAR 2017
/////////////////////////////////////////////
// !!! Please update the changes.log file !!!
/////////////////////////////////////////////
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __DRIVERLIB_VERSION_H__

492
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.c Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// wdt.c
//
// Driver for the Watchdog Timer Module.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup WDT_Watchdog_Timer_api
//! @{
//
//*****************************************************************************
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_wdt.h"
#include "debug.h"
#include "interrupt.h"
#include "wdt.h"
//*****************************************************************************
//
//! Determines if the watchdog timer is enabled.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will check to see if the watchdog timer is enabled.
//!
//! \return Returns \b true if the watchdog timer is enabled, and \b false
//! if it is not.
//
//*****************************************************************************
tBoolean
WatchdogRunning(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// See if the watchdog timer module is enabled, and return.
//
return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN);
}
//*****************************************************************************
//
//! Enables the watchdog timer.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This will enable the watchdog timer counter and interrupt.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Enable the watchdog timer module.
//
HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN;
}
//*****************************************************************************
//
//! Enables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Locks out write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogLock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Lock out watchdog register writes. Writing anything to the WDT_O_LOCK
// register causes the lock to go into effect.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED;
}
//*****************************************************************************
//
//! Disables the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Enables write access to the watchdog timer configuration registers.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogUnlock(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Unlock watchdog register writes.
//
HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
}
//*****************************************************************************
//
//! Gets the state of the watchdog timer lock mechanism.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! Returns the lock state of the watchdog timer registers.
//!
//! \return Returns \b true if the watchdog timer registers are locked, and
//! \b false if they are not locked.
//
//*****************************************************************************
tBoolean
WatchdogLockState(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the lock state.
//
return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false);
}
//*****************************************************************************
//
//! Sets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param ulLoadVal is the load value for the watchdog timer.
//!
//! This function sets the value to load into the watchdog timer when the count
//! reaches zero for the first time; if the watchdog timer is running when this
//! function is called, then the value will be immediately loaded into the
//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an
//! interrupt is immediately generated.
//!
//! \note This function will have no effect if the watchdog timer has
//! been locked.
//!
//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet()
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Set the load register.
//
HWREG(ulBase + WDT_O_LOAD) = ulLoadVal;
}
//*****************************************************************************
//
//! Gets the watchdog timer reload value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function gets the value that is loaded into the watchdog timer when
//! the count reaches zero for the first time.
//!
//! \sa WatchdogReloadSet()
//!
//! \return None.
//
//*****************************************************************************
unsigned long
WatchdogReloadGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the load register.
//
return(HWREG(ulBase + WDT_O_LOAD));
}
//*****************************************************************************
//
//! Gets the current watchdog timer value.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function reads the current value of the watchdog timer.
//!
//! \return Returns the current value of the watchdog timer.
//
//*****************************************************************************
unsigned long
WatchdogValueGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Get the current watchdog timer register value.
//
return(HWREG(ulBase + WDT_O_VALUE));
}
//*****************************************************************************
//
//! Registers an interrupt handler for watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param pfnHandler is a pointer to the function to be called when the
//! watchdog timer interrupt occurs.
//!
//! This function does the actual registering of the interrupt handler. This
//! will enable the global interrupt in the interrupt controller; the watchdog
//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! WatchdogIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note This function will only register the standard watchdog interrupt
//! handler. To register the NMI watchdog handler, use IntRegister()
//! to register the handler for the \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Register the interrupt handler and
// Enable the watchdog timer interrupt.
//
IntRegister(INT_WDT, pfnHandler);
IntEnable(INT_WDT);
}
//*****************************************************************************
//
//! Unregisters an interrupt handler for the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function does the actual unregistering of the interrupt handler. This
//! function will clear the handler to be called when a watchdog timer
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \note This function will only unregister the standard watchdog interrupt
//! handler. To unregister the NMI watchdog handler, use IntUnregister()
//! to unregister the handler for the \b FAULT_NMI interrupt.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntUnregister(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Disable the interrupt
IntDisable(INT_WDT);
//
// Unregister the interrupt handler.
//
IntUnregister(INT_WDT);
}
//*****************************************************************************
//
//! Gets the current watchdog timer interrupt status.
//!
//! \param ulBase is the base address of the watchdog timer module.
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the watchdog timer module. Either
//! the raw interrupt status or the status of interrupt that is allowed to
//! reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, where a 1 indicates that the
//! watchdog interrupt is active, and a 0 indicates that it is not active.
//
//*****************************************************************************
unsigned long
WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Return either the interrupt status or the raw interrupt status as
// requested.
//
if(bMasked)
{
return(HWREG(ulBase + WDT_O_MIS));
}
else
{
return(HWREG(ulBase + WDT_O_RIS));
}
}
//*****************************************************************************
//
//! Clears the watchdog timer interrupt.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! The watchdog timer interrupt source is cleared, so that it no longer
//! asserts.
//!
//! \note Because there is a write buffer in the Cortex-M3 processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogIntClear(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Clear the interrupt source.
//
HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT;
}
//*****************************************************************************
//
//! Enables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function allows the watchdog timer to stop counting when the processor
//! is stopped by the debugger. By doing so, the watchdog is prevented from
//! expiring (typically almost immediately from a human time perspective) and
//! resetting the system (if reset is enabled). The watchdog will instead
//! expired after the appropriate number of processor cycles have been executed
//! while debugging (or at the appropriate time after the processor has been
//! restarted).
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallEnable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Enable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL;
}
//*****************************************************************************
//
//! Disables stalling of the watchdog timer during debug events.
//!
//! \param ulBase is the base address of the watchdog timer module.
//!
//! This function disables the debug mode stall of the watchdog timer. By
//! doing so, the watchdog timer continues to count regardless of the processor
//! debug state.
//!
//! \return None.
//
//*****************************************************************************
void
WatchdogStallDisable(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == WDT_BASE));
//
// Disable timer stalling.
//
HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL);
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************

83
ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// wdt.h - Prototypes for the Watchdog Timer API
//
//
#ifndef __WATCHDOG_H__
#define __WATCHDOG_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern tBoolean WatchdogRunning(unsigned long ulBase);
extern void WatchdogEnable(unsigned long ulBase);
extern void WatchdogLock(unsigned long ulBase);
extern void WatchdogUnlock(unsigned long ulBase);
extern tBoolean WatchdogLockState(unsigned long ulBase);
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal);
extern unsigned long WatchdogReloadGet(unsigned long ulBase);
extern unsigned long WatchdogValueGet(unsigned long ulBase);
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
extern void WatchdogIntUnregister(unsigned long ulBase);
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void WatchdogIntClear(unsigned long ulBase);
extern void WatchdogStallEnable(unsigned long ulBase);
extern void WatchdogStallDisable(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __WATCHDOG_H__

227
ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/asmdefs.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// asmdefs.h - Macros to allow assembly code be portable among toolchains.
//
//*****************************************************************************
#ifndef __ASMDEFS_H__
#define __ASMDEFS_H__
//*****************************************************************************
//
// The defines required for code_red.
//
//*****************************************************************************
#ifdef codered
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // codered
//*****************************************************************************
//
// The defines required for EW-ARM.
//
//*****************************************************************************
#ifdef ewarm
//
// Section headers.
//
#define __LIBRARY__ module
#define __TEXT__ rseg CODE:CODE(2)
#define __DATA__ rseg DATA:DATA(2)
#define __BSS__ rseg DATA:DATA(2)
#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
//
// Assembler nmenonics.
//
#define __ALIGN__ alignrom 2
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__ thumb
#define __WORD__ dcd
#define __INLINE_DATA__ data
#endif // ewarm
//*****************************************************************************
//
// The defines required for GCC.
//
//*****************************************************************************
#if defined(gcc)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // gcc
//*****************************************************************************
//
// The defines required for RV-MDK.
//
//*****************************************************************************
#ifdef rvmdk
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
thumb
require8
preserve8
//
// Section headers.
//
#define __LIBRARY__ ;
#define __TEXT__ area ||.text||, code, readonly, align=2
#define __DATA__ area ||.data||, data, align=2
#define __BSS__ area ||.bss||, noinit, align=2
#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
//
// Assembler nmenonics.
//
#define __ALIGN__ align 4
#define __END__ end
#define __EXPORT__ export
#define __IMPORT__ import
#define __LABEL__
#define __STR__ dcb
#define __THUMB_LABEL__
#define __WORD__ dcd
#define __INLINE_DATA__
#endif // rvmdk
//*****************************************************************************
//
// The defines required for Sourcery G++.
//
//*****************************************************************************
#if defined(sourcerygxx)
//
// The assembly code preamble required to put the assembler into the correct
// configuration.
//
.syntax unified
.thumb
//
// Section headers.
//
#define __LIBRARY__ @
#define __TEXT__ .text
#define __DATA__ .data
#define __BSS__ .bss
#define __TEXT_NOROOT__ .text
//
// Assembler nmenonics.
//
#define __ALIGN__ .balign 4
#define __END__ .end
#define __EXPORT__ .globl
#define __IMPORT__ .extern
#define __LABEL__ :
#define __STR__ .ascii
#define __THUMB_LABEL__ .thumb_func
#define __WORD__ .word
#define __INLINE_DATA__
#endif // sourcerygxx
#endif // __ASMDEF_H__

886
ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_adc.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_ADC_H__
#define __HW_ADC_H__
//*****************************************************************************
//
// The following are defines for the ADC register offsets.
//
//*****************************************************************************
#define ADC_O_ADC_CTRL 0x00000000 // ADC control register.
#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting
#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting
#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting
#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting
#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting
#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting
#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting
#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting
#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable
// register
#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable
// register
#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable
// register
#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable
// register
#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable
// register
#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable
// register
#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable
// register
#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable
// register
#define ADC_O_adc_ch0_irq_status \
0x00000044 // Channel 0 interrupt status
// register
#define ADC_O_adc_ch1_irq_status \
0x00000048 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_irq_status \
0x0000004C
#define ADC_O_adc_ch3_irq_status \
0x00000050 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_irq_status \
0x00000054 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_irq_status \
0x00000058
#define ADC_O_adc_ch6_irq_status \
0x0000005C // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_irq_status \
0x00000060 // Channel 7 interrupt status
// register
#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register
#define ADC_O_adc_timer_configuration \
0x00000068 // ADC timer configuration register
#define ADC_O_adc_timer_current_count \
0x00000070 // ADC timer current count register
#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register
#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register
#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register
#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register
#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register
#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register
#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register
#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register
#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register
#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status
// register
#define ADC_O_adc_ch2_fifo_lvl 0x0000009C
#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status
// register
#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status
// register
#define ADC_O_adc_ch5_fifo_lvl 0x000000A8
#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status
// register
#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status
// register
#define ADC_O_ADC_CH_ENABLE 0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the ADC_O_ADC_CTRL register.
//
//******************************************************************************
#define ADC_ADC_CTRL_adc_cap_scale \
0x00000020 // ADC CAP SCALE.
#define ADC_ADC_CTRL_adc_buf_bypass \
0x00000010 // ADC ANA CIO buffer bypass.
// Signal is modelled in ANA TOP.
// When '1': ADC buffer is bypassed.
#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1:
// ADC buffer is enabled.
#define ADC_ADC_CTRL_adc_core_en \
0x00000004 // ANA ADC core en. This signal act
// as glbal enable to ADC CIO. When
// 1: ADC core is enabled.
#define ADC_ADC_CTRL_adc_soft_reset \
0x00000002 // ADC soft reset. When '1' : reset
// ADC internal logic.
#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC
// module is enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_gain register.
//
//******************************************************************************
#define ADC_adc_ch0_gain_adc_channel0_gain_M \
0x00000003 // gain setting for ADC channel 0.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch0_gain_adc_channel0_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_gain register.
//
//******************************************************************************
#define ADC_adc_ch1_gain_adc_channel1_gain_M \
0x00000003 // gain setting for ADC channel 1.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch1_gain_adc_channel1_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_gain register.
//
//******************************************************************************
#define ADC_adc_ch2_gain_adc_channel2_gain_M \
0x00000003 // gain setting for ADC channel 2.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch2_gain_adc_channel2_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_gain register.
//
//******************************************************************************
#define ADC_adc_ch3_gain_adc_channel3_gain_M \
0x00000003 // gain setting for ADC channel 3.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch3_gain_adc_channel3_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_gain register.
//
//******************************************************************************
#define ADC_adc_ch4_gain_adc_channel4_gain_M \
0x00000003 // gain setting for ADC channel 4
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch4_gain_adc_channel4_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_gain register.
//
//******************************************************************************
#define ADC_adc_ch5_gain_adc_channel5_gain_M \
0x00000003 // gain setting for ADC channel 5.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch5_gain_adc_channel5_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_gain register.
//
//******************************************************************************
#define ADC_adc_ch6_gain_adc_channel6_gain_M \
0x00000003 // gain setting for ADC channel 6
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch6_gain_adc_channel6_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_gain register.
//
//******************************************************************************
#define ADC_adc_ch7_gain_adc_channel7_gain_M \
0x00000003 // gain setting for ADC channel 7.
// when "00": 1x when "01: 2x when
// "10":3x when "11" 4x
#define ADC_adc_ch7_gain_adc_channel7_gain_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_en register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \
0x0000000F // interrupt enable register for
// per ADC channel bit 3: when '1'
// -> enable FIFO overflow interrupt
// bit 2: when '1' -> enable FIFO
// underflow interrupt bit 1: when
// "1' -> enable FIFO empty
// interrupt bit 0: when "1" ->
// enable FIFO full interrupt
#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_irq_status register.
//
//******************************************************************************
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \
0x0000000F // interrupt status register for
// per ADC channel. Interrupt status
// can be cleared on write. bit 3:
// when value '1' is written ->
// would clear FIFO overflow
// interrupt status in the next
// cycle. if same interrupt is set
// in the same cycle then interurpt
// would be set and clear command
// will be ignored. bit 2: when
// value '1' is written -> would
// clear FIFO underflow interrupt
// status in the next cycle. bit 1:
// when value '1' is written ->
// would clear FIFO empty interrupt
// status in the next cycle. bit 0:
// when value '1' is written ->
// would clear FIFO full interrupt
// status in the next cycle.
#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_dma_mode_en register.
//
//******************************************************************************
#define ADC_adc_dma_mode_en_DMA_MODEenable_M \
0x000000FF // this register enable DMA mode.
// when '1' respective ADC channel
// is enabled for DMA. When '0' only
// interrupt mode is enabled. Bit 0:
// channel 0 DMA mode enable. Bit 1:
// channel 1 DMA mode enable. Bit 2:
// channel 2 DMA mode enable. Bit 3:
// channel 3 DMA mode enable. bit 4:
// channel 4 DMA mode enable. bit 5:
// channel 5 DMA mode enable. bit 6:
// channel 6 DMA mode enable. bit 7:
// channel 7 DMA mode enable.
#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_configuration register.
//
//******************************************************************************
#define ADC_adc_timer_configuration_timeren \
0x02000000 // when '1' timer is enabled.
#define ADC_adc_timer_configuration_timerreset \
0x01000000 // when '1' reset timer.
#define ADC_adc_timer_configuration_timercount_M \
0x00FFFFFF // Timer count configuration. 17
// bit counter is supported. Other
// MSB's are redundent.
#define ADC_adc_timer_configuration_timercount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_timer_current_count register.
//
//******************************************************************************
#define ADC_adc_timer_current_count_timercurrentcount_M \
0x0001FFFF // Timer count configuration
#define ADC_adc_timer_current_count_timercurrentcount_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel0FIFODATA register.
//
//******************************************************************************
#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel1FIFODATA register.
//
//******************************************************************************
#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel2FIFODATA register.
//
//******************************************************************************
#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel3FIFODATA register.
//
//******************************************************************************
#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel4FIFODATA register.
//
//******************************************************************************
#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel5FIFODATA register.
//
//******************************************************************************
#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel6FIFODATA register.
//
//******************************************************************************
#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_channel7FIFODATA register.
//
//******************************************************************************
#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \
0xFFFFFFFF // read to this register would
// return ADC data along with time
// stamp information in following
// format: bits [13:0] : ADC sample
// bits [31:14]: : time stamp per
// ADC sample
#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch0_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch1_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch2_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch3_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch4_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch5_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch6_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// ADC_O_adc_ch7_fifo_lvl register.
//
//******************************************************************************
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \
0x00000007 // This register shows current FIFO
// level. FIFO is 4 word wide.
// Possible supported levels are :
// 0x0 to 0x3
#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0
#endif // __HW_ADC_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_aes.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_AES_H__
#define __HW_AES_H__
//*****************************************************************************
//
// The following are defines for the AES_P register offsets.
//
//*****************************************************************************
#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third
// key
#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit
// key) / CBC-MAC third key (MSW)
#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC
// third key (LSW)
#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit
// key) / CBC-MAC third key
#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit
// key) + CCM/CBC-MAC second key
// (MSW) / Hash Key input (MSW)
#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key
// (LSW) / Hash Key input (LSW)
#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key /
// Hash Key input
#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key)
#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key)
#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key)
#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key)
#define AES_O_KEY1_2 0x00000030 // Key
#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key)
#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key)
#define AES_O_KEY1_1 0x0000003C // Key
#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input
// (LSW)
#define AES_O_IV_IN_1 0x00000044 // Initialization vector input
#define AES_O_IV_IN_2 0x00000048 // Initialization vector input
#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input
// (MSW)
#define AES_O_CTRL 0x00000050 // register determines the mode of
// operation of the AES Engine
#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers
// (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The
// authentication length register
// store the authentication data
// length in bytes for combined
// modes only (GCM or CCM) Supported
// AAD-lengths for CCM are from 0 to
// (2^16 - 2^8) bytes. For GCM any
// value up to (2^32 - 1) bytes can
// be used. Once processing with
// this context is started@@ this
// length decrements to zero. A
// write to this register triggers
// the engine to start using this
// context for GCM and CCM. For XTS
// this register is optionally used
// to load ‘j’. Loading of ‘j’ is
// only required if ‘j’ != 0. ‘j’ is
// a 28-bit value and must be
// written to bits [31-4] of this
// register. ‘j’ represents the
// sequential number of the 128-bit
// block inside the data unit. For
// the first block in a unit@@ this
// value is zero. It is not required
// to provide a ‘j’ for each new
// data block within a unit. Note
// that it is possible to start with
// a ‘j’ unequal to zero; refer to
// Table 4 for more details. For a
// Host read operation@@ these
// registers return all-zeroes.
#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write
// plaintext/ciphertext (MSW)
#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write
// plaintext/ciphertext
#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write
// plaintext/ciphertext (LSW)
#define AES_O_TAG_OUT_0 0x00000070
#define AES_O_TAG_OUT_1 0x00000074
#define AES_O_TAG_OUT_2 0x00000078
#define AES_O_TAG_OUT_3 0x0000007C
#define AES_O_REVISION 0x00000080 // Register AES_REVISION
#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This
// register configures the DMA
// signals and controls the IDLE and
// reset logic
#define AES_O_SYSSTATUS 0x00000088
#define AES_O_IRQSTATUS 0x0000008C // This register indicates the
// interrupt status. If one of the
// interrupt bits is set the
// interrupt output will be asserted
#define AES_O_IRQENABLE 0x00000090 // This register contains an enable
// bit for each unique interrupt
// generated by the module. It
// matches the layout of
// AES_IRQSTATUS register. An
// interrupt is enabled when the bit
// in this register is set to ‘1’.
// An interrupt that is enabled is
// propagated to the SINTREQUEST_x
// output. All interrupts need to be
// enabled explicitly by writing
// this register.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_6 register.
//
//******************************************************************************
#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_7 register.
//
//******************************************************************************
#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_4 register.
//
//******************************************************************************
#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_5 register.
//
//******************************************************************************
#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_2 register.
//
//******************************************************************************
#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_3 register.
//
//******************************************************************************
#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_0 register.
//
//******************************************************************************
#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY2_1 register.
//
//******************************************************************************
#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY2_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_6 register.
//
//******************************************************************************
#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_6_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_7 register.
//
//******************************************************************************
#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_7_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_4 register.
//
//******************************************************************************
#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_4_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_5 register.
//
//******************************************************************************
#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_5_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_2 register.
//
//******************************************************************************
#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_3 register.
//
//******************************************************************************
#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_3_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_0 register.
//
//******************************************************************************
#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_KEY1_1 register.
//
//******************************************************************************
#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data
#define AES_KEY1_1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
//
//******************************************************************************
#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
//
//******************************************************************************
#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
//
//******************************************************************************
#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
//
//******************************************************************************
#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data
#define AES_IV_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_CTRL register.
//
//******************************************************************************
#define AES_CTRL_CONTEXT_READY \
0x80000000 // If ‘1’@@ this read-only status
// bit indicates that the context
// data registers can be overwritten
// and the host is permitted to
// write the next context.
#define AES_CTRL_SVCTXTRDY \
0x40000000 // If ‘1’@@ this read-only status
// bit indicates that an AES
// authentication TAG and/or IV
// block(s) is/are available for the
// host to retrieve. This bit is
// only asserted if the
// ‘save_context’ bit is set to ‘1’.
// The bit is mutual exclusive with
// the ‘context_ready’ bit.
#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate
// that an authentication TAG or
// result IV needs to be stored as a
// result context. If this bit is
// set@@ context output DMA and/or
// interrupt will be asserted if the
// operation is finished and related
// signals are enabled.
#define AES_CTRL_CCM_M 0x01C00000 // Defines “M� that indicated the
// length of the authentication
// field for CCM operations; the
// authentication field length
// equals two times (the value of
// CCM-M plus one). Note that the
// AES Engine always returns a
// 128-bit authentication field@@ of
// which the M least significant
// bytes are valid. All values are
// supported.
#define AES_CTRL_CCM_S 22
#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L� that indicated the
// width of the length field for CCM
// operations; the length field in
// bytes equals the value of CMM-L
// plus one. Supported values for L
// are (programmed value): 2 (1)@@ 4
// (3) and 8 (7).
#define AES_CTRL_CCM_L_S 19
#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a
// combined mode@@ using AES for
// both authentication and
// encryption. No additional mode
// selection is required. 0 Other
// mode selected 1 ccm mode selected
#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is
// a combined mode@@ using the
// Galois field multiplier GF(2^128)
// for authentication and AES-CTR
// mode for encryption@@ the bits
// specify the GCM mode. 0x0 No
// operation 0x1 GHASH with H loaded
// and Y0-encrypted forced to zero
// 0x2 GHASH with H loaded and
// Y0-encrypted calculated
// internally 0x3 Autonomous GHASH
// (both H and Y0-encrypted
// calculated internally)
#define AES_CTRL_GCM_S 16
#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the
// Direction bit must be set to ‘1’
// for this mode. 0 Other mode
// selected 1 cbcmac mode selected
#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f9 selected
#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the
// AES key size must be set to
// 128-bit for this mode. 0 Other
// mode selected 1 f8 selected
#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected;
// the bits specify the XTS mode.01
// = Previous/intermediate tweak
// value and ‘j’ loaded (value is
// loaded via IV@@ j is loaded via
// the AAD length register) 0x0 No
// operation 0x1
// Previous/intermediate tweak value
// and ‘j’ loaded (value is loaded
// via IV@@ j is loaded via the AAD
// length register) 0x2 Key2@@ i and
// j loaded (i is loaded via IV@@ j
// is loaded via the AAD length
// register) 0x3 Key2 and i loaded@@
// j=0 (i is loaded via IV)
#define AES_CTRL_XTS_S 11
#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback
// mode (CFB128) is selected. 0
// other mode selected 1 cfb
// selected
#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM)
// is selected@@ this is a counter
// mode with a 16-bit wide counter.
// 0 Other mode selected. 1 ICM mode
// selected
#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for
// AES-CTR mode 0x0 Counter is 32
// bits 0x1 Counter is 64 bits 0x2
// Counter is 128 bits 0x3 Counter
// is 192 bits
#define AES_CTRL_CTR_WIDTH_S 7
#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for
// GCM and CCM@@ when
// encryption/decryption is
// required. 0 Other mode selected 1
// Counter mode
#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc
// mode
#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is
// 128 bits. 0x2 Key is 192 bits 0x3
// Key is 256
#define AES_CTRL_KEY_SIZE_S 3
#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt
// operation is performed. If set to
// ‘0’ a decrypt operation is
// performed. Read 0 decryption is
// selected Read 1 Encryption is
// selected
#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status
// bit indicates that the 16-byte
// input buffer is empty@@ and the
// host is permitted to write the
// next block of data.
#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status
// bit indicates that an AES output
// block is available for the host
// to retrieve.
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_C_LENGTH_1 register.
//
//******************************************************************************
#define AES_C_LENGTH_1_LENGTH_M \
0x1FFFFFFF // Data length (MSW) length
// registers (LSW and MSW) store the
// cryptographic data length in
// bytes for all modes. Once
// processing with this context is
// started@@ this length decrements
// to zero. Data lengths up to (2^61
// – 1) bytes are allowed. For GCM@@
// any value up to 2^36 - 32 bytes
// can be used. This is because a
// 32-bit counter mode is used; the
// maximum number of 128-bit blocks
// is 2^32 – 2@@ resulting in a
// maximum number of bytes of 2^36 -
// 32. A write to this register
// triggers the engine to start
// using this context. This is valid
// for all modes except GCM and CCM.
// Note that for the combined
// modes@@ this length does not
// include the authentication only
// data; the authentication length
// is specified in the
// AES_AUTH_LENGTH register below.
// All modes must have a length > 0.
// For the combined modes@@ it is
// allowed to have one of the
// lengths equal to zero. For the
// basic encryption modes
// (ECB/CBC/CTR/ICM/CFB128) it is
// allowed to program zero to the
// length field; in that case the
// length is assumed infinite. All
// data must be byte (8-bit)
// aligned; bit aligned data streams
// are not supported by the AES
// Engine. For a Host read
// operation@@ these registers
// return all-zeroes.
#define AES_C_LENGTH_1_LENGTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// AES_O_AUTH_LENGTH register.
//
//******************************************************************************
#define AES_AUTH_LENGTH_AUTH_M \
0xFFFFFFFF // data
#define AES_AUTH_LENGTH_AUTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_0 register.
//
//******************************************************************************
#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_0_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_1 register.
//
//******************************************************************************
#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_1_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_2 register.
//
//******************************************************************************
#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_2_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_DATA_IN_3 register.
//
//******************************************************************************
#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt
#define AES_DATA_IN_3_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register.
//
//******************************************************************************
#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_0_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register.
//
//******************************************************************************
#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_1_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register.
//
//******************************************************************************
#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW)
#define AES_TAG_OUT_2_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register.
//
//******************************************************************************
#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW)
#define AES_TAG_OUT_3_HASH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_REVISION register.
//
//******************************************************************************
#define AES_REVISION_SCHEME_M 0xC0000000
#define AES_REVISION_SCHEME_S 30
#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
// compatible module family. If
// there is no level of software
// compatibility a new Func number
// (and hence REVISION) should be
// assigned.
#define AES_REVISION_FUNC_S 16
#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by
// IP design owner. RTL follows a
// numbering such as X.Y.R.Z which
// are explained in this table. R
// changes ONLY when: (1) PDS
// uploads occur which may have been
// due to spec changes (2) Bug fixes
// occur (3) Resets to '0' when X or
// Y changes. Design team has an
// internal 'Z' (customer invisible)
// number which increments on every
// drop that happens due to DV and
// RTL updates. Z resets to 0 when R
// increments.
#define AES_REVISION_R_RTL_S 11
#define AES_REVISION_X_MAJOR_M \
0x00000700 // Major Revision (X)@@ maintained
// by IP specification owner. X
// changes ONLY when: (1) There is a
// major feature addition. An
// example would be adding Master
// Mode to Utopia Level2. The Func
// field (or Class/Type in old PID
// format) will remain the same. X
// does NOT change due to: (1) Bug
// fixes (2) Change in feature
// parameters.
#define AES_REVISION_X_MAJOR_S 8
#define AES_REVISION_CUSTOM_M 0x000000C0
#define AES_REVISION_CUSTOM_S 6
#define AES_REVISION_Y_MINOR_M \
0x0000003F // Minor Revision (Y)@@ maintained
// by IP specification owner. Y
// changes ONLY when: (1) Features
// are scaled (up or down).
// Flexibility exists in that this
// feature scalability may either be
// represented in the Y change or a
// specific register in the IP that
// indicates which features are
// exactly available. (2) When
// feature creeps from Is-Not list
// to Is list. But this may not be
// the case once it sees silicon; in
// which case X will change. Y does
// NOT change due to: (1) Bug fixes
// (2) Typos or clarifications (3)
// major functional/feature
// change/addition/deletion. Instead
// these changes may be reflected
// via R@@ S@@ X as applicable. Spec
// owner maintains a
// customer-invisible number 'S'
// which changes due to: (1)
// Typos/clarifications (2) Bug
// documentation. Note that this bug
// is not due to a spec change but
// due to implementation.
// Nevertheless@@ the spec tracks
// the IP bugs. An RTL release (say
// for silicon PG1.1) that occurs
// due to bug fix should document
// the corresponding spec number
// (X.Y.S) in its release notes.
#define AES_REVISION_Y_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSCONFIG register.
//
//******************************************************************************
#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \
0x00000200 // If set to '1' the two context
// out requests
// (dma_req_context_out_en@@ Bit [8]
// above@@ and context_out interrupt
// enable@@ Bit [3] of AES_IRQENABLE
// register) are mapped on the
// corresponding data output request
// bit. In this case@@ the original
// ‘context out’ bit values are
// ignored.
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
0x00000100 // If set to ‘1’@@ the DMA context
// output request is enabled (for
// context data out@@ e.g. TAG for
// authentication modes). 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // If set to ‘1’@@ the DMA context
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // If set to ‘1’@@ the DMA output
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // If set to ‘1’@@ the DMA input
// request is enabled. 0 Dma
// disabled 1 Dma enabled
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_SYSSTATUS register.
//
//******************************************************************************
#define AES_SYSSTATUS_RESETDONE \
0x00000001
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQSTATUS register.
//
//******************************************************************************
#define AES_IRQSTATUS_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQSTATUS_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQSTATUS_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
//******************************************************************************
//
// The following are defines for the bit fields in the AES_O_IRQENABLE register.
//
//******************************************************************************
#define AES_IRQENABLE_CONTEXT_OUT \
0x00000008 // This bit indicates
// authentication tag (and IV)
// interrupt(s) is/are active and
// triggers the interrupt output.
#define AES_IRQENABLE_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define AES_IRQENABLE_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
#endif // __HW_AES_H__

745
ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_config.h Executable file
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@ -0,0 +1,745 @@
/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_APPS_CONFIG_H__
#define __HW_APPS_CONFIG_H__
//*****************************************************************************
//
// The following are defines for the APPS_CONFIG register offsets.
//
//*****************************************************************************
#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \
0x00000000 // Patch trap address Register
// array
#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \
0x00000078
#define APPS_CONFIG_O_FAULT_STATUS_REG \
0x0000007C
#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \
0x00000080
#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \
0x00000084
#define APPS_CONFIG_O_DMA_DONE_INT_MASK \
0x0000008C
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \
0x00000090
#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \
0x00000094
#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \
0x00000098
#define APPS_CONFIG_O_DMA_DONE_INT_ACK \
0x0000009C
#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \
0x000000A0
#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \
0x000000A4
#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \
0x000000A8
#define APPS_CONFIG_O_RESERVD_REG_0 \
0x000000AC
#define APPS_CONFIG_O_GPT_TRIG_SEL \
0x000000B0
#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \
0x000000B4
#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \
0x000000B8
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \
0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address
// PATCH_TRAP_ADDR_REG[n][31:0] from
// Idcode bus. The exception routine
// should take care to jump to the
// location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_PATCH_TRAP_EN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \
0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus
// fault is generated for the
// address PATCH_TRAP_ADD[n][31:0]
// from Idcode bus. The exception
// routine should take care to jump
// to the location where the patch
// correspond to this address is
// kept.
#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \
0x0000003E // This field shows because of
// which patch trap address the
// bus_fault is generated. If the
// PATCH_ERR bit is set, then it
// means the bus fault is generated
// because of
// PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX]
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1
#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \
0x00000001 // This bit is set when there is a
// bus fault because of patched
// address access to the Apps boot
// rom. Write 0 to clear this
// register.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \
0x00000001 // This bit is set when there is a
// an error in memss write access.
// And the address causing this
// error is captured in
// MEMSS_ERR_ADDR_REG. To capture
// the next error address one have
// to clear this bit.
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \
0x0000F000 // 1= disable corresponding
// interrupt;0 = interrupt enabled
// bit 14: ADC channel 7 interrupt
// enable/disable bit 13: ADC
// channel 5 interrupt
// enable/disable bit 12: ADC
// channel 3 interrupt
// enable/disable bit 11: ADC
// channel 1 interrupt
// enable/disable
#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \
0x00000800 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \
0x00000400 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \
0x00000200 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \
0x00000100 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \
0x00000080 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \
0x00000040 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \
0x00000020 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \
0x00000010 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \
0x00000008 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \
0x00000004 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \
0x00000002 // 1= disable corresponding
// interrupt;0 = interrupt enabled
#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \
0x00000001 // 1= disable corresponding
// interrupt;0 = interrupt enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \
0x0000F000 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ bit 13: ADC channel 5
// DMA Done IRQ bit 12: ADC channel
// 3 DMA Done IRQ bit 11: ADC
// channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \
0x00000800 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \
0x00000400 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \
0x00000200 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \
0x00000100 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000080 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000040 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \
0x00000020 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \
0x00000010 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \
0x00000008 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \
0x00000004 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \
0x00000002 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \
0x00000001 // write 1 to set mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \
0x0000F000 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect bit 14: ADC channel 7 DMA
// Done IRQ mask bit 13: ADC channel
// 5 DMA Done IRQ mask bit 12: ADC
// channel 3 DMA Done IRQ mask bit
// 11: ADC channel 1 DMA Done IRQ
// mask
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \
0x00000800 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \
0x00000400 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \
0x00000200 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \
0x00000100 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000080 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000040 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000020 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000010 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \
0x00000008 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \
0x00000004 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \
0x00000002 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \
0x00000001 // write 1 to clear mask of the
// corresponding DMA DONE IRQ;0 = no
// effect
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \
0xFFFFFFFF // write 1 or 0 to clear all
// DMA_DONE interrupt;
#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_ACK register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \
0x0000F000 // write 1 to clear corresponding
// interrupt; 0 = no effect; bit 14:
// ADC channel 7 DMA Done IRQ bit
// 13: ADC channel 5 DMA Done IRQ
// bit 12: ADC channel 3 DMA Done
// IRQ bit 11: ADC channel 1 DMA
// Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \
0x00000800 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \
0x00000400 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \
0x00000200 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \
0x00000100 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \
0x00000080 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \
0x00000040 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \
0x00000020 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \
0x00000010 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \
0x00000008 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \
0x00000004 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \
0x00000002 // write 1 to clear corresponding
// interrupt; 0 = no effect;
#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \
0x00000001 // write 1 to clear corresponding
// interrupt; 0 = no effect;
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \
0x0000F000 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask bit 14: ADC
// channel 7 DMA Done IRQ bit 13:
// ADC channel 5 DMA Done IRQ bit
// 12: ADC channel 3 DMA Done IRQ
// bit 11: ADC channel 1 DMA Done
// IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \
0x00000800 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \
0x00000400 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \
0x00000200 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \
0x00000100 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000080 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000040 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000020 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000010 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \
0x00000008 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \
0x00000004 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \
0x00000002 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \
0x00000001 // 1= corresponding interrupt is
// active and not masked. read is
// non-destructive;0 = corresponding
// interrupt is inactive or masked
// by DMA_DONE_INT mask
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register.
//
//******************************************************************************
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \
0x0000F000 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive bit 14: ADC channel 7
// DMA Done IRQ bit 13: ADC channel
// 5 DMA Done IRQ bit 12: ADC
// channel 3 DMA Done IRQ bit 11:
// ADC channel 1 DMA Done IRQ
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \
0x00000800 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \
0x00000400 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \
0x00000200 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \
0x00000100 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000080 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000040 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \
0x00000020 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \
0x00000010 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \
0x00000008 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \
0x00000004 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \
0x00000002 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \
0x00000001 // 1= corresponding interrupt is
// active. read is non-destructive;0
// = corresponding interrupt is
// inactive
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register.
//
//******************************************************************************
#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \
0x00000001 // Write 1 to clear the LSB of
// FAULT_STATUS_REG
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_RESERVD_REG_0 register.
//
//******************************************************************************
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_GPT_TRIG_SEL register.
//
//******************************************************************************
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \
0x000000FF // This bit is implemented for GPT
// trigger mode select. GPT IP
// support 2 modes: RTC mode and
// external trigger. When this bit
// is set to logic '1': enable
// external trigger mode for APPS
// GPT CP0 and CP1 pin. bit 0: when
// set '1' enable external GPT
// trigger 0 on GPIO0 CP0 pin else
// RTC mode is selected. bit 1: when
// set '1' enable external GPT
// trigger 1 on GPIO0 CP1 pin else
// RTC mode is selected. bit 2: when
// set '1' enable external GPT
// trigger 2 on GPIO1 CP0 pin else
// RTC mode is selected. bit 3: when
// set '1' enable external GPT
// trigger 3 on GPIO1 CP1 pin else
// RTC mode is selected. bit 4: when
// set '1' enable external GPT
// trigger 4 on GPIO2 CP0 pin else
// RTC mode is selected. bit 5: when
// set '1' enable external GPT
// trigger 5 on GPIO2 CP1 pin else
// RTC mode is selected. bit 6: when
// set '1' enable external GPT
// trigger 6 on GPIO3 CP0 pin else
// RTC mode is selected. bit 7: when
// set '1' enable external GPT
// trigger 7 on GPIO3 CP1 pin else
// RTC mode is selected.
#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \
0x00000007 // Capture data from d2d_spare pads
#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register.
//
//******************************************************************************
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \
0x00000007 // Send data to d2d_spare pads -
// eventually this will get
// registered in top die
#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0
#endif // __HW_APPS_CONFIG_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_rcm.h Normal file → Executable file
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_camera.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_CAMERA_H__
#define __HW_CAMERA_H__
//*****************************************************************************
//
// The following are defines for the CAMERA register offsets.
//
//*****************************************************************************
#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP
// revision code ( Parallel Mode)
#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the
// various parameters of the OCP
// interface (CCP and Parallel Mode)
#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status
// information about the module
// excluding the interrupt status
// information (CCP and Parallel
// Mode)
#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups
// all the status of the module
// internal events that can generate
// an interrupt (CCP & Parallel
// Mode)
#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register
// allows to enable/disable the
// module internal sources of
// interrupt on an event-by-event
// basis (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the
// various parameters of the Camera
// Core block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA
// interface of the Camera Core
// block (CCP & Parallel Mode)
#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value
// of the clock divisor used to
// generate the external clock
// (Parallel Mode)
#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to
// the FIFO and read from the FIFO
// (CCP & Parallel Mode)
#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status
// of some important variables of
// the camera core module (CCP &
// Parallel Mode)
#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values
// of the generic parameters of the
// module
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_REVISION register.
//
//******************************************************************************
#define CAMERA_CC_REVISION_REV_M \
0x000000FF // IP revision [7:4] Major revision
// [3:0] Minor revision Examples:
// 0x10 for 1.0 0x21 for 2.1
#define CAMERA_CC_REVISION_REV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSCONFIG register.
//
//******************************************************************************
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \
0x00000018 // Slave interface power management
// req/ack control """00""
// Force-idle. An idle request is
// acknoledged unconditionally"
// """01"" No-idle. An idle request
// is never acknowledged" """10""
// reserved (Smart-idle not
// implemented)"
#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3
#define CAMERA_CC_SYSCONFIG_SOFT_RESET \
0x00000002 // Software reset. Set this bit to
// 1 to trigger a module reset. The
// bit is automatically reset by the
// hardware. During reset it always
// returns 0. 0 Normal mode 1 The
// module is reset
#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \
0x00000001 // Internal OCP clock gating
// strategy 0 OCP clock is
// free-running 1 Automatic OCP
// clock gating strategy is applied
// based on the OCP interface
// activity
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_SYSSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \
0x00000001 // Internal Reset Monitoring 0
// Internal module reset is on-going
// 1 Reset completed
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQSTATUS register.
//
//******************************************************************************
#define CAMERA_CC_IRQSTATUS_FS_IRQ \
0x00080000 // Frame Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LE_IRQ \
0x00040000 // Line End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_LS_IRQ \
0x00020000 // Line Start has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FE_IRQ \
0x00010000 // Frame End has occurred 0 Event
// false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \
0x00000800 // FSP code error 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \
0x00000400 // Frame Height Error 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \
0x00000200 // False Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \
0x00000100 // Shifted Synchronization Code 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \
0x00000010 // FIFO is not empty 0 Event false
// "1 Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \
0x00000008 // FIFO is full 0 Event false "1
// Event is true (""pending"")" 0
// Event status bit unchanged 1
// Event status bit is reset
#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \
0x00000004 // FIFO threshold has been reached
// 0 Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \
0x00000002 // FIFO overflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \
0x00000001 // FIFO underflow has occurred 0
// Event false "1 Event is true
// (""pending"")" 0 Event status bit
// unchanged 1 Event status bit is
// reset
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_IRQENABLE register.
//
//******************************************************************************
#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \
0x00080000 // Frame Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \
0x00040000 // Line End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \
0x00020000 // Line Start Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \
0x00010000 // Frame End Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \
0x00000800 // FSP code Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \
0x00000400 // Frame Height Error Interrupt
// Enable 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \
0x00000200 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \
0x00000100 // False Synchronization Code
// Interrupt Enable 0 Event is
// masked 1 Event generates an
// interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \
0x00000010 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \
0x00000008 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \
0x00000004 // FIFO Threshold Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \
0x00000002 // FIFO Overflow Interrupt Enable 0
// Event is masked 1 Event generates
// an interrupt when it occurs
#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \
0x00000001 // FIFO Underflow Interrupt Enable
// 0 Event is masked 1 Event
// generates an interrupt when it
// occurs
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \
0x00080000 // Synchronize all camera sensor
// inputs This must be set during
// the configuration phase before
// CC_EN set to '1'. This can be
// used in very high frequency to
// avoid dependancy to the IO
// timings. 0 No synchro (most of
// applications) 1 Synchro enabled
// (should never be required)
#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite
// states machines of the camera
// core module - by writing a 1 to
// this bit. must be applied when
// CC_EN = 0 Reads returns 0
#define CAMERA_CC_CTRL_CC_FRAME_TRIG \
0x00020000 // Set the modality in which CC_EN
// works when a disabling of the
// sensor camera core is wanted "If
// CC_FRAME_TRIG = 1 by writing
// ""0"" to CC_EN" the module is
// disabled at the end of the frame
// "If CC_FRAME_TRIG = 0 by writing
// ""0"" to CC_EN" the module is
// disabled immediately
#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of
// the camera core module "By
// writing ""1"" to this field the
// module is enabled." "By writing
// ""0"" to this field the module is
// disabled at" the end of the frame
// if CC_FRAM_TRIG =1 and is
// disabled immediately if
// CC_FRAM_TRIG = 0
#define CAMERA_CC_CTRL_NOBT_SYNCHRO \
0x00002000 // Enables to start at the
// beginning of the frame or not in
// NoBT 0 Acquisition starts when
// Vertical synchro is high 1
// Acquisition starts when Vertical
// synchro goes from low to high
// (beginning of the frame) -
// Recommended.
#define CAMERA_CC_CTRL_BT_CORRECT \
0x00001000 // Enables the correction within
// the sync codes in BT mode 0
// correction is not enabled 1
// correction is enabled
#define CAMERA_CC_CTRL_PAR_ORDERCAM \
0x00000800 // Enables swap between image-data
// in parallel mode 0 swap is not
// enabled 1 swap is enabled
#define CAMERA_CC_CTRL_PAR_CLK_POL \
0x00000400 // Inverts the clock coming from
// the sensor in parallel mode 0
// clock not inverted - data sampled
// on rising edge 1 clock inverted -
// data sampled on falling edge
#define CAMERA_CC_CTRL_NOBT_HS_POL \
0x00000200 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_HS is
// active high 1 CAM_P_HS is active
// low
#define CAMERA_CC_CTRL_NOBT_VS_POL \
0x00000100 // Sets the polarity of the
// synchronization signals in NOBT
// parallel mode 0 CAM_P_VS is
// active high 1 CAM_P_VS is active
// low
#define CAMERA_CC_CTRL_PAR_MODE_M \
0x0000000E // Sets the Protocol Mode of the
// Camera Core module in parallel
// mode (when CCP_MODE = 0) """000""
// Parallel NOBT 8-bit" """001""
// Parallel NOBT 10-bit" """010""
// Parallel NOBT 12-bit" """011""
// reserved" """100"" Parallet BT
// 8-bit" """101"" Parallel BT
// 10-bit" """110"" reserved"
// """111"" FIFO test mode. Refer to
// Table 12 - FIFO Write and Read
// access"
#define CAMERA_CC_CTRL_PAR_MODE_S 1
#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode
// 0 CCP mode disabled 1 CCP mode
// enabled
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_DMA register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_DMA_DMA_EN \
0x00000100 // Sets the number of dma request
// lines 0 DMA interface disabled
// The DMA request line stays
// inactive 1 DMA interface enabled
// The DMA request line is
// operational
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \
0x0000007F // Sets the threshold of the FIFO
// the assertion of the dmarequest
// line takes place when the
// threshold is reached.
// """0000000"" threshold set to 1"
// """0000001"" threshold set to 2"
// … """1111111"" threshold set to
// 128"
#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_CTRL_XCLK register.
//
//******************************************************************************
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \
0x0000001F // Sets the clock divisor value for
// CAM_XCLK generation. based on
// CAM_MCK (value of CAM_MCLK is
// 96MHz) """00000"" CAM_XCLK Stable
// Low Level" Divider not enabled
// """00001"" CAM_XCLK Stable High
// Level" Divider not enabled from 2
// to 30 CAM_XCLK = CAM_MCLK /
// XCLK_DIV """11111"" Bypass -
// CAM_XCLK = CAM_MCLK"
#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_FIFO_DATA register.
//
//******************************************************************************
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \
0xFFFFFFFF // Writes the 32-bit word into the
// FIFO Reads the 32-bit word from
// the FIFO
#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the CAMERA_O_CC_TEST register.
//
//******************************************************************************
#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \
0xFF000000 // FIFO READ Pointer This field
// shows the value of the FIFO read
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24
#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \
0x00FF0000 // FIFO WRITE pointer This field
// shows the value of the FIFO write
// pointer Expected value ranges
// from 0 to 127
#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16
#define CAMERA_CC_TEST_FIFO_LEVEL_M \
0x0000FF00 // FIFO level (how many 32-bit
// words the FIFO contains) This
// field shows the value of the FIFO
// level and can assume values from
// 0 to 128
#define CAMERA_CC_TEST_FIFO_LEVEL_S 8
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \
0x000000FF // FIFO level peak This field shows
// the max value of the FIFO level
// and can assume values from 0 to
// 128
#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// CAMERA_O_CC_GEN_PAR register.
//
//******************************************************************************
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \
0x00000007 // Camera Core FIFO DEPTH generic
// parameter
#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0
#endif // __HW_CAMERA_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_DES_H__
#define __HW_DES_H__
//*****************************************************************************
//
// The following are defines for the DES_P register offsets.
//
//*****************************************************************************
#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key
#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key
#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key
#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key
#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit
// key/192-bit key
#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit
// key/192-bit key
#define DES_O_IV_L 0x00000018 // Initialization vector LSW
#define DES_O_IV_H 0x0000001C // Initialization vector MSW
#define DES_O_CTRL 0x00000020
#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data
// length in bytes for all modes.
// Once processing is started with
// this context this length
// decrements to zero. Data lengths
// up to (2^32 – 1) bytes are
// allowed. A write to this register
// triggers the engine to start
// using this context. For a Host
// read operation these registers
// return all-zeroes.
#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write
// encrypted/decrypted data.
#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write
// encrypted/decrypted data.
#define DES_O_REVISION 0x00000030
#define DES_O_SYSCONFIG 0x00000034
#define DES_O_SYSSTATUS 0x00000038
#define DES_O_IRQSTATUS 0x0000003C // This register indicates the
// interrupt status. If one of the
// interrupt bits is set the
// interrupt output will be asserted
#define DES_O_IRQENABLE 0x00000040 // This register contains an enable
// bit for each unique interrupt
// generated by the module. It
// matches the layout of
// DES_IRQSTATUS register. An
// interrupt is enabled when the bit
// in this register is set to 1
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_L register.
//
//******************************************************************************
#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3
#define DES_KEY3_L_KEY3_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY3_H register.
//
//******************************************************************************
#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3
#define DES_KEY3_H_KEY3_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_L register.
//
//******************************************************************************
#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2
#define DES_KEY2_L_KEY2_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY2_H register.
//
//******************************************************************************
#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2
#define DES_KEY2_H_KEY2_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_L register.
//
//******************************************************************************
#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1
#define DES_KEY1_L_KEY1_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_KEY1_H register.
//
//******************************************************************************
#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1
#define DES_KEY1_H_KEY1_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_L register.
//
//******************************************************************************
#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC
// CFB modes
#define DES_IV_L_IV_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IV_H register.
//
//******************************************************************************
#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC
// CFB modes
#define DES_IV_H_IV_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_CTRL register.
//
//******************************************************************************
#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit
// indicates that the context data
// registers can be overwritten and
// the host is permitted to write
// the next context.
#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0
// ecb mode 0x1 cbc mode 0x2 cfb
// mode 0x3 reserved
#define DES_CTRL_MODE_S 4
#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
// encryption/decryption. 0 des mode
// 1 tdes mode
#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0
// decryption is selected 1
// Encryption is selected
#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to
// encrypt/decrypt data
#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data
// decrypted/encrypted ready
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_LENGTH register.
//
//******************************************************************************
#define DES_LENGTH_LENGTH_M 0xFFFFFFFF
#define DES_LENGTH_LENGTH_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_L register.
//
//******************************************************************************
#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption
#define DES_DATA_L_DATA_L_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_DATA_H register.
//
//******************************************************************************
#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption
#define DES_DATA_H_DATA_H_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_REVISION register.
//
//******************************************************************************
#define DES_REVISION_SCHEME_M 0xC0000000
#define DES_REVISION_SCHEME_S 30
#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software
// compatible module family. If
// there is no level of software
// compatibility a new Func number
// (and hence REVISION) should be
// assigned.
#define DES_REVISION_FUNC_S 16
#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP
// design owner. RTL follows a
// numbering such as X.Y.R.Z which
// are explained in this table. R
// changes ONLY when: (1) PDS
// uploads occur which may have been
// due to spec changes (2) Bug fixes
// occur (3) Resets to '0' when X or
// Y changes. Design team has an
// internal 'Z' (customer invisible)
// number which increments on every
// drop that happens due to DV and
// RTL updates. Z resets to 0 when R
// increments.
#define DES_REVISION_R_RTL_S 11
#define DES_REVISION_X_MAJOR_M \
0x00000700 // Major Revision (X) maintained by
// IP specification owner. X changes
// ONLY when: (1) There is a major
// feature addition. An example
// would be adding Master Mode to
// Utopia Level2. The Func field (or
// Class/Type in old PID format)
// will remain the same. X does NOT
// change due to: (1) Bug fixes (2)
// Change in feature parameters.
#define DES_REVISION_X_MAJOR_S 8
#define DES_REVISION_CUSTOM_M 0x000000C0
#define DES_REVISION_CUSTOM_S 6
#define DES_REVISION_Y_MINOR_M \
0x0000003F // Minor Revision (Y) maintained by
// IP specification owner. Y changes
// ONLY when: (1) Features are
// scaled (up or down). Flexibility
// exists in that this feature
// scalability may either be
// represented in the Y change or a
// specific register in the IP that
// indicates which features are
// exactly available. (2) When
// feature creeps from Is-Not list
// to Is list. But this may not be
// the case once it sees silicon; in
// which case X will change. Y does
// NOT change due to: (1) Bug fixes
// (2) Typos or clarifications (3)
// major functional/feature
// change/addition/deletion. Instead
// these changes may be reflected
// via R S X as applicable. Spec
// owner maintains a
// customer-invisible number 'S'
// which changes due to: (1)
// Typos/clarifications (2) Bug
// documentation. Note that this bug
// is not due to a spec change but
// due to implementation.
// Nevertheless the spec tracks the
// IP bugs. An RTL release (say for
// silicon PG1.1) that occurs due to
// bug fix should document the
// corresponding spec number (X.Y.S)
// in its release notes.
#define DES_REVISION_Y_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSCONFIG register.
//
//******************************************************************************
#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
0x00000080 // If set to ‘1’ the DMA context
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
0x00000040 // If set to ‘1’ the DMA output
// request is enabled. 0 Dma
// disabled 1 Dma enabled
#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
0x00000020 // If set to ‘1’ the DMA input
// request is enabled. 0 Dma
// disabled 1 Dma enabled
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_SYSSTATUS register.
//
//******************************************************************************
#define DES_SYSSTATUS_RESETDONE \
0x00000001
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQSTATUS register.
//
//******************************************************************************
#define DES_IRQSTATUS_DATA_OUT \
0x00000004 // This bit indicates data output
// interrupt is active and triggers
// the interrupt output.
#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
// interrupt is active and triggers
// the interrupt output.
#define DES_IRQSTATUS_CONTEX_IN \
0x00000001 // This bit indicates context
// interrupt is active and triggers
// the interrupt output.
//******************************************************************************
//
// The following are defines for the bit fields in the DES_O_IRQENABLE register.
//
//******************************************************************************
#define DES_IRQENABLE_M_DATA_OUT \
0x00000004 // If this bit is set to ‘1’ the
// secure data output interrupt is
// enabled.
#define DES_IRQENABLE_M_DATA_IN \
0x00000002 // If this bit is set to ‘1’ the
// secure data input interrupt is
// enabled.
#define DES_IRQENABLE_M_CONTEX_IN \
0x00000001 // If this bit is set to ‘1’ the
// secure context interrupt is
// enabled.
#endif // __HW_DES_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
#ifndef __HW_DTHE_H__
#define __HW_DTHE_H__
//*****************************************************************************
//
// The following are defines for the DTHE register offsets.
//
//*****************************************************************************
#define DTHE_O_SHA_IM 0x00000810
#define DTHE_O_SHA_RIS 0x00000814
#define DTHE_O_SHA_MIS 0x00000818
#define DTHE_O_SHA_IC 0x0000081C
#define DTHE_O_AES_IM 0x00000820
#define DTHE_O_AES_RIS 0x00000824
#define DTHE_O_AES_MIS 0x00000828
#define DTHE_O_AES_IC 0x0000082C
#define DTHE_O_DES_IM 0x00000830
#define DTHE_O_DES_RIS 0x00000834
#define DTHE_O_DES_MIS 0x00000838
#define DTHE_O_DES_IC 0x0000083C
#define DTHE_O_EIP_CGCFG 0x00000A00
#define DTHE_O_EIP_CGREQ 0x00000A04
#define DTHE_O_CRC_CTRL 0x00000C00
#define DTHE_O_CRC_SEED 0x00000C10
#define DTHE_O_CRC_DIN 0x00000C14
#define DTHE_O_CRC_RSLT_PP 0x00000C18
#define DTHE_O_RAND_KEY0 0x00000F00
#define DTHE_O_RAND_KEY1 0x00000F04
#define DTHE_O_RAND_KEY2 0x00000F08
#define DTHE_O_RAND_KEY3 0x00000F0C
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IMST register.
//
//******************************************************************************
#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is
// raised when DMA complets the
// output context movement from
// internal register
#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IRIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done
#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_IMIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done
#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_SHAMD5_ICIS register.
//
//******************************************************************************
#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done� flag
#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IMST register.
//
//******************************************************************************
#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is
// raised when DMA finishes writing
// last word of the process result
#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is
// raised when DMA complets the
// output context movement from
// internal register
#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IRIS register.
//
//******************************************************************************
#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done
#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_IMIS register.
//
//******************************************************************************
#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done
#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_AES_ICIS register.
//
//******************************************************************************
#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement
// done� flag
#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done� flag
#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IMST register.
//
//******************************************************************************
#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is
// raised when DMA finishes writing
// last word of the process result
#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is
// raised when DMA writes last word
// of input data to internal FIFO of
// the engine
#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is
// raised when DMA complets Context
// write to internal register
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IRIS register.
//
//******************************************************************************
#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done
#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_IMIS register.
//
//******************************************************************************
#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done
#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done
#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_DES_ICIS register.
//
//******************************************************************************
#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement
// done� flag
#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done�
// flag
#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done� flag
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_EIP_CGCFG register.
//
//******************************************************************************
#define DTHE_EIP_CGCFG_EIP29_CFG \
0x00000010 // Clock gating protocol setting
// for EIP29T. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP75_CFG \
0x00000008 // Clock gating protocol setting
// for EIP75T. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP16_CFG \
0x00000004 // Clock gating protocol setting
// for DES. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP36_CFG \
0x00000002 // Clock gating protocol setting
// for AES. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
#define DTHE_EIP_CGCFG_EIP57_CFG \
0x00000001 // Clock gating protocol setting
// for SHAMD5. 0 – Follow direct
// protocol 1 – Follow idle_req/ack
// protocol.
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_EIP_CGREQ register.
//
//******************************************************************************
#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5� write “1� to lower
// bits [4:0] will set the bit.
// Write “0� will be ignored When
// “0x2� write “1� to lower bit
// [4:0] will clear the bit. Write
// “0� will be ignored for other key
// value, regular read write
// operation
#define DTHE_EIP_CGREQ_Key_S 28
#define DTHE_EIP_CGREQ_EIP29_REQ \
0x00000010 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP75_REQ \
0x00000008 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP16_REQ \
0x00000004 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP36_REQ \
0x00000002 // 0 – request clock gating 1 –
// request to un-gate the clock.
#define DTHE_EIP_CGREQ_EIP57_REQ \
0x00000001 // 0 – request clock gating 1 –
// request to un-gate the clock.
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register.
//
//******************************************************************************
#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED
// register context as starting
// value 10 – all “zero� 11 – all
// “one� This is self clearing. With
// first write to data register this
// value clears to zero and remain
// zero for rest of the operation
// unless written again
#define DTHE_CRC_CTRL_INIT_S 13
#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8
// bit
#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result
// before storing to CRC_RSLT_PP0
#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result
// byte before storing to
// CRC_RSLT_PP0. applicable for all
// bytes in word
#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For
// all bytes in word
#define DTHE_CRC_CTRL_ENDIAN_M \
0x00000030 // Endian control [0] – swap byte
// in half-word [1] – swap half word
#define DTHE_CRC_CTRL_ENDIAN_S 4
#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 –
// polynomial 0x8005 0001 –
// polynomial 0x1021 0010 –
// polynomial 0x4C11DB7 0011 –
// polynomial 0x1EDC6F41 1000 – TCP
// checksum TYPE in DTHE_S_CRC_CTRL
// & DTHE_S_CRC_CTRL should be
// exclusive
#define DTHE_CRC_CTRL_TYPE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_SEED register.
//
//******************************************************************************
#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and
// checksum operation. Please see
// CTRL register for more detail.
// This resister also holds the
// latest result of CRC or checksum
// operation
#define DTHE_CRC_SEED_SEED_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the DTHE_O_CRC_DIN register.
//
//******************************************************************************
#define DTHE_CRC_DIN_DATA_IN_M \
0xFFFFFFFF // Input data for CRC or checksum
// operation
#define DTHE_CRC_DIN_DATA_IN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_CRC_RSLT_PP register.
//
//******************************************************************************
#define DTHE_CRC_RSLT_PP_RSLT_PP_M \
0xFFFFFFFF // Input data for CRC or checksum
// operation
#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY0 register.
//
//******************************************************************************
#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [31:0]
#define DTHE_RAND_KEY0_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY1 register.
//
//******************************************************************************
#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [63:32]
#define DTHE_RAND_KEY1_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY2 register.
//
//******************************************************************************
#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [95:34]
#define DTHE_RAND_KEY2_KEY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// DTHE_O_RAND_KEY3 register.
//
//******************************************************************************
#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key
// [127:96]
#define DTHE_RAND_KEY3_KEY_S 0
#endif // __HW_DTHE_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_I2C_H__
#define __HW_I2C_H__
//*****************************************************************************
//
// The following are defines for the I2C register offsets.
//
//*****************************************************************************
#define I2C_O_MSA 0x00000000
#define I2C_O_MCS 0x00000004
#define I2C_O_MDR 0x00000008
#define I2C_O_MTPR 0x0000000C
#define I2C_O_MIMR 0x00000010
#define I2C_O_MRIS 0x00000014
#define I2C_O_MMIS 0x00000018
#define I2C_O_MICR 0x0000001C
#define I2C_O_MCR 0x00000020
#define I2C_O_MCLKOCNT 0x00000024
#define I2C_O_MBMON 0x0000002C
#define I2C_O_MBLEN 0x00000030
#define I2C_O_MBCNT 0x00000034
#define I2C_O_SOAR 0x00000800
#define I2C_O_SCSR 0x00000804
#define I2C_O_SDR 0x00000808
#define I2C_O_SIMR 0x0000080C
#define I2C_O_SRIS 0x00000810
#define I2C_O_SMIS 0x00000814
#define I2C_O_SICR 0x00000818
#define I2C_O_SOAR2 0x0000081C
#define I2C_O_SACKCTL 0x00000820
#define I2C_O_FIFODATA 0x00000F00
#define I2C_O_FIFOCTL 0x00000F04
#define I2C_O_FIFOSTATUS 0x00000F08
#define I2C_O_OBSMUXSEL0 0x00000F80
#define I2C_O_OBSMUXSEL1 0x00000F84
#define I2C_O_MUXROUTE 0x00000F88
#define I2C_O_PV 0x00000FB0
#define I2C_O_PP 0x00000FC0
#define I2C_O_PC 0x00000FC4
#define I2C_O_CC 0x00000FC8
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MSA register.
//
//******************************************************************************
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
#define I2C_MSA_SA_S 1
#define I2C_MSA_RS 0x00000001 // Receive not send
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCS register.
//
//******************************************************************************
#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
#define I2C_MCS_IDLE 0x00000020 // I2C Idle
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
#define I2C_MCS_ERROR 0x00000002 // Error
#define I2C_MCS_BUSY 0x00000001 // I2C Busy
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MDR register.
//
//******************************************************************************
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred
#define I2C_MDR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MTPR register.
//
//******************************************************************************
#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period
#define I2C_MTPR_TPR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MIMR register.
//
//******************************************************************************
#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
// Mask
#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MRIS register.
//
//******************************************************************************
#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
// Status
#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
// Status
#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
// Status
#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
// Status
#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
// Status
#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
// Status
#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
// Status
#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
// Status
#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MMIS register.
//
//******************************************************************************
#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
// Mask
#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
// Status
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MICR register.
//
//******************************************************************************
#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
// Clear
#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
// Clear
#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
// Clear
#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
// Clear
#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
// Clear
#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCR register.
//
//******************************************************************************
#define I2C_MCR_MMD 0x00000040 // Multi-master Disable
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
//
//******************************************************************************
#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
#define I2C_MCLKOCNT_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBMON register.
//
//******************************************************************************
#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBLEN register.
//
//******************************************************************************
#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
#define I2C_MBLEN_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MBCNT register.
//
//******************************************************************************
#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
#define I2C_MBCNT_CNTL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR register.
//
//******************************************************************************
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
#define I2C_SOAR_OAR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SCSR register.
//
//******************************************************************************
#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
#define I2C_SCSR_FBR 0x00000004 // First Byte Received
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
#define I2C_SCSR_DA 0x00000001 // Device Active
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SDR register.
//
//******************************************************************************
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
#define I2C_SDR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SIMR register.
//
//******************************************************************************
#define I2C_SIMR_IM 0x00000100 // Interrupt Mask
#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SRIS register.
//
//******************************************************************************
#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status
#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
// Interrupt Status
#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
// Interrupt Status
#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
// Status
#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
// Status
#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
// Status
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
// Status
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SMIS register.
//
//******************************************************************************
#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
// Mask
#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
// Mask
#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
// Status
#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
// Status
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
// Status
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
// Status
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SICR register.
//
//******************************************************************************
#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
// Mask
#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SOAR2 register.
//
//******************************************************************************
#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
#define I2C_SOAR2_OAR2_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_SACKCTL register.
//
//******************************************************************************
#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFODATA register.
//
//******************************************************************************
#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte
#define I2C_FIFODATA_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
//
//******************************************************************************
#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
#define I2C_FIFOCTL_RXTRIG_S 16
#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
#define I2C_FIFOCTL_TXTRIG_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register.
//
//******************************************************************************
#define I2C_FIFOSTATUS_RXABVTRIG \
0x00040000 // RX FIFO Above Trigger Level
#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
#define I2C_FIFOSTATUS_TXBLWTRIG \
0x00000004 // TX FIFO Below Trigger Level
#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register.
//
//******************************************************************************
#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3
#define I2C_OBSMUXSEL0_LN3_S 24
#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2
#define I2C_OBSMUXSEL0_LN2_S 16
#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1
#define I2C_OBSMUXSEL0_LN1_S 8
#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0
#define I2C_OBSMUXSEL0_LN0_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register.
//
//******************************************************************************
#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7
#define I2C_OBSMUXSEL1_LN7_S 24
#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6
#define I2C_OBSMUXSEL1_LN6_S 16
#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5
#define I2C_OBSMUXSEL1_LN5_S 8
#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4
#define I2C_OBSMUXSEL1_LN4_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_MUXROUTE register.
//
//******************************************************************************
#define I2C_MUXROUTE_LN7ROUTE_M \
0x70000000 // Lane 7 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN7ROUTE_S 28
#define I2C_MUXROUTE_LN6ROUTE_M \
0x07000000 // Lane 6 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN6ROUTE_S 24
#define I2C_MUXROUTE_LN5ROUTE_M \
0x00700000 // Lane 5 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN5ROUTE_S 20
#define I2C_MUXROUTE_LN4ROUTE_M \
0x00070000 // Lane 4 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN4ROUTE_S 16
#define I2C_MUXROUTE_LN3ROUTE_M \
0x00007000 // Lane 3 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN3ROUTE_S 12
#define I2C_MUXROUTE_LN2ROUTE_M \
0x00000700 // Lane 2 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN2ROUTE_S 8
#define I2C_MUXROUTE_LN1ROUTE_M \
0x00000070 // Lane 1 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN1ROUTE_S 4
#define I2C_MUXROUTE_LN0ROUTE_M \
0x00000007 // Lane 0 output is routed to the
// lane pointed to by the offset in
// this bit field
#define I2C_MUXROUTE_LN0ROUTE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PV register.
//
//******************************************************************************
#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision
#define I2C_PV_MAJOR_S 8
#define I2C_PV_MINOR_M 0x000000FF // Minor Revision
#define I2C_PV_MINOR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PP register.
//
//******************************************************************************
#define I2C_PP_HS 0x00000001 // High-Speed Capable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_PC register.
//
//******************************************************************************
#define I2C_PC_HS 0x00000001 // High-Speed Capable
//******************************************************************************
//
// The following are defines for the bit fields in the I2C_O_CC register.
//
//******************************************************************************
#endif // __HW_I2C_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_STACK_DIE_CTRL_H__
#define __HW_STACK_DIE_CTRL_H__
//*****************************************************************************
//
// The following are defines for the STACK_DIE_CTRL register offsets.
//
//*****************************************************************************
#define STACK_DIE_CTRL_O_STK_UP_RESET \
0x00000000 // Can be written only by Base
// Processor. Writing to this
// register will reset the stack
// processor reset will be
// de-asserted upon clearing this
// register.
#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \
0x00000004 // This register defines who among
// base processor and stack
// processor have highest priority
// for Sram Access. Can be written
// only by Base Processor.
#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \
0x00000008 // In Spinlock mode this Register
// defines who among base processor
// and stack processor have access
// to Sram Bank2 right now. In
// Handshake mode this Register
// defines who among base processor
// and stack processor have access
// to Sram Bank2 and Bank3 right
// now. Its Clear only register and
// is set by hardware. Lower bit can
// be cleared only by Base Processor
// and Upper bit Cleared only by the
// Stack processor.
#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \
0x0000000C // In Spinlock mode whenever Base
// processor wants the access to
// Sram Bank2 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by Stack
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \
0x00000010 // In Spinlock mode Whenever Stack
// processor wants the access to
// Sram Bank2 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by the Base
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \
0x00000014 // Register defines who among base
// processor and stack processor
// have access to Sram Bank3 right
// now. Its Clear only register and
// is set by hardware. Lower bit can
// be cleared only by Base Processor
// and Upper bit Cleared only by the
// Stack processor.
#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \
0x00000018 // In Spinlock mode whenever Base
// processor wants the access to
// Sram Bank3 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by Stack
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \
0x0000001C // In Spinlock mode Whenever Stack
// processor wants the access to
// Sram Bank3 it should request for
// it by writing into this register.
// It'll get interrupt whenever it
// is granted. In Handshake mode
// this bit will be set by the Base
// processor. Its a set only bit and
// is cleared by HW when the request
// is granted.
#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \
0x00000020 // Read State Machine timing
// configuration register. Generally
// Bit 4 and 3 will be identical.
// For stacked die always 43 are 0
// and 6:5 == 1 for 120Mhz.
#define STACK_DIE_CTRL_O_RDSM_CFG_EE \
0x00000024 // Read State Machine timing
// configuration register. Generally
// Bit 4 and 3 will be identical.
// For stacked die always 43 are 0
// and 6:5 == 1 for 120Mhz.
#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \
0x00000028 // Reading this register Base
// procesor will able to know the
// reason for the interrupt. This is
// clear only register - set by HW
// upon an interrupt to Base
// processor and can be cleared only
// by BASE processor.
#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \
0x0000002C // Reading this register Stack
// procesor will able to know the
// reason for the interrupt. This is
// clear only register - set by HW
// upon an interrupt to Stack
// processor and can be cleared only
// by Stack processor.
#define STACK_DIE_CTRL_O_STK_CLK_EN \
0x00000030 // Can be written only by base
// processor. Controls the enable
// pin of the cgcs for the clocks
// going to CM3 dft ctrl block and
// Sram.
#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \
0x00000034 // Can be written only by the base
// processor. Decides the ram
// sharing mode :: handshake or
// Spinlock mode.
#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \
0x00000038 // Stores the last bus fault
// address.
#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \
0x0000003C // write only registers on read
// returns 0.W Write 1 to clear the
// bust fault to store the new bus
// fault address
#define STACK_DIE_CTRL_O_RESET_CAUSE \
0x00000040 // Reset cause value captured from
// the ICR_CLKRST block.
#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \
0x00000044 // Watchdog timer event value
// captured from the ICR_CLKRST
// block
#define STACK_DIE_CTRL_O_DMA_REQ \
0x00000048 // To send Dma Request to bottom
// die.
#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \
0x0000004C // Address offset within SRAM to
// which CM3 should jump after
// reset.
#define STACK_DIE_CTRL_O_SW_REG1 \
0x00000050 // These are sw registers for
// topdie processor and bottom die
// processor to communicate. Both
// can set and read these registers.
// In case of write clash bottom
// die's processor wins and top die
// processor access is ignored.
#define STACK_DIE_CTRL_O_SW_REG2 \
0x00000054 // These are sw registers for
// topdie processor and bottom die
// processor to communicate. Both
// can set and read these registers.
// In case of write clash bottom
// die's processor wins and top die
// processor access is ignored.
#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \
0x00000058 // By posting the request Flash can
// be put into low-power mode
// (Sleep) without powering down the
// Flash. Earlier (in Garnet) this
// was fully h/w controlled and the
// control for this was coming from
// SysCtl while entering into Cortex
// Deep-sleep mode. But for our
// device the D2D i/f doesnt support
// this. The Firmware has to program
// the register in the top-die for
// entering into this mode and wait
// for an interrupt.
#define STACK_DIE_CTRL_O_MISC_CTL \
0x0000005C // Miscellanious control register.
#define STACK_DIE_CTRL_O_SW_DFT_CTL \
0x000000FC // DFT control and status bits
#define STACK_DIE_CTRL_O_PADN_CTL_0 \
0x00000100 // Mainly for For controlling the
// pads OEN pins. There are total 60
// pads and hence 60 control registe
// i.e n value varies from 0 to 59.
// Here is the mapping for the
// pad_ctl register number and the
// functionality : 0 D2DPAD_DMAREQ1
// 1 D2DPAD_DMAREQ0 2
// D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4
// D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6
// D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8
// D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS
// 10 D2DPAD_JTAG_TDI 11-27
// D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE
// -1:0] 28-56 D2DPAD_TOSTACK
// [D2D_TOSTACK_SIZE -1:0] 57-59
// D2DPAD_SPARE [D2D_SPARE_PAD_SIZE
// -1:0] 0:00
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_RESET register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \
0x00000001 // 1 :Assert Reset 0 : Deassert the
// Reset
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \
0x00000003 // 00 : Equal Priority 01 : Stack
// Processor have priority 10 : Base
// Processor have priority 11 :
// Unused
#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \
0x00000002 // Stack Processor should clear it
// when it is done with the sram
// bank usage. Set by HW It is set
// when Stack Processor is granted
// the access to this bank
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \
0x00000001 // Base Processor should clear it
// when it is done wth the sram
// usage. Set by HW It is set when
// Base Processor is granted the
// access to this bank
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \
0x00000001 // Base Processor will set when
// Sram access is needed in Spin
// Lock mode. In Handshake mode
// Stack Processor will set to
// inform Base Processor that it is
// done with the processing of data
// in SRAM and is now ready to use
// by the base processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \
0x00000001 // Stack Processor will set when
// Sram access is needed in Spin
// Lock mode. In Handshake mode Base
// Processor will set to inform
// Stack Processor to start
// processing the data in the Ram.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \
0x00000002 // Stack Processor should clear it
// when it is done with the sram
// bank usage. Set by HW It is set
// when Stack Processor is granted
// the access to this bank.
#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \
0x00000001 // Base Processor should clear it
// when it is done wth the sram
// usage. Set by HW it is set when
// Base Processor is granted the
// access to this bank.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \
0x00000001 // Base Processor will set when
// Sram access is needed in Spin
// Lock mode. Not used in handshake
// mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \
0x00000001 // Stack Processor will set when
// Sram access is needed in Spin
// Lock mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RDSM_CFG_CPU register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \
0x000000C0 // Bank Clock Hi Time 00 : HCLK
// pulse 01 : 1 cycle of HCLK 10 :
// 1.5 cycles of HCLK 11 : 2 cycles
// of HCLK
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \
0x00000020 // FLCLK 0 : indicates flash clock
// rise aligns on HCLK rise 1 :
// indicates flash clock rise aligns
// on HCLK fall
#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \
0x00000010 // 0 : Always register flash rdata
// before sending to CPU 1 : Drive
// Flash rdata directly out on MISS
// (Both ICODE / DCODE)
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \
0x0000000F // Number of wait states inserted
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RDSM_CFG_EE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \
0x000000C0 // Bank Clock Hi Time 00 : HCLK
// pulse 01 : 1 cycle of HCLK 10 :
// 1.5 cycles of HCLK 11 : 2 cycles
// of HCLK
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \
0x00000020 // FLCLK 0 : indicates flash clock
// rise aligns on HCLK rise 1 :
// indicates flash clock rise aligns
// on HCLK fall
#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \
0x00000010 // 0 : Always register flash rdata
// before sending to CPU 1 : Drive
// Flash rdata directly out on MISS
// (Both ICODE / DCODE)
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \
0x0000000F // Number of wait states inserted
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \
0x00000010 // Set when Relinquish Interrupt
// sent to Base processor for Bank3.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \
0x00000008 // Set when Relinquish Interrupt
// sent to Base processor for Bank2.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \
0x00000004 // Set when Bank3 is granted to
// Base processor.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \
0x00000002 // Set when Bank2 is granted to
// BAse processor.
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \
0x00000001 // Set when there Base processor do
// an Invalid access to Sram. Ex :
// Accessing the bank which is not
// granted for BAse processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \
0x00000008 // Set when Relinquish Interrupt
// sent to Stack processor for
// Bank3.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \
0x00000004 // Set when Relinquish Interrupt
// sent to Stack processor for
// Bank2.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \
0x00000002 // Set when Bank3 is granted to
// Stack processor.
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \
0x00000001 // Set when Bank2 is granted to
// Stack processor.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_STK_CLK_EN register.
//
//******************************************************************************
#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \
0x00000004 // Enable the clock going to sram.
#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \
0x00000002 // Enable the clock going to dft
// control block
#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \
0x00000001 // Enable the clock going to Cm3
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \
0x00000001 // 0 : Handshake Mode 1 : Spinlock
// mode.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \
0xFFFFFFFF // Fault Address
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_BUS_FAULT_CLR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \
0x00000001 // When set it'll clear the bust
// fault address register to store
// the new bus fault address
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_RESET_CAUSE register.
//
//******************************************************************************
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register.
//
//******************************************************************************
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_DMA_REQ register.
//
//******************************************************************************
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \
0x00000002 // Generate DMAREQ1 on setting this
// bit.
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \
0x00000001 // Generate DMAREQ0 on setting this
// bit.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_REG1 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_REG2 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \
0xFFFFFFFF
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \
0x00000002 // captures the status of of
// fmc_lpm_ack
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \
0x00000001 // When set assert
// iflpe2fmc_lpm_req to FMC.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_MISC_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \
0x00000080 // 1 : will reset the async wdog
// timer runing on piosc clock
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \
0x00000020 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \
0x00000010 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \
0x00000008 // Setting this Will send to
// interttupt to CM3
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \
0x00000004 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 3 goes to Bank3 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank2
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \
0x00000002 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 2 goes to Bank2 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank2
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \
0x00000001 // While testing Flash Setting this
// bit will Control the
// CE/STR/AIN/CLKIN going to flash
// banks 12 and 3. 0 : Control
// signals coming from FMC for Bank
// 1 goes to Bank1 1 : Control
// signals coming from FMC for Bank
// 0 goes to Bank1
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_SW_DFT_CTL register.
//
//******************************************************************************
#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \
0x20000000 // when set to '1' all flash
// control signals switch over to
// CM3 control when '0' it is under
// the D2D interface control
#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \
0x10000000 // 1 indicates in SWIF mode the
// control signals to flash are from
// FMC CPU read controls the clock
// and address. that is one can give
// address via FMC and read through
// IDMEM.
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \
0x00800000 // 'CPU Done' bit for PBIST. Write
// '1' to indicate test done.
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \
0x00400000 // 'CPU Fail' bit for PBIST. Write
// '1' to indicate test failed.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \
0x00001000 // when set to '1' flash bank 4
// (EEPROM) is owned by the CM3for
// reads over DCODE bus. When '0'
// access control given to D2D
// interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \
0x00000800 // when set to '1' flash bank 3 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \
0x00000400 // when set to '1' flash bank 2 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \
0x00000200 // when set to '1' flash bank 1 is
// owned by the CM3for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \
0x00000100 // when set to '1' flash bank 0 is
// owned by the CM3 for reads over
// DCODE bus. When '0' access
// control given to D2D interface.
//******************************************************************************
//
// The following are defines for the bit fields in the
// STACK_DIE_CTRL_O_PADN_CTL_0 register.
//
//******************************************************************************
#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \
0x00000008 // This bit is valid for only the
// spare pads ie for n=57 to 59.
// value to drive at the output of
// the pad
#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \
0x00000004 // This bit is valid for only the
// spare pads ie for n=57 to 59.
// captures the 'Y' pin of the pad
// which is the data being driven
// into the die
#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \
0x00000002 // OEN2X control when '1' enables
// the output with 1x. Total drive
// strength is decided bu oen1x
// setting + oen2x setting.
#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \
0x00000001 // OEN1X control when '1' enables
// the output with 1x . Total drive
// strength is decided bu oen1x
// setting + oen2x setting.
#endif // __HW_STACK_DIE_CTRL_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_timer.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
//*****************************************************************************
//
// hw_timer.h - Defines and macros used when accessing the timer.
//
//*****************************************************************************
//##### INTERNAL BEGIN #####
//
// This is an auto-generated file. Do not edit by hand.
// Created by version 6779 of DriverLib.
//
//##### INTERNAL END #####
#ifndef __HW_TIMER_H__
#define __HW_TIMER_H__
//*****************************************************************************
//
// The following are defines for the Timer register offsets.
//
//*****************************************************************************
#define TIMER_O_CFG 0x00000000 // GPTM Configuration
#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
#define TIMER_O_CTL 0x0000000C // GPTM Control
//##### GARNET BEGIN #####
#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
//##### GARNET END #####
#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
#define TIMER_O_TAR 0x00000048 // GPTM Timer A
#define TIMER_O_TBR 0x0000004C // GPTM Timer B
#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CFG register.
//
//*****************************************************************************
#define TIMER_CFG_M 0x00000007 // GPTM Configuration
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC)
// counter configuration
#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The
// function is controlled by bits
// 1:0 of GPTMTAMR and GPTMTBMR
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
// Operation
#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
// Update
#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
// Enable
#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
//##### GARNET END #####
#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
// Enable
#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
// Select
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
// Operation
#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
// Update
#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
// Enable
#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
//##### GARNET END #####
#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
// Enable
#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
// Select
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_CTL register.
//
//*****************************************************************************
#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
// Enable
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
// Enable
#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
//##### GARNET BEGIN #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_SYNC register.
//
//*****************************************************************************
#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11
#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of
// GPTM11 is triggered
#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of
// GPTM11 is triggered
#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A
// and Timer B of GPTM11 is
// triggered
#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10
#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of
// GPTM10 is triggered
#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of
// GPTM10 is triggered
#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A
// and Timer B of GPTM10 is
// triggered
#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9
#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of
// GPTM9 is triggered
#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of
// GPTM9 is triggered
#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A
// and Timer B of GPTM9 is
// triggered
#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8
#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of
// GPTM8 is triggered
#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of
// GPTM8 is triggered
#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A
// and Timer B of GPTM8 is
// triggered
#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7
#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of
// GPTM7 is triggered
#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of
// GPTM7 is triggered
#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A
// and Timer B of GPTM7 is
// triggered
#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6
#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of
// GPTM6 is triggered
#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of
// GPTM6 is triggered
#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A
// and Timer B of GPTM6 is
// triggered
#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5
#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of
// GPTM5 is triggered
#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of
// GPTM5 is triggered
#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A
// and Timer B of GPTM5 is
// triggered
#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4
#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of
// GPTM4 is triggered
#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of
// GPTM4 is triggered
#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A
// and Timer B of GPTM4 is
// triggered
#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3
#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of
// GPTM3 is triggered
#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of
// GPTM3 is triggered
#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A
// and Timer B of GPTM3 is
// triggered
#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2
#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of
// GPTM2 is triggered
#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of
// GPTM2 is triggered
#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A
// and Timer B of GPTM2 is
// triggered
#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1
#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of
// GPTM1 is triggered
#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of
// GPTM1 is triggered
#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A
// and Timer B of GPTM1 is
// triggered
#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0
#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of
// GPTM0 is triggered
#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of
// GPTM0 is triggered
#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A
// and Timer B of GPTM0 is
// triggered
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_IMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Mask
//##### GARNET END #####
#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match
// Interrupt Mask
#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt
// Mask
#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt
// Mask
#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
// Mask
#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match
// Interrupt Mask
#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt
// Mask
#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt
// Mask
#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
// Mask
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RIS register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Raw Interrupt Status
//##### GARNET END #####
#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw
// Interrupt
#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw
// Interrupt
#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw
// Interrupt
#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
// Interrupt
#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw
// Interrupt
#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw
// Interrupt
#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw
// Interrupt
#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_MIS register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update
// Error Masked Interrupt Status
//##### GARNET END #####
#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked
// Interrupt
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked
// Interrupt
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked
// Interrupt
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
// Interrupt
#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked
// Interrupt
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked
// Interrupt
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked
// Interrupt
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_ICR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update
// Error Interrupt Clear
//##### GARNET END #####
#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match
// Interrupt Clear
#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt
// Clear
#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt
// Clear
#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
// Clear
#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match
// Interrupt Clear
#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt
// Clear
#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt
// Clear
#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
// Interrupt
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAILR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
// Register
//##### GARNET END #####
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load
// Register High
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load
// Register Low
#define TIMER_TAILR_TAILRH_S 16
#define TIMER_TAILR_TAILRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAILR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBILR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
// Register
//##### GARNET END #####
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load
// Register
#define TIMER_TBILR_TBILRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBILR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAMATCHR
// register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
//##### GARNET END #####
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low
#define TIMER_TAMATCHR_TAMRH_S 16
#define TIMER_TAMATCHR_TAMRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAMATCHR_TAMR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBMATCHR
// register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
//##### GARNET END #####
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low
//##### GARNET BEGIN #####
#define TIMER_TBMATCHR_TBMR_S 0
//##### GARNET END #####
#define TIMER_TBMATCHR_TBMRL_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
//##### GARNET END #####
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
//##### GARNET BEGIN #####
#define TIMER_TAPR_TAPSRH_S 8
//##### GARNET END #####
#define TIMER_TAPR_TAPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
//##### GARNET END #####
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
//##### GARNET BEGIN #####
#define TIMER_TBPR_TBPSRH_S 8
//##### GARNET END #####
#define TIMER_TBPR_TBPSR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
// Byte
//##### GARNET END #####
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
//##### GARNET BEGIN #####
#define TIMER_TAPMR_TAPSMRH_S 8
//##### GARNET END #####
#define TIMER_TAPMR_TAPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPMR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
// Byte
//##### GARNET END #####
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
//##### GARNET BEGIN #####
#define TIMER_TBPMR_TBPSMRH_S 8
//##### GARNET END #####
#define TIMER_TBPMR_TBPSMR_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
//##### GARNET END #####
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAR_TARH_S 16
#define TIMER_TAR_TARL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBR register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
//##### GARNET END #####
#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B
#define TIMER_TBR_TBRL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBR_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAV register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
//##### GARNET END #####
#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High
#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low
#define TIMER_TAV_TAVH_S 16
#define TIMER_TAV_TAVL_S 0
//##### GARNET BEGIN #####
#define TIMER_TAV_S 0
//##### GARNET END #####
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBV register.
//
//*****************************************************************************
//##### GARNET BEGIN #####
#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
//##### GARNET END #####
#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register
#define TIMER_TBV_TBVL_S 0
//##### GARNET BEGIN #####
#define TIMER_TBV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_RTCPD register.
//
//*****************************************************************************
#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
#define TIMER_RTCPD_RTCPD_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPS register.
//
//*****************************************************************************
#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
#define TIMER_TAPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPS register.
//
//*****************************************************************************
#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TBPS_PSS_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TAPV register.
//
//*****************************************************************************
#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
#define TIMER_TAPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_TBPV register.
//
//*****************************************************************************
#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
#define TIMER_TBPV_PSV_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the TIMER_O_PP register.
//
//*****************************************************************************
#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
#define TIMER_PP_SIZE_M 0x0000000F // Count Size
#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are
// 16 bits each with an 8-bit
// prescale counter
#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are
// 32 bits each with an 16-bit
// prescale counter
//##### GARNET END #####
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CFG
// register.
//
//*****************************************************************************
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_CTL
// register.
//
//*****************************************************************************
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_RIS
// register.
//
//*****************************************************************************
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAILR
// register.
//
//*****************************************************************************
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBILR
// register.
//
//*****************************************************************************
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TAMATCHR register.
//
//*****************************************************************************
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the
// TIMER_O_TBMATCHR register.
//
//*****************************************************************************
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TAR
// register.
//
//*****************************************************************************
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_O_TBR
// register.
//
//*****************************************************************************
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the timer
// registers.
//
//*****************************************************************************
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV
#define TIMER_RV_CFG 0x00000000 // Configuration register RV
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV
#define TIMER_RV_CTL 0x00000000 // Control register RV
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnMR
// register.
//
//*****************************************************************************
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPR
// register.
//
//*****************************************************************************
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the TIMER_TnPMR
// register.
//
//*****************************************************************************
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value
#endif
#endif // __HW_TIMER_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_types.h Normal file → Executable file
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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_uart.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_UART_H__
#define __HW_UART_H__
//*****************************************************************************
//
// The following are defines for the UART register offsets.
//
//*****************************************************************************
#define UART_O_DR 0x00000000
#define UART_O_RSR 0x00000004
#define UART_O_ECR 0x00000004
#define UART_O_FR 0x00000018
#define UART_O_ILPR 0x00000020
#define UART_O_IBRD 0x00000024
#define UART_O_FBRD 0x00000028
#define UART_O_LCRH 0x0000002C
#define UART_O_CTL 0x00000030
#define UART_O_IFLS 0x00000034
#define UART_O_IM 0x00000038
#define UART_O_RIS 0x0000003C
#define UART_O_MIS 0x00000040
#define UART_O_ICR 0x00000044
#define UART_O_DMACTL 0x00000048
#define UART_O_LCTL 0x00000090
#define UART_O_LSS 0x00000094
#define UART_O_LTIM 0x00000098
#define UART_O_9BITADDR 0x000000A4
#define UART_O_9BITAMASK 0x000000A8
#define UART_O_PP 0x00000FC0
#define UART_O_CC 0x00000FC8
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_DR register.
//
//******************************************************************************
#define UART_DR_OE 0x00000800 // UART Overrun Error
#define UART_DR_BE 0x00000400 // UART Break Error
#define UART_DR_PE 0x00000200 // UART Parity Error
#define UART_DR_FE 0x00000100 // UART Framing Error
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
#define UART_DR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_RSR register.
//
//******************************************************************************
#define UART_RSR_OE 0x00000008 // UART Overrun Error
#define UART_RSR_BE 0x00000004 // UART Break Error
#define UART_RSR_PE 0x00000002 // UART Parity Error
#define UART_RSR_FE 0x00000001 // UART Framing Error
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ECR register.
//
//******************************************************************************
#define UART_ECR_DATA_M 0x000000FF // Error Clear
#define UART_ECR_DATA_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_FR register.
//
//******************************************************************************
#define UART_FR_RI 0x00000100 // Ring Indicator
#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
#define UART_FR_BUSY 0x00000008 // UART Busy
#define UART_FR_DCD 0x00000004 // Data Carrier Detect
#define UART_FR_DSR 0x00000002 // Data Set Ready
#define UART_FR_CTS 0x00000001 // Clear To Send
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ILPR register.
//
//******************************************************************************
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
#define UART_ILPR_ILPDVSR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IBRD register.
//
//******************************************************************************
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
#define UART_IBRD_DIVINT_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_FBRD register.
//
//******************************************************************************
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
#define UART_FBRD_DIVFRAC_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCRH register.
//
//******************************************************************************
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 :
// UART_LCRH_WLEN_5 : 5 bits
// (default) 0x00000020 :
// UART_LCRH_WLEN_6 : 6 bits
// 0x00000040 : UART_LCRH_WLEN_7 : 7
// bits 0x00000060 :
// UART_LCRH_WLEN_8 : 8 bits
#define UART_LCRH_WLEN_S 5
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
#define UART_LCRH_BRK 0x00000001 // UART Send Break
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_CTL register.
//
//******************************************************************************
#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
#define UART_CTL_RI 0x00002000 // Ring Indicator
#define UART_CTL_DCD 0x00001000 // Data Carrier Detect
#define UART_CTL_RTS 0x00000800 // Request to Send
#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
#define UART_CTL_RXE 0x00000200 // UART Receive Enable
#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
#define UART_CTL_LIN 0x00000040 // LIN Mode Enable
#define UART_CTL_HSE 0x00000020 // High-Speed Enable
#define UART_CTL_EOT 0x00000010 // End of Transmission
#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
#define UART_CTL_UARTEN 0x00000001 // UART Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IFLS register.
//
//******************************************************************************
#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
// Level Select
#define UART_IFLS_RX_S 3
#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
// Level Select
#define UART_IFLS_TX_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_IM register.
//
//******************************************************************************
#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask
#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask
#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt
// Mask
#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
// Mask
#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
// Mask
#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
// Mask
#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
// Mask
#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
// Interrupt Mask
#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Mask
#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
// Interrupt Mask
#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
// Interrupt Mask
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_RIS register.
//
//******************************************************************************
#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
// Status
#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt
// Status
#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt
// Status
#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw
// Interrupt Status
#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
// Interrupt Status
#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
// Status
#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
// Status
#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
// Status
#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
// Status
#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
// Interrupt Status
#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
// Status
#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
// Status
#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
// Interrupt Status
#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
// Raw Interrupt Status
#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
// Interrupt Status
#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
// Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_MIS register.
//
//******************************************************************************
#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
// Status
#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
// Status
#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt
// Status
#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt
// Status
#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked
// Interrupt Status
#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
// Status
#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
// Interrupt Status
#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
// Interrupt Status
#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
// Interrupt Status
#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
// Interrupt Status
#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
// Interrupt Status
#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
// Interrupt Status
#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
// Status
#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
// Status
#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
// Interrupt Status
#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
// Masked Interrupt Status
#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
// Interrupt Status
#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
// Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_ICR register.
//
//******************************************************************************
#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear
#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear
#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt
// Clear
#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
// Clear
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
// Interrupt Clear
#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
// Interrupt Clear
#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
// Interrupt Clear
#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
// Interrupt Clear
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_DMACTL register.
//
//******************************************************************************
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LCTL register.
//
//******************************************************************************
#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 :
// UART_LCTL_BLEN_13T : Sync break
// length is 13T bits (default)
// 0x00000010 : UART_LCTL_BLEN_14T :
// Sync break length is 14T bits
// 0x00000020 : UART_LCTL_BLEN_15T :
// Sync break length is 15T bits
// 0x00000030 : UART_LCTL_BLEN_16T :
// Sync break length is 16T bits
#define UART_LCTL_BLEN_S 4
#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LSS register.
//
//******************************************************************************
#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot
#define UART_LSS_TSS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_LTIM register.
//
//******************************************************************************
#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value
#define UART_LTIM_TIMER_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UART_O_9BITADDR register.
//
//******************************************************************************
#define UART_9BITADDR_9BITEN \
0x00008000 // Enable 9-Bit Mode
#define UART_9BITADDR_ADDR_M \
0x000000FF // Self Address for 9-Bit Mode
#define UART_9BITADDR_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UART_O_9BITAMASK register.
//
//******************************************************************************
#define UART_9BITAMASK_RANGE_M \
0x0000FF00 // Self Address Range for 9-Bit
// Mode
#define UART_9BITAMASK_RANGE_S 8
#define UART_9BITAMASK_MASK_M \
0x000000FF // Self Address Mask for 9-Bit Mode
#define UART_9BITAMASK_MASK_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_PP register.
//
//******************************************************************************
#define UART_PP_MSE 0x00000008 // Modem Support Extended
#define UART_PP_MS 0x00000004 // Modem Support
#define UART_PP_NB 0x00000002 // 9-Bit Support
#define UART_PP_SC 0x00000001 // Smart Card Support
//******************************************************************************
//
// The following are defines for the bit fields in the UART_O_CC register.
//
//******************************************************************************
#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
// 0x00000005 : UART_CC_CS_PIOSC :
// PIOSC 0x00000000 :
// UART_CC_CS_SYSCLK : The system
// clock (default)
#define UART_CC_CS_S 0
#endif // __HW_UART_H__

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ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_udma.h Executable file
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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_UDMA_H__
#define __HW_UDMA_H__
//*****************************************************************************
//
// The following are defines for the UDMA register offsets.
//
//*****************************************************************************
#define UDMA_O_STAT 0x00000000
#define UDMA_O_CFG 0x00000004
#define UDMA_O_CTLBASE 0x00000008
#define UDMA_O_ALTBASE 0x0000000C
#define UDMA_O_WAITSTAT 0x00000010
#define UDMA_O_SWREQ 0x00000014
#define UDMA_O_USEBURSTSET 0x00000018
#define UDMA_O_USEBURSTCLR 0x0000001C
#define UDMA_O_REQMASKSET 0x00000020
#define UDMA_O_REQMASKCLR 0x00000024
#define UDMA_O_ENASET 0x00000028
#define UDMA_O_ENACLR 0x0000002C
#define UDMA_O_ALTSET 0x00000030
#define UDMA_O_ALTCLR 0x00000034
#define UDMA_O_PRIOSET 0x00000038
#define UDMA_O_PRIOCLR 0x0000003C
#define UDMA_O_ERRCLR 0x0000004C
#define UDMA_O_CHASGN 0x00000500
#define UDMA_O_CHIS 0x00000504
#define UDMA_O_CHMAP0 0x00000510
#define UDMA_O_CHMAP1 0x00000514
#define UDMA_O_CHMAP2 0x00000518
#define UDMA_O_CHMAP3 0x0000051C
#define UDMA_O_PV 0x00000FB0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_STAT register.
//
//******************************************************************************
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
#define UDMA_STAT_DMACHANS_S 16
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
// 0x00000090 : UDMA_STAT_STATE_DONE
// : Done 0x00000000 :
// UDMA_STAT_STATE_IDLE : Idle
// 0x00000010 :
// UDMA_STAT_STATE_RD_CTRL : Reading
// channel controller data
// 0x00000030 :
// UDMA_STAT_STATE_RD_DSTENDP :
// Reading destination end pointer
// 0x00000040 :
// UDMA_STAT_STATE_RD_SRCDAT :
// Reading source data 0x00000020 :
// UDMA_STAT_STATE_RD_SRCENDP :
// Reading source end pointer
// 0x00000080 :
// UDMA_STAT_STATE_STALL : Stalled
// 0x000000A0 :
// UDMA_STAT_STATE_UNDEF : Undefined
// 0x00000060 : UDMA_STAT_STATE_WAIT
// : Waiting for uDMA request to
// clear 0x00000070 :
// UDMA_STAT_STATE_WR_CTRL : Writing
// channel controller data
// 0x00000050 :
// UDMA_STAT_STATE_WR_DSTDAT :
// Writing destination data
#define UDMA_STAT_STATE_S 4
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CFG register.
//
//******************************************************************************
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CTLBASE register.
//
//******************************************************************************
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
#define UDMA_CTLBASE_ADDR_S 10
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTBASE register.
//
//******************************************************************************
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
// Pointer
#define UDMA_ALTBASE_ADDR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_WAITSTAT register.
//
//******************************************************************************
#define UDMA_WAITSTAT_WAITREQ_M \
0xFFFFFFFF // Channel [n] Wait Status
#define UDMA_WAITSTAT_WAITREQ_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_SWREQ register.
//
//******************************************************************************
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
#define UDMA_SWREQ_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_O_USEBURSTSET register.
//
//******************************************************************************
#define UDMA_USEBURSTSET_SET_M \
0xFFFFFFFF // Channel [n] Useburst Set
#define UDMA_USEBURSTSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the
// UDMA_O_USEBURSTCLR register.
//
//******************************************************************************
#define UDMA_USEBURSTCLR_CLR_M \
0xFFFFFFFF // Channel [n] Useburst Clear
#define UDMA_USEBURSTCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_REQMASKSET register.
//
//******************************************************************************
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
#define UDMA_REQMASKSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register.
//
//******************************************************************************
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
#define UDMA_REQMASKCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ENASET register.
//
//******************************************************************************
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set
#define UDMA_ENASET_CHENSET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ENACLR register.
//
//******************************************************************************
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
#define UDMA_ENACLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTSET register.
//
//******************************************************************************
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
#define UDMA_ALTSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ALTCLR register.
//
//******************************************************************************
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
#define UDMA_ALTCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PRIOSET register.
//
//******************************************************************************
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
#define UDMA_PRIOSET_SET_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PRIOCLR register.
//
//******************************************************************************
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
#define UDMA_PRIOCLR_CLR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_ERRCLR register.
//
//******************************************************************************
#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHASGN register.
//
//******************************************************************************
#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
#define UDMA_CHASGN_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHIS register.
//
//******************************************************************************
#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
#define UDMA_CHIS_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP0 register.
//
//******************************************************************************
#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
#define UDMA_CHMAP0_CH7SEL_S 28
#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
#define UDMA_CHMAP0_CH6SEL_S 24
#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
#define UDMA_CHMAP0_CH5SEL_S 20
#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
#define UDMA_CHMAP0_CH4SEL_S 16
#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
#define UDMA_CHMAP0_CH3SEL_S 12
#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
#define UDMA_CHMAP0_CH2SEL_S 8
#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
#define UDMA_CHMAP0_CH1SEL_S 4
#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
#define UDMA_CHMAP0_CH0SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP1 register.
//
//******************************************************************************
#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
#define UDMA_CHMAP1_CH15SEL_S 28
#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
#define UDMA_CHMAP1_CH14SEL_S 24
#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
#define UDMA_CHMAP1_CH13SEL_S 20
#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
#define UDMA_CHMAP1_CH12SEL_S 16
#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
#define UDMA_CHMAP1_CH11SEL_S 12
#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
#define UDMA_CHMAP1_CH10SEL_S 8
#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
#define UDMA_CHMAP1_CH9SEL_S 4
#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
#define UDMA_CHMAP1_CH8SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP2 register.
//
//******************************************************************************
#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
#define UDMA_CHMAP2_CH23SEL_S 28
#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
#define UDMA_CHMAP2_CH22SEL_S 24
#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
#define UDMA_CHMAP2_CH21SEL_S 20
#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
#define UDMA_CHMAP2_CH20SEL_S 16
#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
#define UDMA_CHMAP2_CH19SEL_S 12
#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
#define UDMA_CHMAP2_CH18SEL_S 8
#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
#define UDMA_CHMAP2_CH17SEL_S 4
#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
#define UDMA_CHMAP2_CH16SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_CHMAP3 register.
//
//******************************************************************************
#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
#define UDMA_CHMAP3_CH31SEL_S 28
#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
#define UDMA_CHMAP3_CH30SEL_S 24
#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
#define UDMA_CHMAP3_CH29SEL_S 20
#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
#define UDMA_CHMAP3_CH28SEL_S 16
#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
#define UDMA_CHMAP3_CH27SEL_S 12
#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
#define UDMA_CHMAP3_CH26SEL_S 8
#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
#define UDMA_CHMAP3_CH25SEL_S 4
#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
#define UDMA_CHMAP3_CH24SEL_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the UDMA_O_PV register.
//
//******************************************************************************
#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision
#define UDMA_PV_MAJOR_S 8
#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision
#define UDMA_PV_MINOR_S 0
#endif // __HW_UDMA_H__

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/*
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef __HW_WDT_H__
#define __HW_WDT_H__
//*****************************************************************************
//
// The following are defines for the WDT register offsets.
//
//*****************************************************************************
#define WDT_O_LOAD 0x00000000
#define WDT_O_VALUE 0x00000004
#define WDT_O_CTL 0x00000008
#define WDT_O_ICR 0x0000000C
#define WDT_O_RIS 0x00000010
#define WDT_O_MIS 0x00000014
#define WDT_O_TEST 0x00000418
#define WDT_O_LOCK 0x00000C00
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOAD register.
//
//******************************************************************************
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
#define WDT_LOAD_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_VALUE register.
//
//******************************************************************************
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
#define WDT_VALUE_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_CTL register.
//
//******************************************************************************
#define WDT_CTL_WRC 0x80000000 // Write Complete
#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit
// is not used in cc3xx, WDOG shall
// always generate RESET to system
// irrespective of this bit setting.
#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_ICR register.
//
//******************************************************************************
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
#define WDT_ICR_S 0
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_RIS register.
//
//******************************************************************************
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_MIS register.
//
//******************************************************************************
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_TEST register.
//
//******************************************************************************
#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable
#define WDT_TEST_STALL_EN_S 10
#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
//******************************************************************************
//
// The following are defines for the bit fields in the WDT_O_LOCK register.
//
//******************************************************************************
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
#define WDT_LOCK_S 0
#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
#define WDT_LOCK_LOCKED 0x00000001 // Locked
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
//*****************************************************************************
//
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and
// WDT_MIS registers.
//
//*****************************************************************************
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired
#endif // __HW_WDT_H__

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/*
* Copyright (c) 2016-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== ADC.c ========
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/ADC.h>
#include <ti/drivers/dpl/HwiP.h>
extern const ADC_Config ADC_config[];
extern const uint_least8_t ADC_count;
/* Default ADC parameters structure */
const ADC_Params ADC_defaultParams = {
.custom = NULL,
.isProtected = true
};
static bool isInitialized = false;
/*
* ======== ADC_close ========
*/
void ADC_close(ADC_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== ADC_control ========
*/
int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, void *arg)
{
return (handle->fxnTablePtr->controlFxn(handle, cmd, arg));
}
/*
* ======== ADC_convert ========
*/
int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value)
{
return (handle->fxnTablePtr->convertFxn(handle, value));
}
/*
* ======== ADC_convertToMicroVolts ========
*/
uint32_t ADC_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue)
{
return (handle->fxnTablePtr->convertToMicroVolts(handle, adcValue));
}
/*
* ======== ADC_init ========
*/
void ADC_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < ADC_count; i++) {
ADC_config[i].fxnTablePtr->initFxn((ADC_Handle)&(ADC_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== ADC_open ========
*/
ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params)
{
ADC_Handle handle = NULL;
if (isInitialized && (index < ADC_count)) {
/* If params are NULL use defaults */
if (params == NULL) {
params = (ADC_Params *) &ADC_defaultParams;
}
/* Get handle for this driver instance */
handle = (ADC_Handle) &(ADC_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== ADC_Params_init ========
*/
void ADC_Params_init(ADC_Params *params)
{
*params = ADC_defaultParams;
}

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/*
* Copyright (c) 2016-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file ADC.h
*
* @brief ADC driver interface
*
* The ADC header file should be included in an application as follows:
* @code
* #include <ti/drivers/ADC.h>
* @endcode
*
* # Operation #
* The ADC driver operates as a simplified ADC module with only single channel
* sampling support. It also operates on blocking only mode which means users
* have to wait the current sampling finished before starting another sampling.
* The sampling channel needs to be specified in the ADC_open() before calling
* ADC_convert().
*
* The APIs in this driver serve as an interface to a typical TI-RTOS
* application. The specific peripheral implementations are responsible to
* create all the SYS/BIOS specific primitives to allow for thread-safe
* operation.
* User can use the ADC driver or the ADCBuf driver that has more features.
* But both ADC and ADCBuf cannot be used together in an application.
*
* ## Opening the driver #
*
* @code
* ADC_Handle adc;
* ADC_Params params;
*
* ADC_Params_init(&params);
* adc = ADC_open(Board_ADCCHANNEL_A0, &params);
* if (adc == NULL) {
* // ADC_open() failed
* while (1);
* }
* @endcode
*
* ## Converting #
* An ADC conversion with a ADC peripheral is started by calling ADC_convert().
* The result value is returned by ADC_convert() once the conversion is
* finished.
*
* @code
* int_fast16_t res;
* uint_fast16_t adcValue;
*
* res = ADC_convert(adc, &adcValue);
* if (res == ADC_STATUS_SUCCESS) {
* //use adcValue
* }
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* ADC_FxnTable.
*
* The ADC driver interface module is joined (at link time) to a
* NULL-terminated array of ADC_Config data structures named *ADC_config*.
* *ADC_config* is implemented in the application with each entry being an
* instance of a ADC peripheral. Each entry in *ADC_config* contains a:
* - (ADC_FxnTable *) to a set of functions that implement a ADC peripheral
* - (void *) data object that is associated with the ADC_FxnTable
* - (void *) hardware attributes that are associated to the ADC_FxnTable
*
* # Instrumentation #
* The ADC driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_ADC__include
#define ti_drivers_ADC__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stdint.h>
/**
* @brief Define to support deprecated API ADC_convertRawToMicroVolts.
*
* It is succeeded by the generic ADC_convertToMicroVolts.
*/
#define ADC_convertRawToMicroVolts ADC_convertToMicroVolts
/**
* @defgroup ADC_CONTROL ADC_control command and status codes
* These ADC macros are reservations for ADC.h
* @{
*/
/*!
* Common ADC_control command code reservation offset.
* ADC driver implementations should offset command codes with ADC_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0
* #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1
* @endcode
*/
#define ADC_CMD_RESERVED (32)
/*!
* Common ADC_control status code reservation offset.
* ADC driver implementations should offset status codes with
* ADC_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0
* #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1
* #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2
* @endcode
*/
#define ADC_STATUS_RESERVED (-32)
/*!
* @brief Successful status code returned by ADC_control().
*
* ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed
* successfully.
* @{
* @ingroup ADC_CONTROL
*/
#define ADC_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by ADC_control().
*
* ADC_control() returns ADC_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define ADC_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by ADC_control() for undefined
* command codes.
*
* ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define ADC_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup ADC_CMD Command Codes
* ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC
* driver implementations support these command codes.
* @{
* @ingroup ADC_CONTROL
*/
/* Add ADC_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from a ADC_open() call.
*/
typedef struct ADC_Config_ *ADC_Handle;
/*!
* @brief ADC Parameters
*
* ADC parameters are used to with the ADC_open() call. Only custom argument
* is supported in the parameters. Default values for these parameters are
* set using ADC_Params_init().
*
* @sa ADC_Params_init()
*/
typedef struct ADC_Params_ {
void *custom; /*!< Custom argument used by driver
implementation */
bool isProtected; /*!< By default ADC uses a semaphore
to guarantee thread safety. Setting
this parameter to 'false' will eliminate
the usage of a semaphore for thread
safety. The user is then responsible
for ensuring that parallel invocations
of ADC_convert() are thread safe. */
} ADC_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_close().
*/
typedef void (*ADC_CloseFxn) (ADC_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_control().
*/
typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_ConvertFxn().
*/
typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t *value);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_convertToMicroVolts().
*/
typedef uint32_t (*ADC_ConvertToMicroVoltsFxn) (ADC_Handle handle,
uint16_t adcValue);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_init().
*/
typedef void (*ADC_InitFxn) (ADC_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADC_open().
*/
typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params *params);
/*!
* @brief The definition of a ADC function table that contains the
* required set of functions to control a specific ADC driver
* implementation.
*/
typedef struct ADC_FxnTable_ {
/*! Function to close the specified peripheral */
ADC_CloseFxn closeFxn;
/*! Function to perform implementation specific features */
ADC_ControlFxn controlFxn;
/*! Function to initiate a ADC single channel conversion */
ADC_ConvertFxn convertFxn;
/*! Function to convert ADC result to microvolts */
ADC_ConvertToMicroVoltsFxn convertToMicroVolts;
/*! Function to initialize the given data object */
ADC_InitFxn initFxn;
/*! Function to open the specified peripheral */
ADC_OpenFxn openFxn;
} ADC_FxnTable;
/*!
* @brief ADC Global configuration
*
* The ADC_Config structure contains a set of pointers used to characterize
* the ADC driver implementation.
*
* This structure needs to be defined before calling ADC_init() and it must
* not be changed thereafter.
*
* @sa ADC_init()
*/
typedef struct ADC_Config_ {
/*! Pointer to a table of driver-specific implementations of ADC APIs */
ADC_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} ADC_Config;
/*!
* @brief Function to close a ADC driver
*
* @pre ADC_open() has to be called first.
*
* @param handle An ADC handle returned from ADC_open()
*
* @sa ADC_open()
*/
extern void ADC_close(ADC_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* ADC_Handle.
*
* @pre ADC_open() has to be called first.
*
* @param handle A ADC handle returned from ADC_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param arg An optional R/W (read/write) argument that is
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa ADC_open()
*/
extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to perform ADC conversion
*
* Function to perform ADC single channel single sample conversion.
*
* @pre ADC_open() has been called
*
* @param handle An ADC_Handle
* @param value A pointer to the conversion result
*
* @return The return value indicates the conversion is succeeded or
* failed. The value could be ADC_STATUS_SUCCESS or
* ADC_STATUS_ERROR.
*
* @sa ADC_open()
* @sa ADC_close()
*/
extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value);
/*!
* @brief Function performs conversion from ADC result to actual value in
* microvolts.
*
* @pre ADC_open() and ADC_convert() has to be called first.
*
* @param handle A ADC handle returned from ADC_open()
*
* @param adcValue A sampling result return from ADC_convert()
*
* @return The actual sampling result in micro volts unit.
*
* @sa ADC_open()
*/
extern uint32_t ADC_convertToMicroVolts(ADC_Handle handle,
uint16_t adcValue);
/*!
* @brief Function to initializes the ADC driver
*
* @pre The ADC_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other ADC driver APIs.
*/
extern void ADC_init(void);
/*!
* @brief Function to initialize the ADC peripheral
*
* Function to initialize the ADC peripheral specified by the
* particular index value.
*
* @pre ADC_init() has been called
*
* @param index Logical peripheral number for the ADC indexed into
* the ADC_config table
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A ADC_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa ADC_init()
* @sa ADC_close()
*/
extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params);
/*!
* @brief Function to initialize the ADC_Params struct to its defaults
*
* @param params An pointer to ADC_Params structure for
* initialization
*
* Defaults values are:
* custom = NULL
*/
extern void ADC_Params_init(ADC_Params *params);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_ADC__include */

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/*
* Copyright (c) 2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== ADCBuf.c ========
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/ADCBuf.h>
#include <ti/drivers/dpl/HwiP.h>
extern const ADCBuf_Config ADCBuf_config[];
extern const uint_least8_t ADCBuf_count;
/* Default ADC parameters structure */
const ADCBuf_Params ADCBuf_defaultParams = {
.returnMode = ADCBuf_RETURN_MODE_BLOCKING, /*!< Blocking mode */
.blockingTimeout = 25000, /*!< Timeout of 25000 RTOS ticks */
.callbackFxn = NULL, /*!< No callback function */
.recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT, /*!< One-shot measurement */
.samplingFrequency = 10000, /*!< Take samples at 10kHz */
.custom = NULL
};
static bool isInitialized = false;
/*
* ======== ADCBuf_close ========
*/
void ADCBuf_close(ADCBuf_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== ADCBuf_control ========
*/
int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg)
{
return handle->fxnTablePtr->controlFxn(handle, cmd, cmdArg);
}
/*
* ======== ADCBuf_init ========
*/
void ADCBuf_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < ADCBuf_count; i++) {
ADCBuf_config[i].fxnTablePtr->initFxn((ADCBuf_Handle) & (ADCBuf_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== ADCBuf_open ========
*/
ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params)
{
ADCBuf_Handle handle = NULL;
/* Verify driver index and state */
if (isInitialized && (index < ADCBuf_count)) {
/* If params are NULL use defaults */
if (params == NULL) {
params = (ADCBuf_Params *)&ADCBuf_defaultParams;
}
/* Get handle for this driver instance */
handle = (ADCBuf_Handle)&(ADCBuf_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== ADCBuf_Params_init ========
*/
void ADCBuf_Params_init(ADCBuf_Params *params)
{
*params = ADCBuf_defaultParams;
}
/*
* ======== ADCBuf_convert ========
*/
int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount)
{
return (handle->fxnTablePtr->convertFxn(handle, conversions, channelCount));
}
/*
* ======== ADCBuf_convertCancel ========
*/
int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle)
{
return (handle->fxnTablePtr->convertCancelFxn(handle));
}
/*
* ======== ADCBuf_getResolution ========
*/
uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle)
{
return (handle->fxnTablePtr->getResolutionFxn(handle));
}
/*
* ======== ADCBuf_adjustRawValues ========
*/
int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan)
{
return (handle->fxnTablePtr->adjustRawValuesFxn(handle, sampleBuf, sampleCount, adcChan));
}
/*
* ======== ADCBuf_convertAdjustedToMicroVolts ========
*/
int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChan, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount)
{
return (handle->fxnTablePtr->convertAdjustedToMicroVoltsFxn(handle, adcChan, adjustedSampleBuffer, outputMicroVoltBuffer, sampleCount));
}

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/*
* Copyright (c) 2016-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file ADCBuf.h
*
* @brief ADCBuf driver interface
*
* The ADCBuf header file should be included in an application as follows:
* @code
* #include <ti/drivers/ADCBuf.h>
* @endcode
*
* # Operation #
* The ADCBuf driver in TI-RTOS samples an analogue waveform at a specified
* frequency. The resulting samples are transferred to a buffer provided by
* the application. The driver can either take n samples once, or continuously
* sample by double-buffering and providing a callback to process each finished
* buffer.
*
* The APIs in this driver serve as an interface to a typical TI-RTOS
* application. The specific peripheral implementations are responsible to
* create all the SYS/BIOS specific primitives to allow for thread-safe
* operation.
* User can use the ADC driver or the ADCBuf driver. But both ADC and ADCBuf
* cannot be used together in an application.
*
* ## Opening the driver #
*
* @code
* ADCBuf_Handle adcBufHandle;
* ADCBuf_Params adcBufParams;
*
* ADCBuf_Params_init(&adcBufParams);
* adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams);
* @endcode
*
* ## Making a conversion #
* In this context, a conversion refers to taking multiple ADC samples and
* transferring them to an application-provided buffer.
* To start a conversion, the application must configure an ADCBuf_Conversion struct
* and call ADCBuf_convert(). In blocking mode, ADCBuf_convert() will return
* when the conversion is finished and the desired number of samples have been made.
* In callback mode, ADCBuf_convert() will return immediately and the application will
* get a callback when the conversion is done.
*
* @code
* ADCBuf_Conversion blockingConversion;
*
* blockingConversion.arg = NULL;
* blockingConversion.adcChannel = Board_ADCCHANNEL_A1;
* blockingConversion.sampleBuffer = sampleBufferOnePtr;
* blockingConversion.sampleBufferTwo = NULL;
* blockingConversion.samplesRequestedCount = ADCBUFFERSIZE;
*
* if (!ADCBuf_convert(adcBuf, &continuousConversion, 1)) {
* // handle error
* }
* @endcode
*
* ## Canceling a conversion #
* ADCBuf_convertCancel() is used to cancel an ADCBuf conversion when the driver is
* used in ::ADCBuf_RETURN_MODE_CALLBACK.
*
* Calling this API while no conversion is in progress has no effect. If a
* conversion is in progress, it is canceled and the provided callback function
* is called.
*
* In ::ADCBuf_RECURRENCE_MODE_CONTINUOUS, this function must be called to stop the
* conversion. The driver will continue providing callbacks with fresh samples
* until thie ADCBuf_convertCancel() function is called. The callback function is not
* called after ADCBuf_convertCancel() while in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS.
*
* # Implementation #
*
* This module serves as the main interface for TI-RTOS applications. Its
* purpose is to redirect the module's APIs to specific peripheral
* implementations which are specified using a pointer to an ADCBuf_FxnTable.
*
* The ADCBuf driver interface module is joined (at link time) to a
* NULL-terminated array of ADCBuf_Config data structures named *ADCBuf_config*.
* *ADCBuf_config* is implemented in the application with each entry being an
* instance of an ADCBuf peripheral. Each entry in *ADCBuf_config* contains a:
* - (ADCBuf_FxnTable *) to a set of functions that implement an ADCBuf peripheral
* - (void *) data object that is associated with the ADCBuf_FxnTable
* - (void *) hardware attributes that are associated to the ADCBuf_FxnTable
*
* # Instrumentation #
*
* The ADCBuf driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ---------------------------------|
* Diags_USER1 | basic operations performed |
* Diags_USER2 | detailed operations performed |
*
* ============================================================================
*/
#ifndef ti_drivers_adcbuf__include
#define ti_drivers_adcbuf__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @defgroup ADCBUF_CONTROL ADCBuf_control command and status codes
* These ADCBuf macros are reservations for ADCBuf.h
* @{
*/
/*!
* Common ADCBuf_control command code reservation offset.
* ADC driver implementations should offset command codes with ADCBuf_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define ADCXYZ_COMMAND0 ADCBuf_CMD_RESERVED + 0
* #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1
* @endcode
*/
#define ADCBuf_CMD_RESERVED (32)
/*!
* Common ADCBuf_control status code reservation offset.
* ADC driver implementations should offset status codes with
* ADCBuf_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define ADCXYZ_STATUS_ERROR0 ADCBuf_STATUS_RESERVED - 0
* #define ADCXYZ_STATUS_ERROR1 ADCBuf_STATUS_RESERVED - 1
* #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2
* @endcode
*/
#define ADCBuf_STATUS_RESERVED (-32)
/*!
* \brief Success status code returned by:
* ADCBuf_control()
*
* Functions return ADCBuf_STATUS_SUCCESS if the call was executed
* successfully.
* @{
* @ingroup ADCBUF_CONTROL
*/
#define ADCBuf_STATUS_SUCCESS (0)
/*!
* \brief Generic error status code returned by ADCBuf_control().
*
* ADCBuf_control() returns ADCBuf_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define ADCBuf_STATUS_ERROR (-1)
/*!
* \brief An error status code returned by ADCBuf_control() for undefined
* command codes.
*
* ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define ADCBuf_STATUS_UNDEFINEDCMD (-2)
/*!
* \brief An error status code returned by ADCBuf_adjustRawValues() if the
* function is not supported by a particular driver implementation.
*
* ADCBuf_adjustRawValues() returns ADCBuf_STATUS_UNSUPPORTED if the function is
* not supported by the driver implementation.
*/
#define ADCBuf_STATUS_UNSUPPORTED (-3)
/** @}*/
/**
* @defgroup ADCBUF_CMD Command Codes
* ADCBUF_CMD_* macros are general command codes for I2C_control(). Not all ADCBuf
* driver implementations support these command codes.
* @{
* @ingroup ADCBUF_CONTROL
*/
/* Add ADCBUF_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an ADCBuf_open() call.
*/
typedef struct ADCBuf_Config_ *ADCBuf_Handle;
/*!
* @brief
* An ::ADCBuf_Conversion data structure is used with ADCBuf_convert(). It indicates
* which channel to perform the ADC conversion on, how many conversions to make, and where to put them.
* The arg variable is an user-definable argument which gets passed to the
* ::ADCBuf_Callback when the ADC driver is in ::ADCBuf_RETURN_MODE_CALLBACK.
*/
typedef struct ADCBuf_Conversion_ {
uint16_t samplesRequestedCount; /*!< Number of samples to convert and return */
void *sampleBuffer; /*!< Buffer the results of the conversions are stored in */
void *sampleBufferTwo; /*!< A second buffer that is filled in ::ADCBuf_RECURRENCE_MODE_CONTINUOUS mode while
the first buffer is processed by the application. The value is not used in
::ADCBuf_RECURRENCE_MODE_ONE_SHOT mode. */
void *arg; /*!< Argument to be passed to the callback function in ::ADCBuf_RETURN_MODE_CALLBACK */
uint32_t adcChannel; /*!< Channel to perform the ADC conversion on. Mapping of channel to pin or internal signal is device specific. */
} ADCBuf_Conversion;
/*!
* @brief The definition of a callback function used by the ADC driver
* when used in ::ADCBuf_RETURN_MODE_CALLBACK. It is called in a HWI or SWI context depending on the device specific implementation.
*/
typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle,
ADCBuf_Conversion *conversion,
void *completedADCBuffer,
uint32_t completedChannel);
/*!
* @brief ADC trigger mode settings
*
* This enum defines if the driver should make n conversions and return
* or run indefinitely and run a callback function every n conversions.
*/
typedef enum ADCBuf_Recurrence_Mode_ {
/*!
* The driver makes n measurements and returns or runs a callback function depending
* on the ::ADCBuf_Return_Mode setting.
*/
ADCBuf_RECURRENCE_MODE_ONE_SHOT,
/*!
* The driver makes n measurements and then runs a callback function. This process happens
* until the application calls ::ADCBuf_ConvertCancelFxn(). This setting can only be used in
* ::ADCBuf_RETURN_MODE_CALLBACK.
*/
ADCBuf_RECURRENCE_MODE_CONTINUOUS
} ADCBuf_Recurrence_Mode;
/*!
* @brief ADC return mode settings
*
* This enum defines how the ADCBuf_convert() function returns.
* It either blocks or returns immediately and calls a callback function when the provided buffer has been filled.
*/
typedef enum ADCBuf_Return_Mode_ {
/*!
* Uses a semaphore to block while ADC conversions are performed. Context of the call
* must be a Task.
*
* @note Blocking return mode cannot be used in combination with ::ADCBuf_RECURRENCE_MODE_CONTINUOUS
*/
ADCBuf_RETURN_MODE_BLOCKING,
/*!
* Non-blocking and will return immediately. When the conversion
* is finished the configured callback function is called.
*/
ADCBuf_RETURN_MODE_CALLBACK
} ADCBuf_Return_Mode;
/*!
* @brief ADC Parameters
*
* ADC Parameters are used to with the ADCBuf_open() call. Default values for
* these parameters are set using ADCBuf_Params_init().
*
* @sa ADCBuf_Params_init()
*/
typedef struct ADCBuf_Params_ {
uint32_t blockingTimeout; /*!< Timeout for semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */
uint32_t samplingFrequency; /*!< The frequency at which the ADC will produce a sample */
ADCBuf_Return_Mode returnMode; /*!< Return mode for all conversions */
ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */
ADCBuf_Recurrence_Mode recurrenceMode; /*!< One-shot or continuous conversion */
void *custom; /*!< Pointer to a device specific extension of the ADCBuf_Params */
} ADCBuf_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_close().
*/
typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_open().
*/
typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle,
const ADCBuf_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_control().
*/
typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle,
uint_fast8_t cmd,
void *arg);
/*
* @brief A function pointer to a driver specific implementation of
* ADCBuf_init().
*/
typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convert().
*/
typedef int_fast16_t (*ADCBuf_ConvertFxn) (ADCBuf_Handle handle,
ADCBuf_Conversion conversions[],
uint_fast8_t channelCount);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convertCancel().
*/
typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_GetResolution();
*/
typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_adjustRawValues();
*/
typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle,
void *sampleBuffer,
uint_fast16_t sampleCount,
uint32_t adcChannel);
/*!
* @brief A function pointer to a driver specific implementation of
* ADCBuf_convertAdjustedToMicroVolts();
*/
typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) (ADCBuf_Handle handle,
uint32_t adcChannel,
void *adjustedSampleBuffer,
uint32_t outputMicroVoltBuffer[],
uint_fast16_t sampleCount);
/*!
* @brief The definition of an ADCBuf function table that contains the
* required set of functions to control a specific ADC driver
* implementation.
*/
typedef struct ADCBuf_FxnTable_ {
/*! Function to close the specified peripheral */
ADCBuf_CloseFxn closeFxn;
/*! Function to driver implementation specific control function */
ADCBuf_ControlFxn controlFxn;
/*! Function to initialize the given data object */
ADCBuf_InitFxn initFxn;
/*! Function to open the specified peripheral */
ADCBuf_OpenFxn openFxn;
/*! Function to start an ADC conversion with the specified peripheral */
ADCBuf_ConvertFxn convertFxn;
/*! Function to abort a conversion being carried out by the specified peripheral */
ADCBuf_ConvertCancelFxn convertCancelFxn;
/*! Function to get the resolution in bits of the ADC */
ADCBuf_GetResolutionFxn getResolutionFxn;
/*! Function to adjust raw ADC return bit values to values comparable between devices of the same type */
ADCBuf_adjustRawValuesFxn adjustRawValuesFxn;
/*! Function to convert adjusted ADC values to microvolts */
ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn;
} ADCBuf_FxnTable;
/*!
* @brief ADCBuf Global configuration
*
* The ADCBuf_Config structure contains a set of pointers used to characterise
* the ADC driver implementation.
*
* This structure needs to be defined before calling ADCBuf_init() and it must
* not be changed thereafter.
*
* @sa ADCBuf_init()
*/
typedef struct ADCBuf_Config_ {
/*! Pointer to a table of driver-specific implementations of ADC APIs */
const ADCBuf_FxnTable *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} ADCBuf_Config;
/*!
* @brief Function to close an ADC peripheral specified by the ADC handle
*
* @pre ADCBuf_open() has to be called first.
*
* @pre In ADCBuf_RECURRENCE_MODE_CONTINUOUS, the application must call ADCBuf_convertCancel() first.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @sa ADCBuf_open()
*/
extern void ADCBuf_close(ADCBuf_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* ADCBuf_Handle.
*
* @pre ADCBuf_open() has to be called first.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param cmd A command value defined by the driver specific
* implementation
*
* @param cmdArg A pointer to an optional R/W (read/write) argument that
* is accompanied with cmd
*
* @return An ADCBuf_Status describing an error or success state. Negative values
* indicates an error.
*
* @sa ADCBuf_open()
*/
extern int_fast16_t ADCBuf_control(ADCBuf_Handle handle, uint_fast16_t cmd, void *cmdArg);
/*!
* @brief This function initializes the ADC module. This function must
*
* @pre The ADCBuf_Config structure must exist and be persistent before this
* function can be called.
* This function call does not modify any peripheral registers.
* Function should only be called once.
*/
extern void ADCBuf_init(void);
/*!
* @brief This function sets all fields of a specified ADCBuf_Params structure to their
* default values.
*
* @param params A pointer to ADCBuf_Params structure for initialization
*
* Default values are:
* returnMode = ADCBuf_RETURN_MODE_BLOCKING,
* blockingTimeout = 25000,
* callbackFxn = NULL,
* recurrenceMode = ADCBuf_RECURRENCE_MODE_ONE_SHOT,
* samplingFrequency = 10000,
* custom = NULL
*
* ADCBuf_Params::blockingTimeout should be set large enough to allow for the desired number of samples to be
* collected with the specified frequency.
*/
extern void ADCBuf_Params_init(ADCBuf_Params *params);
/*!
* @brief This function opens a given ADCBuf peripheral.
*
* @param index Logical peripheral number for the ADCBuf indexed into
* the ADCBuf_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values.
*
* @return An ADCBuf_Handle on success or a NULL on an error or if it has been
* opened already. If NULL is returned further ADC API calls will
* result in undefined behaviour.
*
* @sa ADCBuf_close()
*/
extern ADCBuf_Handle ADCBuf_open(uint_least8_t index, ADCBuf_Params *params);
/*!
* @brief This function starts a set of conversions on one or more channels.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param conversions A pointer to an array of ADCBuf_Conversion structs with the specific parameters
* for each channel. Only use one ADCBuf_Conversion struct per channel.
*
* @param channelCount The number of channels to convert on in this call. Should be the length of the conversions array.
* Depending on the device, multiple simultaneous conversions may not be supported. See device
* specific implementation.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*
* @sa ADCBuf_convertCancel()
*/
extern int_fast16_t ADCBuf_convert(ADCBuf_Handle handle, ADCBuf_Conversion conversions[], uint_fast8_t channelCount);
/*!
* @brief This function cancels an ADC conversion that is in progress.
*
* This function must be called before calling ADCBuf_close().
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @sa ADCBuf_convert()
*/
extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle);
/*!
* @brief This function returns the resolution in bits of the specified ADC.
*
* @param handle An ADCBuf handle returned from ADCBuf_open().
*
* @return The resolution in bits of the specified ADC.
*
* @pre ADCBuf_open() must have been called prior.
*/
extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle);
/*!
* @brief This function adjusts a raw ADC output buffer such that the result is comparable between devices of the same make.
* The function does the adjustment in-place.
*
* @param handle An ADCBuf handle returned from ADCBuf_open().
*
* @param sampleBuf A buffer full of raw sample values.
*
* @param sampleCount The number of samples to adjust.
*
* @param adcChan The channel the buffer was sampled on.
*
* @return A buffer full of adjusted samples contained in sampleBuffer.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*/
extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, void *sampleBuf, uint_fast16_t sampleCount, uint32_t adcChan);
/*!
* @brief This function converts a raw ADC output value to a value scaled in micro volts.
*
* @param handle An ADCBuf handle returned from ADCBuf_open()
*
* @param adcChan The ADC channel the samples stem from. This parameter is only necessary for certain devices.
* See device specific implementation for details.
*
* @param adjustedSampleBuffer A buffer full of adjusted samples.
*
* @param outputMicroVoltBuffer The output buffer. The conversion does not occur in place due to the differing data type sizes.
*
* @param sampleCount The number of samples to convert.
*
* @return A number of measurements scaled in micro volts inside outputMicroVoltBuffer.
*
* @return ADCBuf_STATUS_SUCCESS if the operation was successful. ADCBuf_STATUS_ERROR or a device specific status is returned otherwise.
*
* @pre ADCBuf_open() must have been called prior.
*
* @pre ADCBuf_adjustRawValues() must be called on adjustedSampleBuffer prior.
*/
extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts(ADCBuf_Handle handle, uint32_t adcChan, void *adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_adcbuf__include */

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/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== AESCCM.c ========
*
* This file contains default values for the AESCCM_Params struct.
*
*/
#include <stdbool.h>
#include <stdlib.h>
#include <ti/drivers/AESCCM.h>
#include <ti/drivers/dpl/SemaphoreP.h>
const AESCCM_Params AESCCM_defaultParams = {
.returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING,
.callbackFxn = NULL,
.nonceInternallyGenerated = false,
.timeout = SemaphoreP_WAIT_FOREVER,
.custom = NULL,
};

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/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file AESCCM.h
*
* @brief AESCCM driver header
*
* @warning This is a beta API. It may change in future releases.
*
* # Overview #
* The Counter with CBC-MAC (CCM) mode of operation is a generic
* authenticated encryption block cipher mode. It can be used with
* any 128-bit block cipher.
* AESCCM combines CBC-MAC with an AES block cipher in CTR mode of operation.
*
* This combination of block cipher modes enables CCM to encrypt messages of any
* length and not only multiples of the block cipher block size.
*
* AESCCM encryption has the following inputs and outputs:
*
* <table>
* <caption id="AESCCM_multi_row">AES-CCM input and output parameters</caption>
* <tr><th>Encryption</th><th>Decryption</th></tr>
* <tr><th colspan=2>Input</th></tr>
* <tr><td>Shared AES key</td><td> Shared AES key</td></tr>
* <tr><td>Nonce</td><td>Nonce</td></tr>
* <tr><td>Cleartext</td><td>Ciphertext (encrypted plaintext + MAC)</td></tr>
* <tr><td>AAD (optional)</td><td>AAD (optional)</td></tr>
* <tr><th colspan=2>Output</th></tr>
* <tr><td>Ciphertext (encrypted plaintext + MAC)</td><td>Cleartext</td></tr>
* </table>
*
* The AES key is a shared secret between the two parties and has a length
* between 128 and 256 bits.
*
* The nonce is generated by the party performing the authenticated
* encryption operation. Within the scope of any authenticated
* encryption key, the nonce value must be unique. That is, the set of
* nonce values used with any given key must not contain any duplicate
* values. Using the same nonce for two different messages encrypted
* with the same key destroys the security properties.
*
* The optional additional authentication data (AAD) is authenticated,
* but not encrypted. Thus, the AAD is not included in the AES-CCM output.
* It can be used to authenticate packet headers.
*
* After the encryption operation, the ciphertext contains the encrypted
* data and the message authentication code (MAC). The MAC can be seen as an
* encrypted fingerprint of the message header and content.
*
* # Usage #
*
* ## Before starting a CCM operation #
*
* Before starting a CCM operation, the application must do the following:
* - Call AESCCM_init() to initialize the driver
* - Call AESCCM_Params_init() to initialize the AESCCM_Params to default values.
* - Modify the AESCCM_Params as desired
* - Call AESCCM_open() to open an instance of the driver
* - Initialize a CryptoKey. These opaque datastructures are representations
* of keying material and its storage. Depending on how the keying material
* is stored (RAM or flash, key store, key blob), the CryptoKey must be
* initialized differently. The AESCCM API can handle all types of CryptoKey.
* However, not all device-specific implementions support all types of CryptoKey.
* Devices without a key store will not support CryptoKeys with keying material
* stored in a key store for example.
* All devices support plaintext CryptoKeys.
*
* ## Starting a CCM operation #
*
* There are two general ways to execute a CCM operation. In one call or multiple.
*
* The AESCCM_oneStepEncrypt and AESCCM_oneStepDecrypt functions do a CCM operation in a single call.
* They will always be the most highly optimized routines with the least overhead and the fastest
* runtime. However, they require all AAD and plaintext or ciphertext data to be
* available to the function at the start of the call. When trying to operate on
* data that is too large to fit into available memory, partial processing would be
* more advisable.
* All devices support single call operations.
* When performing a decryption operation with AESCCM_oneStepDecrypt(), the MAC is
* automatically verified when using AESCCM_RETURN_BEHAVIOR_BLOCKING or AESCCM_RETURN_BEHAVIOR_POLLING.
* When using AESCCM_RETURN_BEHAVIOR_CALLBACK however, the application's registered
* callback function must call AESCCM_verifyMac() itself to ensure that the computed
* and transmitted MACs match.
*
* The partial processing functions split the setup, processing of the AAD, processing
* of the plaintext or ciphertext, and computation or verification of the MAC into
* multiple calls. The AAD and payload processing functions may be called on buffers
* smaller than the total AAD and payload sizes.
* Not all devices support partial processing. The hardware or software implementations
* of the CCM mode of operation available on a specific device may not be designed to
* support partial processing.
*
* ## After the CCM operation completes #
*
* After the CCM operation completes, the application should either start another operation
* or close the driver by calling AESCCM_close()
*
* ## AESCCM Driver Configuration #
*
* In order to use the AESCCM APIs, the application is required
* to provide device-specific AESCCM configuration in the Board.c file.
* The AESCCM driver interface defines a configuration data structure:
*
* @code
* typedef struct AESCCM_Config_ {
* void *object;
* void const *hwAttrs;
* } AESCCM_Config;
* @endcode
*
* The application must declare an array of AESCCM_Config elements, named
* AESCCM_config[]. Each element of AESCCM_config[] must be populated with
* pointers to a device specific AESCCM driver implementation's driver object and
* hardware attributes. The hardware attributes define properties such
* as the AESCCM peripheral's base address.
* Each element in AESCCM_config[] corresponds to an AESCCM instance
* and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as AESCCM0 or AESCCM1). For example, it is
* possible to use AESCCM_config[0] for AESCCM1. Multiple drivers and driver
* instances may all access the same underlying hardware. This is transparent
* to the application. Mutual exclusion is performed automatically by the
* drivers as necessary.
*
* Because the AESCCM configuration is very device dependent, you will need to
* check the doxygen for the device specific AESCCM implementation. There you
* will find a description of the AESCCM hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the AESCCM
* configuration.
*
* ## AESCCM Parameters
*
* The #AESCCM_Params structure is passed to the AESCCM_open() call. If NULL
* is passed for the parameters, AESCCM_open() uses default parameters.
* A #AESCCM_Params structure is initialized with default values by passing
* it to AESCCM_Params_init().
* Some of the AESCCM parameters are described below. To see brief descriptions
* of all the parameters, see #AESCCM_Params.
*
* ## AESCCM Return Behavior
* The AESCCM driver supports three return behaviors when processing data: blocking, polling, and
* callback. The return behavior is determined by the returnBehavior parameter
* in the AESCCM_Params data structure. The AESCCM driver
* defaults to blocking mode, if the application does not set it.
* Once an AESCCM driver is opened, the only way to change the return behavior
* is to close and re-open the AESCCM instance with the new return behavior.
*
* In blocking mode, a task's code execution is blocked until an AESCCM
* operation has completed. This ensures that only one AESCCM operation
* operates at a given time. Other tasks requesting AESCCM operations while
* a operation is currently taking place are also placed into a blocked
* state. AESCCM operations are executed in the order in which they were
* received. In blocking mode, you cannot perform AESCCM operations
* in the context of a software or hardware ISR.
*
* In callback mode, an AESCCM operation functions asynchronously, which
* means that it does not block code execution. After an AESCCM operation
* has been completed, the AESCCM driver calls a user-provided hook function.
* Callback mode is supported in the task, SWI, and HWI execution context,
* However, if an AESCCM operation is requested while a operation is taking place,
* the call returns an error code.
*
* In polling mode, an AESCCM operation behaves the almost the same way as
* in blocking mode. Instead of pending on a semaphore and letting other
* scheduled tasks run, the application task, SWI, or HWI continuously polls
* a flag until the operation completes. If an AESCCM operation is
* requested while a operation is taking place, the call returns an error code.
* When starting an AESCCM operation in polling mode from HWI or SWI context,
* the AESCCM HWI and SWI must be configured to have a higher priority to pre-empt
* the polling context.
*
* ## Examples
*
* ### Single call CCM encryption + authentication with plaintext CryptoKey in blocking return mode #
* @code
*
* #include <ti/drivers/AESCCM.h>
* #include <ti/drivers/types/cryptoKey/CryptoKey_Plaintext.h>
*
* ...
*
* AESCCM_Handle handle;
* CryptoKey cryptoKey;
* int_fast16_t encryptionResult;
* uint8_t nonce[] = "Thisisanonce";
* uint8_t aad[] = "This string will be authenticated but not encrypted.";
* uint8_t plaintext[] = "This string will be encrypted and authenticated.";
* uint8_t mac[16];
* uint8_t ciphertext[sizeof(plaintext)];
* uint8_t keyingMaterial[32] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
* 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
* 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
* 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F}
*
* handle = AESCCM_open(0, NULL);
*
* if (handle == NULL) {
* // handle error
* }
*
* CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial));
*
* encryptionResult = AESCCM_oneStepEncrypt(handle,
* &cryptoKey,
* aad, sizeof(aad),
* plaintext, sizeof(plaintext),
* nonce, sizeof(nonce),
* mac, sizeof(mac),
* ciphertext);
*
* if (encryptionResult != AESCCM_STATUS_SUCCESS) {
* // handle error
* }
*
* AESCCM_close(handle);
*
* @endcode
*
* ### Single call CCM decryption + verification with plaintext CryptoKey in callback return mode #
* @code
*
* #include <ti/drivers/AESCCM.h>
* #include <ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h>
*
* ...
*
* // The following test vector is Packet Vector 1 from RFC 3610 of the IETF.
*
* uint8_t nonce[] = {0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xA0,
* 0xA1, 0xA2, 0xA3, 0xA4, 0xA5};
* uint8_t aad[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07};
* uint8_t mac[] = {0x17, 0xE8, 0xD1, 0x2C, 0xFD, 0xF9, 0x26, 0xE0};
* uint8_t ciphertext[] = {0x58, 0x8C, 0x97, 0x9A, 0x61, 0xC6, 0x63, 0xD2,
* 0xF0, 0x66, 0xD0, 0xC2, 0xC0, 0xF9, 0x89, 0x80,
* 0x6D, 0x5F, 0x6B, 0x61, 0xDA, 0xC3, 0x84};
* uint8_t keyingMaterial[] = {0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
* 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF};
* uint8_t plaintext[sizeof(ciphertext)];
*
* // The plaintext should be the following after the decryption operation:
* // {0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
* // 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
* // 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E}
*
*
* void ccmCallback(AESCCM_Handle handle, CryptoKey *processedKey) {
* int_fast16_t verificationResult;
*
* verificationResult = AESCCM_verifyMac(handle, &mac);
*
* if (verificationResult != AESCCM_STATUS_SUCCESS) {
* // handle error
* }
* }
*
* void ccmStartFunction(void) {
* AESCCM_Handle handle;
* AESCCM_Params params;
* CryptoKey cryptoKey;
* int_fast16_t decryptionResult;
*
* AESCCM_Params_init(&params);
* params.returnBehavior = AESCCM_RETURN_BEHAVIOR_CALLBACK;
* params.callbackFxn = ccmCallback;
*
* handle = AESCCM_open(0, &params);
*
* if (handle == NULL) {
* // handle error
* }
*
* CryptoKeyPlaintext_initKey(&cryptoKey, keyingMaterial, sizeof(keyingMaterial));
*
* decryptionResult = AESCCM_oneStepEncrypt(handle,
* &cryptoKey,
* aad, sizeof(aad),
* ciphertext, sizeof(ciphertext),
* nonce, sizeof(nonce),
* mac, sizeof(mac),
* plaintext);
*
* if (encryptionResult != AESCCM_STATUS_SUCCESS) {
* // handle error
* }
*
* // do other things while CCM operation completes in the background
*
* }
*
*
* @endcode
*/
#ifndef ti_drivers_AESCCM__include
#define ti_drivers_AESCCM__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <ti/drivers/cryptoutils/cryptokey/CryptoKey.h>
/**
* @defgroup AESCCM_CONTROL AESCCM_control command and status codes
* These AESCCM macros are reservations for AESCCM.h
* @{
*/
/*!
* Common AESCCM_control command code reservation offset.
* AESCCM driver implementations should offset command codes with AESCCM_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define AESCCMXYZ_CMD_COMMAND0 AESCCM_CMD_RESERVED + 0
* #define AESCCMXYZ_CMD_COMMAND1 AESCCM_CMD_RESERVED + 1
* @endcode
*/
#define AESCCM_CMD_RESERVED (32)
/*!
* Common AESCCM_control status code reservation offset.
* AESCCM driver implementations should offset status codes with
* AESCCM_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define AESCCMXYZ_STATUS_ERROR0 AESCCM_STATUS_RESERVED - 0
* #define AESCCMXYZ_STATUS_ERROR1 AESCCM_STATUS_RESERVED - 1
* #define AESCCMXYZ_STATUS_ERROR2 AESCCM_STATUS_RESERVED - 2
* @endcode
*/
#define AESCCM_STATUS_RESERVED (-32)
/**
* @defgroup AESCCM_STATUS Status Codes
* AESCCM_STATUS_* macros are general status codes returned by AESCCM functions
* @{
* @ingroup AESCCM_CONTROL
*/
/*!
* @brief Successful status code.
*
* Function return AESCCM_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define AESCCM_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code.
*
* Functions return AESCCM_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define AESCCM_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by AESCCM_control() for undefined
* command codes.
*
* AESCCM_control() returns AESCCM_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define AESCCM_STATUS_UNDEFINEDCMD (-2)
/*!
* @brief An error status code returned if the hardware or software resource
* is currently unavailable.
*
* AESCCM driver implementations may have hardware or software limitations on how
* many clients can simultaneously perform operations. This status code is returned
* if the mutual exclusion mechanism signals that an operation cannot currently be performed.
*/
#define AESCCM_STATUS_RESOURCE_UNAVAILABLE (-3)
/*!
* @brief An error status code returned if the MAC provided by the application for
* a decryption operation does not match the one calculated during the operation.
*
* This code is returned by AESCCM_oneStepDecrypt() and AESCCM_verifyMAC() if the
* verification of the MAC fails.
*/
#define AESCCM_STATUS_MAC_INVALID (-4)
/** @}*/
/**
* @defgroup AESCCM_CMD Command Codes
* AESCCM_CMD_* macros are general command codes for AESCCM_control(). Not all AESCCM
* driver implementations support these command codes.
* @{
* @ingroup AESCCM_CONTROL
*/
/* Add AESCCM_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an AESCCM_open() call.
*/
typedef struct AESCCM_Config_ *AESCCM_Handle;
/*!
* @brief The definition of a callback function used by the AESCCM driver
* when used in ::AESCCM_RETURN_BEHAVIOR_CALLBACK
*
* @param handle Handle of the client that started the CCM operation.
*
* @param processedKey The CryptoKey that the CCM operation was performed with.
*/
typedef void (*AESCCM_CallbackFxn) (AESCCM_Handle handle, CryptoKey *processedKey);
/*!
* @brief The way in which CCM function calls return after performing an
* encryption + authentication or decryption + verification operation.
*
* Not all CCM operations exhibit the specified return behavor. Functions that do not
* require significant computation and cannot offload that computation to a background thread
* behave like regular functions. Which functions exhibit the specfied return behavior is not
* implementation dependent. Specifically, a software-backed implementation run on the same
* CPU as the application will emulate the return behavior while not actually offloading
* the computation to the background thread.
*
* AESCCM functions exhibiting the specified return behavior have restrictions on the
* context from which they may be called.
*
* | | Task | Hwi | Swi |
* |--------------------------------|-------|-------|-------|
* |AESCCM_RETURN_BEHAVIOR_CALLBACK | X | X | X |
* |AESCCM_RETURN_BEHAVIOR_BLOCKING | X | | |
* |AESCCM_RETURN_BEHAVIOR_POLLING | X | X | X |
*
*/
typedef enum AESCCM_ReturnBehavior_ {
AESCCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the
* CCM operation goes on in the background. The registered
* callback function is called after the operation completes.
* The context the callback function is called (task, HWI, SWI)
* is implementation-dependent.
*/
AESCCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while CCM operation goes
* on in the background. CCM operation results are available
* after the function returns.
*/
AESCCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CCM
* operation goes on in the background. CCM operation results
* are available after the function returns.
*/
} AESCCM_ReturnBehavior;
/*!
* @brief Enum for the direction of the CCM operation.
*/
typedef enum AESCCM_Mode_ {
AESCCM_MODE_ENCRYPT = 1,
AESCCM_MODE_DECRYPT = 2,
} AESCCM_Mode;
/*!
* @brief CCM Parameters
*
* CCM Parameters are used to with the AESCCM_open() call. Default values for
* these parameters are set using AESCCM_Params_init().
*
* @sa AESCCM_Params_init()
*/
typedef struct AESCCM_Params_ {
AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */
AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */
bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into the AESCCM_setupEncrypt()
* and AESCCM_oneStepEncrypt() functions will be overwritten with a
* randomly generated nonce.
*/
uint32_t timeout;
void *custom; /*!< Custom argument used by driver
* implementation
*/
} AESCCM_Params;
/*!
* @brief AESCCM Global configuration
*
* The AESCCM_Config structure contains a set of pointers used to characterize
* the AESCCM driver implementation.
*
* This structure needs to be defined before calling AESCCM_init() and it must
* not be changed thereafter.
*
* @sa AESCCM_init()
*/
typedef struct AESCCM_Config_ {
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} AESCCM_Config;
/*!
* @brief Default AESCCM_Params structure
*
* @sa AESCCM_Params_init()
*/
extern const AESCCM_Params AESCCM_defaultParams;
/*!
* @brief This function initializes the CCM module.
*
* @pre The AESCCM_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other CCM driver APIs. This function call does not modify any
* peripheral registers.
*/
void AESCCM_init(void);
/*!
* @brief Function to initialize the AESCCM_Params struct to its defaults
*
* @param params An pointer to AESCCM_Params structure for
* initialization
*
* Defaults values are:
* returnBehavior = AESCCM_RETURN_BEHAVIOR_BLOCKING
* callbackFxn = NULL
* nonceInternallyGenerated = false
* timeout = SemaphoreP_WAIT_FOREVER
* custom = NULL
*/
void AESCCM_Params_init(AESCCM_Params *params);
/*!
* @brief This function opens a given CCM peripheral.
*
* @pre CCM controller has been initialized using AESCCM_init()
*
* @param index Logical peripheral number for the CCM indexed into
* the AESCCM_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values.
*
* @return A AESCCM_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa AESCCM_init()
* @sa AESCCM_close()
*/
AESCCM_Handle AESCCM_open(uint_least8_t index, AESCCM_Params *params);
/*!
* @brief Function to close a CCM peripheral specified by the CCM handle
*
* @pre AESCCM_open() has to be called first.
*
* @param handle A CCM handle returned from AESCCM_open()
*
* @sa AESCCM_open()
*/
void AESCCM_close(AESCCM_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* AESCCM_Handle.
*
* Commands for AESCCM_control can originate from AESCCM.h or from implementation
* specific AESCCM*.h (_AESCCMCC26XX.h_, _AESCCMMSP432.h_, etc.. ) files.
* While commands from AESCCM.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific AESCCM*.h files add
* unique driver capabilities but are not API portable across all AESCCM driver
* implementations.
*
* Commands supported by AESCCM.h follow an AESCCM_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by AESCCM*.h follow an AESCCM*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref AESCCM_CMD "AESCCM_control command codes" for command codes.
*
* See @ref AESCCM_STATUS "AESCCM_control return status codes" for status codes.
*
* @pre AESCCM_open() has to be called first.
*
* @param handle A AESCCM handle returned from AESCCM_open()
*
* @param cmd AESCCM.h or AESCCM*.h commands.
*
* @param args An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa AESCCM_open()
*/
int_fast16_t AESCCM_control(AESCCM_Handle handle, uint32_t cmd, void *args);
/*!
* @brief Function to set up an AESCCM encryption + authentication operation in multiple calls.
*
* @pre AESCCM_open() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] key A previously initialized CryptoKey
*
* @param [in] aadTotalLength Total length of the additional authentication data in bytes.
* Either \c aadTotalLength or \c plaintextTotalLength must be non-zero.
*
* @param [in] plaintextTotalLength Total length of the plaintext in bytes.
* Either \c aadTotalLength or \c plaintextTotalLength must be non-zero.
*
* @param [in,out] nonce A buffer containing a nonce. Nonces must be unique to each CCM operation and
* may not be reused. If nonceInternallyGenerated was set in the AESCCM_Params,
* the nonce will be generated by this function call and copied to this buffer.
*
* @param [in] nonceLength Length of \c nonce in bytes.
* Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}.
*
* @param [in] macLength Length of the message authentication code in bytes.
* Valid MAC lengths are [0, 1, ... 16].
*
* @return A status code
*
* @post AESCCM_processAAD() must be called next.
*
* @sa AESCCM_setupDecrypt()
*/
int_fast16_t AESCCM_setupEncrypt(AESCCM_Handle handle,
CryptoKey *key,
uint8_t *nonce, uint8_t nonceLength,
size_t aadTotalLength,
size_t plaintextTotalLength,
uint8_t macLength);
/*!
* @brief Function to set up an AESCCM decryption + verification operation in multiple calls.
*
* @pre AESCCM_open() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] key A previously initialized CryptoKey
*
* @param [in] aadTotalLength Total length of the additional authentication data in bytes.
* Either \c aadTotalLength or \c plaintextTotalLength must be non-zero.
*
* @param [in] ciphertextTotalLength Total length of the ciphertext in bytes.
* Either \c aadTotalLength or \c ciphertextTotalLength must be non-zero.
*
* @param [in] nonce A buffer containing the nonce transmitted with the ciphertext and AAD.
*
* @param [in] nonceLength Length of \c nonce in bytes.
* Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}.
*
* @param [in] macLength Length of the message authentication code in bytes.
* Valid MAC lengths are [0, 1, ... 16].
*
* @return A status code
*
* @post AESCCM_processAAD() must be called next.
*
* @sa AESCCM_setupEncrypt()
*/
int_fast16_t AESCCM_setupDecrypt(AESCCM_Handle handle,
CryptoKey *key,
uint8_t *nonce, uint8_t nonceLength,
size_t aadTotalLength,
size_t ciphertextTotalLength,
uint8_t macLength);
/*!
* @brief Function to process the additional authentication data in one or more calls.
*
* @pre AESCCM_setupDecrypt(), AESCCM_setupEncrypt(), or AESCCM_processAAD() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] aad A buffer of length \c length containing additional authentication data
* to be authenticated but not encrypted.
*
* @param [in] length Length of \c aad in bytes. Must be non-zero. May be smaller than the
* total AAD length provided in the setup call. This enables partial processing
* of longer AAD.
*
* @return A status code
*
* @post AESCCM_processPayload() or AESCCM_processAAD() must be called next.
*/
int_fast16_t AESCCM_processAAD(AESCCM_Handle handle, uint8_t *aad, size_t length);
/*!
* @brief Function to process the input data in one or more calls.
*
* @pre AESCCM_processAAD() or AESCCM_processPayload() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] input A buffer of length \c length containing either plaintext or ciphertext depending
* on the AESCCM_Mode.
*
* @param [in] length Length of \c input and output in bytes. Must be non-zero. May be smaller than the
* total input length provided in the setup call. This enables partial processing
* of longer inputs.
*
* @param [out] output A buffer of length \c length that is filled with either ciphertext or plaintext
* depending on the AESCCM_Mode after processing.
*
* @return A status code
*
* @post AESCCM_processPayload(), AESCCM_computeMAC(), or AESCCM_verifyMAC() must be called next.
*/
int_fast16_t AESCCM_processPayload(AESCCM_Handle handle, uint8_t *input, size_t length, uint8_t *output);
/*!
* @brief Function to compute the message authentication code.
*
* @pre AESCCM_processPayload() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] mac A buffer that the computed MAC is copied to.
*
* @return A status code
*
*/
int_fast16_t AESCCM_computeMAC(AESCCM_Handle handle, uint8_t *mac);
/*!
* @brief Function to verify the provided message authentication code.
*
* @pre AESCCM_processPayload() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] mac A buffer containing the MAC that the computed one will be verified against.
*
* @return A status code
*
*/
int_fast16_t AESCCM_verifyMAC(AESCCM_Handle handle, uint8_t *mac);
/*!
* @brief Function to perform an AESCCM encryption + authentication operation in one call.
*
* @note None of the buffers provided as arguments may be altered by the application during an ongoing operation.
* Doing so can yield corrupted ciphertext or incorrect authentication.
*
* @pre AESCCM_open() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] key A previously initialized CryptoKey
*
* @param [in] aad A buffer of length \c aadLength containing additional authentication data
* to be authenticated but not encrypted.
*
* @param [in] aadLength Length of \c aad in bytes. Either \c aadLength or \c plaintextLength must be
* non-zero.
*
* @param [in] plaintext The plaintext buffer to be encrypted and authenticated in the CCM operation.
*
* @param [in] plaintextLength Length of \c plaintext in bytes. Either \c aadLength or \c plaintextLength must be
* non-zero.
*
* @param [in,out] nonce A buffer containing a nonce. Nonces must be unique to each CCM operation and
* may not be reused. If nonceInternallyGenerated was set in the AESCCM_Params,
* the nonce will be generated by this function call and copied to this buffer.
*
* @param [in] nonceLength Length of \c nonce in bytes.
* Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}.
*
* @param [out] mac The message authentication code buffer to store the encrypted authentication tag.
*
* @param [in] macLength Length of \c mac in bytes.
* Valid MAC lengths are [0, 1, ... 16].
*
* @param [out] ciphertext The output ciphertext buffer that the encrypted plaintext is copied to.
* It is of length \c plaintextLength.
*
* @return A status code
*
* @sa AESCCM_oneStepDecrypt()
*/
int_fast16_t AESCCM_oneStepEncrypt(AESCCM_Handle handle,
CryptoKey *key,
uint8_t *aad, size_t aadLength,
uint8_t *plaintext, size_t plaintextLength,
uint8_t *nonce, uint8_t nonceLength,
uint8_t *mac, uint8_t macLength,
uint8_t *ciphertext);
/*!
* @brief Function to perform an AESCCM decryption + verification operation in one call.
*
* @note None of the buffers provided as arguments may be altered by the application during an ongoing operation.
* Doing so can yield corrupted plaintext or incorrectly failed verification.
*
* @pre AESCCM_open() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [in] key A previously initialized CryptoKey
*
* @param [in] aad A buffer of length \c aadLength containing additional authentication data
* to be verified but not decrypted.
*
* @param [in] aadLength Length of \c aad in bytes. Either \c aadLength or \c plaintextLength must be
* non-zero.
*
* @param [in] ciphertext The ciphertext buffer to be decrypted and verified in the CCM operation.
*
* @param [in] ciphertextLength Length of \c plaintext in bytes. Either \c aadLength or \c plaintextLength must be
* non-zero.
*
* @param [in] nonce A buffer containing the nonce transmitted with the ciphertext and AAD.
*
* @param [in] nonceLength Length of \c nonce in bytes.
* Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}.
*
* @param [in] mac The message authentication code buffer containing the encrypted authentication tag.
*
* @param [in] macLength Length of \c mac in bytes.
* Valid MAC lengths are [0, 1, ... 16].
*
* @param [out] plaintext The output plaintext buffer that the decrypted ciphertext is copied to.
* It is of length \c ciphertexttextLength.
*
* @return A status code
*
* @sa AESCCM_oneStepEncrypt()
*/
int_fast16_t AESCCM_oneStepDecrypt(AESCCM_Handle handle,
CryptoKey *key,
uint8_t *aad, size_t aadLength,
uint8_t *ciphertext, size_t ciphertextLength,
uint8_t *nonce, uint8_t nonceLength,
uint8_t *mac, uint8_t macLength,
uint8_t *plaintext);
/*!
* @brief Returns the AESCCM_Mode of an AESCCM operation in progress.
*
* @pre AESCCM_setupEncrypt() or AESCCM_setupDecrypt() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] mode Whether the operation in progress is a decryption or encryption operation
*
* @return A status code
*/
int_fast16_t AESCCM_getMode(AESCCM_Handle handle, AESCCM_Mode *mode);
/*!
* @brief Returns a pointer to the CryptoKey used for an AESCCM operation in progress.
*
* @pre AESCCM_setupEncrypt() or AESCCM_setupDecrypt() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] key The CryptoKey used in the operation
*
* @return A status code
*/
int_fast16_t AESCCM_getCryptoKey(AESCCM_Handle handle, CryptoKey **key);
/*!
* @brief Returns a pointer to the nonce and the nonce length of an AESCCM operation in progress.
*
* @pre AESCCM_setupEncrypt() or AESCCM_setupDecrypt() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] nonce The nonce used in the operation
*
* @param [out] nonceLength The length of the nonce used in the operation
*
* @return A status code
*/
int_fast16_t AESCCM_getNonce(AESCCM_Handle handle, uint8_t **nonce, uint8_t *nonceLength);
/*!
* @brief Returns a pointer to the AAD and the AAD length of an AESCCM operation in progress.
*
* @pre AESCCM_processAAD() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] aad The AAD used in the operation
*
* @param [out] aadLength The length of the AAD used in the operation
*
* @return A status code
*/
int_fast16_t AESCCM_getAAD(AESCCM_Handle handle, uint8_t **aad, size_t *aadLength);
/*!
* @brief Returns a pointer to the input (plaintext or ciphertext) and the input length of an AESCCM operation in progress.
*
* @pre AESCCM_processPayload() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] input The last input buffer used in the operation
*
* @param [out] inputLength The length of the last input buffer used in the operation
*
* @param [out] totalInputLength The total length of the input specified in the setup call. It is the same as the total length of the input.
*
* @return A status code
*/
int_fast16_t AESCCM_getInput(AESCCM_Handle handle, uint8_t **input, size_t *inputLength, size_t *totalInputLength);
/*!
* @brief Returns a pointer to the output (plaintext or ciphertext) and the output length of an AESCCM operation in progress.
*
* @pre AESCCM_processPayload() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] output The output buffer used in the operation
*
* @param [out] outputLength The output of the input used in the operation
*
* @param [out] totalOutputLength The total length of the output specified in the setup call. It is the same as the total length of the input.
*
* @return A status code
*/
int_fast16_t AESCCM_getOutput(AESCCM_Handle handle, uint8_t **output, size_t *outputLength, size_t *totalOutputLength);
/*!
* @brief Returns a pointer to the MAC and the MAC length of the last completed AESCCM operation.
*
* @pre AESCCM_verifyMAC() or AESCCM_calculateMAC() has to be called first.
*
* @param [in] handle A CCM handle returned from AESCCM_open()
*
* @param [out] mac The MAC verified or calculated in the operation
*
* @param [out] macLength The length of the MAC
*
* @return A status code
*/
int_fast16_t AESCCM_getMAC(AESCCM_Handle handle, uint8_t *mac, uint8_t *macLength);
int_fast16_t AESCCM_setMACReturnPointer(AESCCM_Handle handle, uint8_t *mac);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_AESCCM__include */

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== Camera.c ========
*/
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/Camera.h>
#include <ti/drivers/dpl/HwiP.h>
extern const Camera_Config Camera_config[];
extern const uint_least8_t Camera_count;
/* Default Camera parameters structure */
const Camera_Params Camera_defaultParams = {
Camera_MODE_BLOCKING, /* captureMode */
24000000, /* outputClock */
Camera_HSYNC_POLARITY_HIGH, /* hsyncPolarity */
Camera_VSYNC_POLARITY_HIGH, /* vsyncPolarity */
Camera_PCLK_CONFIG_RISING_EDGE, /* pixelClkConfig */
Camera_BYTE_ORDER_NORMAL, /* byteOrder */
Camera_INTERFACE_SYNC_ON, /* interfaceSync */
Camera_STOP_CAPTURE_FRAME_END, /* stopConfig */
Camera_START_CAPTURE_FRAME_START, /* startConfig */
Camera_WAIT_FOREVER, /* captureTimeout */
NULL, /* captureCallback */
NULL
};
static bool isInitialized = false;
/*
* ======== Camera_close ========
*/
void Camera_close(Camera_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== Camera_control ========
*/
int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd, void *arg)
{
return (handle->fxnTablePtr->controlFxn(handle, cmd, arg));
}
/*
* ======== Camera_init ========
*/
void Camera_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < Camera_count; i++) {
Camera_config[i].fxnTablePtr->initFxn((Camera_Handle)&(Camera_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== Camera_open ========
*/
Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params)
{
Camera_Handle handle = NULL;
/* Verify driver index and state */
if (isInitialized && (index < Camera_count)) {
/* If params are NULL use defaults. */
if (params == NULL) {
params = (Camera_Params *)&Camera_defaultParams;
}
/* Get handle for this driver instance */
handle = (Camera_Handle)&(Camera_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== Camera_Params_init ========
*/
void Camera_Params_init(Camera_Params *params)
{
*params = Camera_defaultParams;
}
/*
* ======== Camera_capture ========
*/
int_fast16_t Camera_capture(Camera_Handle handle, void *buffer,
size_t bufferlen, size_t *frameLen)
{
return (handle->fxnTablePtr->captureFxn(handle, buffer, bufferlen, frameLen));
}

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/*
* Copyright (c) 2015-2016, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file Camera.h
*
* @brief Camera driver interface
*
* The Camera header file should be included in an application as follows:
* @code
* #include <ti/drivers/Camera.h>
* @endcode
*
* # Overview #
* The Camera driver is used to retrieve the data being transferred by the
* Camera sensor.
* This driver provides an API for capturing the image from the Camera sensor.
* The camera sensor control and implementation are the responsibility of the
* application using the interface.
*
* The Camera driver has been designed to operate in an RTOS environment. It
* protects its transactions with OS primitives supplied by the underlying
* RTOS.
*
* # Usage #
*
* The Camera driver includes the following APIs:
* - Camera_init(): Initialize the Camera driver.
* - Camera_Params_init(): Initialize a #Camera_Params structure with default
* vaules.
* - Camera_open(): Open an instance of the Camera driver.
* - Camera_control(): Performs implemenation-specific features on a given
* Camera peripheral.
* - Camera_capture(): Capture a frame.
* - Camera_close(): De-initialize a given Camera instance.
*
*
* ### Camera Driver Configuration #
*
* In order to use the Camera APIs, the application is required
* to provide device-specific Camera configuration in the Board.c file.
* The Camera driver interface defines a configuration data structure:
*
* @code
* typedef struct Camera_Config_ {
* Camera_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } Camera_Config;
* @endcode
*
* The application must declare an array of Camera_Config elements, named
* Camera_config[]. Each element of Camera_config[] must be populated with
* pointers to a device specific Camera driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the Camera peripheral's base address.
* Each element in Camera_config[] corresponds to
* a Camera instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as Camera0 or Camera1). For example, it
* is possible to use Camera_config[0] for Camera1.
*
* Because the Camera configuration is very device dependent, you will need to
* check the doxygen for the device specific Camera implementation. There you
* will find a description of the Camera hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the Camera
* configuration.
*
* ### Initializing the Camear Driver #
* The application initializes the Camera driver by calling Camera_init().
* This function must be called before any other Camera API. Camera_init()
* iterates through the elements of the Camera_config[] array, calling
* the element's device implementation Camera initialization function.
* ### Camera Parameters
*
* The #Camera_Params structure is passed to Camera_open(). If NULL
* is passed for the parameters, Camera_open() uses default parameters.
* A #Camera_Params structure is initialized with default values by passing
* it to Camera_Params_init().
* Some of the Camera parameters are described below. To see brief descriptions
* of all the parameters, see #Camera_Params.
*
* #### Camera Modes
* The Camera driver operates in either blocking mode or callback mode:
* - #Camera_MODE_BLOCKING: The call to Camera_capture() blocks until the
* capture has completed.
* - #Camera_MODE_CALLBACK: The call to Camera_capture() returns immediately.
* When the capture completes, the Camera driver will call a user-
* specified callback function.
*
* The capture mode is determined by the #Camera_Params.captureMode parameter
* passed to Camera_open(). The Camera driver defaults to blocking mode, if the
* application does not set it.
*
* Once a Camera driver instance is opened, the only way
* to change the capture mode is to close and re-open the Camera
* instance with the new capture mode.
*
* ### Opening the driver #
* The following example opens a Camera driver instance in blocking mode:
* @code
* Camera_Handle handle;
* Camera_Params params;
*
* Camera_Params_init(&params);
* params.captureMode = Camera_MODE_BLOCKING;
* < Change any other params as required >
*
* handle = Camera_open(someCamera_configIndexValue, &params);
* if (!handle) {
* // Error opening the Camera driver
* }
* @endcode
*
* ### Capturing an Image #
*
* The following code example captures a frame.
*
* @code
* unsigned char captureBuffer[1920];
*
* ret = Camera_capture(handle, &captureBuffer, sizeof(captureBuffer));
* @endcode
*
* # Implementation #
*
* This module serves as the main interface for RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to a
* #Camera_FxnTable.
*
* The Camera driver interface module is joined (at link time) to an
* array of #Camera_Config data structures named *Camera_config*.
* *Camera_config* is implemented in the application with each entry being an
* instance of a Camera peripheral. Each entry in *Camera_config* contains a:
* - (Camera_FxnTable *) to a set of functions that implement a Camera
* peripheral
* - (void *) data object that is associated with the Camera_FxnTable
* - (void *) hardware attributes that are associated to the Camera_FxnTable
*
*******************************************************************************
*/
#ifndef ti_drivers_Camera__include
#define ti_drivers_Camera__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stddef.h>
/**
* @defgroup CAMERA_CONTROL Camera_control command and status codes
* These Camera macros are reservations for Camera.h
* @{
*/
/*!
* Common Camera_control command code reservation offset.
* Camera driver implementations should offset command codes with
* CAMERA_CMD_RESERVED growing positively
*
* Example implementation specific command codes:
* @code
* #define CAMERAXYZ_CMD_COMMAND0 CAMERA_CMD_RESERVED + 0
* #define CAMERAXYZ_CMD_COMMAND1 CAMERA_CMD_RESERVED + 1
* @endcode
*/
#define CAMERA_CMD_RESERVED (32)
/*!
* Common Camera_control status code reservation offset.
* Camera driver implementations should offset status codes with
* CAMERA_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define CAMERAXYZ_STATUS_ERROR0 CAMERA_STATUS_RESERVED - 0
* #define CAMERAXYZ_STATUS_ERROR1 CAMERA_STATUS_RESERVED - 1
* #define CAMERAXYZ_STATUS_ERROR2 CAMERA_STATUS_RESERVED - 2
* @endcode
*/
#define CAMERA_STATUS_RESERVED (-32)
/**
* @defgroup Camera_STATUS Status Codes
* Camera_STATUS_* macros are general status codes returned by Camera_control()
* @{
* @ingroup Camera_CONTROL
*/
/*!
* @brief Successful status code returned by Camera_control().
*
* Camera_control() returns CAMERA_STATUS_SUCCESS if the control code was
* executed successfully.
*/
#define CAMERA_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by Camera_control().
*
* Camera_control() returns CAMERA_STATUS_ERROR if the control code was not
* executed successfully.
*/
#define CAMERA_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by Camera_control() for undefined
* command codes.
*
* Camera_control() returns CAMERA_STATUS_UNDEFINEDCMD if the control code is
* not recognized by the driver implementation.
*/
#define CAMERA_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup Camera_CMD Command Codes
* Camera_CMD_* macros are general command codes for Camera_control(). Not all
* Camera driver implementations support these command codes.
* @{
* @ingroup Camera_CONTROL
*/
/* Add Camera_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief Wait forever define
*/
#define Camera_WAIT_FOREVER (~(0U))
/*!
* @brief A handle that is returned from a Camera_open() call.
*/
typedef struct Camera_Config_ *Camera_Handle;
/*!
* @brief The definition of a callback function used by the Camera driver
* when used in ::Camera_MODE_CALLBACK
*
* @param Camera_Handle Camera_Handle
*
* @param buf Pointer to capture buffer
*
* @param frameLength length of frame
*
*/
typedef void (*Camera_Callback) (Camera_Handle handle, void *buf,
size_t frameLength);
/*!
* @brief Camera capture mode settings
*
* This enum defines the capture mode for the
* configured Camera.
*/
typedef enum Camera_CaptureMode_ {
/*!
* Uses a semaphore to block while data is being sent. Context of
* the call must be a Task.
*/
Camera_MODE_BLOCKING,
/*!
* Non-blocking and will return immediately. When the capture
* by the interrupt is finished the configured callback function
* is called.
*/
Camera_MODE_CALLBACK
} Camera_CaptureMode;
/*!
* @brief Camera HSync polarity
*
* This enum defines the polarity of the HSync signal.
*/
typedef enum Camera_HSyncPolarity_ {
Camera_HSYNC_POLARITY_HIGH = 0,
Camera_HSYNC_POLARITY_LOW
} Camera_HSyncPolarity;
/*!
* @brief Camera VSync polarity
*
* This enum defines the polarity of the VSync signal.
*/
typedef enum Camera_VSyncPolarity_ {
Camera_VSYNC_POLARITY_HIGH = 0,
Camera_VSYNC_POLARITY_LOW
} Camera_VSyncPolarity;
/*!
* @brief Camera pixel clock configuration
*
* This enum defines the pixel clock configuration.
*/
typedef enum Camera_PixelClkConfig_ {
Camera_PCLK_CONFIG_RISING_EDGE = 0,
Camera_PCLK_CONFIG_FALLING_EDGE
} Camera_PixelClkConfig;
/*!
* @brief Camera byte order
*
* This enum defines the byte order of camera capture.
*
* In normal mode, the byte order is:
* | byte3 | byte2 | byte1 | byte0 |
*
* In swap mode, the bytes are ordered as:
* | byte2 | byte3 | byte0 | byte1 |
*/
typedef enum Camera_ByteOrder_ {
Camera_BYTE_ORDER_NORMAL = 0,
Camera_BYTE_ORDER_SWAP
} Camera_ByteOrder;
/*!
* @brief Camera interface synchronization
*
* This enum defines the sensor to camera interface synchronization
* configuration.
*/
typedef enum Camera_IfSynchoronisation_ {
Camera_INTERFACE_SYNC_OFF = 0,
Camera_INTERFACE_SYNC_ON
} Camera_IfSynchoronisation;
/*!
* @brief Camera stop capture configuration
*
* This enum defines the stop capture configuration.
*/
typedef enum Camera_StopCaptureConfig_ {
Camera_STOP_CAPTURE_IMMEDIATE = 0,
Camera_STOP_CAPTURE_FRAME_END
} Camera_StopCaptureConfig;
/*!
* @brief Camera start capture configuration
*
* This enum defines the start capture configuration.
*/
typedef enum Camera_StartCaptureConfig_ {
Camera_START_CAPTURE_IMMEDIATE = 0,
Camera_START_CAPTURE_FRAME_START
} Camera_StartCaptureConfig;
/*!
* @brief Camera Parameters
*
* Camera parameters are used to with the Camera_open() call.
* Default values for these parameters are set using Camera_Params_init().
*
* If Camera_CaptureMode is set to Camera_MODE_BLOCKING then Camera_capture
* function calls will block thread execution until the capture has completed.
*
* If Camera_CaptureMode is set to Camera_MODE_CALLBACK then Camera_capture
* will not block thread execution and it will call the function specified by
* captureCallbackFxn.
*
* @sa Camera_Params_init()
*/
typedef struct Camera_Params_ {
/*!< Mode for camera capture */
Camera_CaptureMode captureMode;
/*!< Output clock to set divider */
uint32_t outputClock;
/*!< Polarity of Hsync */
Camera_HSyncPolarity hsyncPolarity;
/*!< Polarity of VSync */
Camera_VSyncPolarity vsyncPolarity;
/*!< Pixel clock configuration */
Camera_PixelClkConfig pixelClkConfig;
/*!< camera capture byte order */
Camera_ByteOrder byteOrder;
/*!< Camera-Sensor synchronization */
Camera_IfSynchoronisation interfaceSync;
/*!< Camera stop configuration */
Camera_StopCaptureConfig stopConfig;
/*!< Camera start configuration */
Camera_StartCaptureConfig startConfig;
/*!< Timeout for capture semaphore */
uint32_t captureTimeout;
/*!< Pointer to capture callback */
Camera_Callback captureCallback;
/*!< Custom argument used by driver implementation */
void *custom;
} Camera_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_close().
*/
typedef void (*Camera_CloseFxn) (Camera_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_control().
*/
typedef int_fast16_t (*Camera_ControlFxn) (Camera_Handle handle,
uint_fast16_t cmd,
void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_init().
*/
typedef void (*Camera_InitFxn) (Camera_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_open().
*/
typedef Camera_Handle (*Camera_OpenFxn) (Camera_Handle handle,
Camera_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* Camera_capture().
*/
typedef int_fast16_t (*Camera_CaptureFxn) (Camera_Handle handle, void *buffer,
size_t bufferlen, size_t *frameLen);
/*!
* @brief The definition of a Camera function table that contains the
* required set of functions to control a specific Camera driver
* implementation.
*/
typedef struct Camera_FxnTable_ {
/*! Function to close the specified peripheral */
Camera_CloseFxn closeFxn;
/*! Function to implementation specific control function */
Camera_ControlFxn controlFxn;
/*! Function to initialize the given data object */
Camera_InitFxn initFxn;
/*! Function to open the specified peripheral */
Camera_OpenFxn openFxn;
/*! Function to initiate a Camera capture */
Camera_CaptureFxn captureFxn;
} Camera_FxnTable;
/*!
* @brief Camera Global configuration
*
* The Camera_Config structure contains a set of pointers used to characterize
* the Camera driver implementation.
*
* This structure needs to be defined before calling Camera_init() and it must
* not be changed thereafter.
*
* @sa Camera_init()
*/
typedef struct Camera_Config_ {
/*! Pointer to a table of driver-specific implementations of Camera APIs */
Camera_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} Camera_Config;
/*!
* @brief Function to close a Camera peripheral specified by the Camera handle
*
* @pre Camera_open() had to be called first.
*
* @param handle A Camera_Handle returned from Camera_open
*
* @sa Camera_open()
*/
extern void Camera_close(Camera_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* Camera_Handle.
*
* Commands for Camera_control can originate from Camera.h or from
* implementation specific Camera*.h (_CameraCC32XX.h_, etc.. ) files.
* While commands from Camera.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific Camera*.h files add
* unique driver capabilities but are not API portable across all Camera driver
* implementations.
*
* Commands supported by Camera.h follow a Camera_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by Camera*.h follow a Camera*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref Camera_CMD "Camera_control command codes" for command codes.
*
* See @ref Camera_STATUS "Camera_control return status codes" for status codes.
*
* @pre Camera_open() has to be called first.
*
* @param handle A Camera handle returned from Camera_open()
*
* @param cmd Camera.h or Camera*.h commands.
*
* @param arg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa Camera_open()
*/
extern int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initializes the Camera module
*
* @pre The Camera_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other Camera driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void Camera_init(void);
/*!
* @brief Function to initialize a given Camera peripheral specified by the
* particular index value. The parameter specifies which mode the
* Camera will operate.
*
* @pre Camera controller has been initialized
*
* @param index Logical peripheral number for the Camera indexed into
* the Camera_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values. All the fields in this structure are
* RO (read-only).
*
* @return A Camera_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa Camera_init()
* @sa Camera_close()
*/
extern Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params);
/*!
* @brief Function to initialize the Camera_Params structure to its defaults
*
* @param params An pointer to Camera_Params structure for
* initialization
*
* Defaults values are:
* captureMode = Camera_MODE_BLOCKING;
* outputClock = 24000000;
* hsyncPolarity = Camera_HSYNC_POLARITY_HIGH;
* vsyncPolarity = Camera_VSYNC_POLARITY_HIGH;
* pixelClkConfig = Camera_PCLK_CONFIG_RISING_EDGE;
* byteOrder = Camera_BYTE_ORDER_NORMAL;
* interfaceSync = Camera_INTERFACE_SYNC_ON;
* stopConfig = Camera_STOP_CAPTURE_FRAME_END;
* startConfig = Camera_START_CAPTURE_FRAME_START;
* captureTimeout = Camera_WAIT_FOREVER;
* captureCallback = NULL;
*/
extern void Camera_Params_init(Camera_Params *params);
/*!
* @brief Function that handles the Camera capture of a frame.
*
* In Camera_MODE_BLOCKING, Camera_capture will block task execution until
* the capture is complete.
*
* In Camera_MODE_CALLBACK, Camera_capture does not block task execution
* and calls a callback function specified by captureCallbackFxn.
* The Camera buffer must stay persistent until the Camera_capture
* function has completed!
*
* @param handle A Camera_Handle
*
* @param buffer A pointer to a WO (write-only) buffer into which the
* captured frame is placed
*
* @param bufferlen Length (in bytes) of the capture buffer
*
* @param frameLen Pointer to return number of bytes captured.
*
* @return CAMERA_STATUS_SUCCESS on successful capture, CAMERA_STATUS_ERROR if
* if otherwise.
*
* @sa Camera_open
*/
extern int_fast16_t Camera_capture(Camera_Handle handle, void *buffer,
size_t bufferlen, size_t *frameLen);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_Camera__include */

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/*
* Copyright (c) 2016-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/Capture.h>
#include <ti/drivers/dpl/HwiP.h>
extern const Capture_Config Capture_config[];
extern const uint_least8_t Capture_count;
/* Default Parameters */
static const Capture_Params defaultParams = {
.callbackFxn = NULL,
.mode = Capture_RISING_EDGE,
.periodUnit = Capture_PERIOD_COUNTS
};
static bool isInitialized = false;
/*
* ======== Capture_close ========
*/
void Capture_close(Capture_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== Capture_control ========
*/
int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd,
void *arg)
{
return (handle->fxnTablePtr->controlFxn(handle, cmd, arg));
}
/*
* ======== Capture_init ========
*/
void Capture_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < Capture_count; i++) {
Capture_config[i].fxnTablePtr->initFxn((Capture_Handle) &(Capture_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== Capture_open ========
*/
Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params)
{
Capture_Handle handle = NULL;
/* Verify driver index and state */
if (isInitialized && (index < Capture_count)) {
/* If parameters are NULL use defaults */
if (params == NULL) {
params = (Capture_Params *) &defaultParams;
}
/* Get handle for this driver instance */
handle = (Capture_Handle) &(Capture_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== Capture_Params_init ========
*/
void Capture_Params_init(Capture_Params *params)
{
*params = defaultParams;
}
/*
* ======== Capture_start ========
*/
int32_t Capture_start(Capture_Handle handle)
{
return (handle->fxnTablePtr->startFxn(handle));
}
/*
* ======== Capture_stop ========
*/
void Capture_stop(Capture_Handle handle)
{
handle->fxnTablePtr->stopFxn(handle);
}

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/*
* Copyright (c) 2016-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file Capture.h
* @brief Capture driver interface
*
* The capture header file should be included in an application as follows:
* @code
* #include <ti/drivers/Capture.h>
* @endcode
*
* # Overview #
* The capture driver serves as the main interface for a typical RTOS
* application. Its purpose is to redirect the capture APIs to device specific
* implementations which are specified using a pointer to a #Capture_FxnTable.
* The device specific implementations are responsible for creating all the
* RTOS specific primitives to allow for thead-safe operation. The capture
* driver utilizes the general purpose timer hardware.
*
* The capture driver internally handles the general purpose timer resource
* allocation. For each capture driver instance, Capture_open() occupies the
* specified timer, and Capture_close() releases the occupied timer resource.
*
* # Usage#
* The capture driver is used to detect and time edge triggered events on a
* GPIO pin. The following example code opens a capture instance in falling
* edge mode. The interval returned in the callback function is in
* microseconds.
*
* @code
* Capture_Handle handle;
* Capture_Params params;
*
* Capture_Params_init(&params);
* params.mode = Capture_FALLING_EDGE;
* params.callbackFxn = someCaptureCallbackFunction;
* params.periodUnit = Capture_PERIOD_US;
*
* handle = Capture_open(someCapture_configIndexValue, &params);
*
* if (handle == NULL) {
* //Capture_open() failed
* while(1);
* }
*
* status = Capture_start(handle);
*
* if (status == Capture_STATUS_ERROR) {
* //Capture_start() failed
* while(1);
* }
*
* sleep(10000);
*
* Capture_stop(handle);
* @endcode
* ### Capture Driver Configuration #
*
* In order to use the capture APIs, the application is required to provide
* device specific capture configuration in the Board.c file. The capture
* driver interface defines a configuration data structure:
*
* @code
* typedef struct Capture_Config_ {
* Capture_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } Capture_Config;
* @endcode
*
* The application must declare an array of Capture_Config elements, named
* Capture_config[]. Each element of Capture_config[] is populated with
* pointers to a device specific capture driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the timer peripheral's base address, interrupt
* number and interrupt priority. Each element in Capture_config[] corresponds
* to a capture instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the peripheral designation.
*
* You will need to check the device specific capture driver implementation's
* header file for example configuration.
*
* ### Initializing the Capture Driver #
*
* Capture_init() must be called before any other capture APIs. This function
* calls the device implementation's capture initialization function, for each
* element of Capture_config[].
*
* ### Modes of Operation #
*
* The capture driver supports four modes of operation which may be specified
* in the Capture_Params.
*
* #Capture_RISING_EDGE will capture rising edge triggers. After
* Capture_start() is called, the callback function specified in
* Capture_Params will be called after each rising edge is detected on the
* GPIO pin. This behavior will continue until Capture_stop() is called.
*
* #Capture_FALLING_EDGE will capture falling edge triggers. After
* Capture_start() is called, the callback function specified in
* Capture_Params will be called after each falling edge is detected on the
* GPIO pin. This behavior will continue until Capture_stop() is called.
*
* #Capture_ANY_EDGE will capture both rising and falling edge triggers. After
* Capture_start() is called, the callback function specified in
* Capture_Params will be called after each rising or falling edge is detected
* on the GPIO pin. This behavior will continue until Capture_stop() is
* called.
*
* # Implementation #
*
* The capture driver interface module is joined (at link time) to an
* array of Capture_Config data structures named *Capture_config*.
* Capture_config is implemented in the application with each entry being an
* instance of a capture peripheral. Each entry in *Capture_config* contains a:
* - (Capture_FxnTable *) to a set of functions that implement a capture
* peripheral
* - (void *) data object that is associated with the Capture_FxnTable
* - (void *) hardware attributes that are associated with the Capture_FxnTable
*
* The capture APIs are redirected to the device specific implementations
* using the Capture_FxnTable pointer of the Capture_config entry.
* In order to use device specific functions of the capture driver directly,
* link in the correct driver library for your device and include the
* device specific capture driver header file (which in turn includes
* Capture.h). For example, for the MSP432 family of devices, you would
* include the following header file:
*
* @code
* #include <ti/drivers/capture/CaptureMSP432.h>
* @endcode
*
*******************************************************************************
*/
#ifndef ti_drivers_Capture__include
#define ti_drivers_Capture__include
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdint.h>
/*!
* Common Capture_control command code reservation offset.
* Capture driver implementations should offset command codes with
* Capture_CMD_RESERVED growing positively.
*
* Example implementation specific command codes:
* @code
* #define CaptureXYZ_CMD_COMMAND0 Capture_CMD_RESERVED + 0
* #define CaptureXYZ_CMD_COMMAND1 Capture_CMD_RESERVED + 1
* @endcode
*/
#define Capture_CMD_RESERVED (32)
/*!
* Common Capture_control status code reservation offset.
* Capture driver implementations should offset status codes with
* Capture_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define CaptureXYZ_STATUS_ERROR0 Capture_STATUS_RESERVED - 0
* #define CaptureXYZ_STATUS_ERROR1 Capture_STATUS_RESERVED - 1
* @endcode
*/
#define Capture_STATUS_RESERVED (-32)
/*!
* @brief Successful status code.
*/
#define Capture_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code.
*/
#define Capture_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by Capture_control() for undefined
* command codes.
*
* Capture_control() returns Capture_STATUS_UNDEFINEDCMD if the control code is
* not recognized by the driver implementation.
*/
#define Capture_STATUS_UNDEFINEDCMD (-2)
/*!
* @brief A handle that is returned from a Capture_open() call.
*/
typedef struct Capture_Config_ *Capture_Handle;
/*!
* @brief Capture mode settings
*
* This enum defines the capture modes that may be specified in
* #Capture_Params.
*/
typedef enum Capture_Mode_ {
Capture_RISING_EDGE, /*!< Capture is triggered on rising edges. */
Capture_FALLING_EDGE, /*!< Capture is triggered on falling edges. */
Capture_ANY_EDGE /*!< Capture is triggered on both rising and
falling edges. */
} Capture_Mode;
/*!
* @brief Capture period unit enum
*
* This enum defines the units that may be specified for the period
* in #Capture_Params.
*/
typedef enum Capture_PeriodUnits_ {
Capture_PERIOD_US, /*!< Period specified in micro seconds. */
Capture_PERIOD_HZ, /*!< Period specified in hertz; interrupts per
second. */
Capture_PERIOD_COUNTS /*!< Period specified in timer ticks. Varies
by board. */
} Capture_PeriodUnits;
/*!
* @brief Capture callback function
*
* User definable callback function prototype. The capture driver will call
* the defined function and pass in the capture driver's handle and the
* pointer to the user-specified the argument.
*
* @param handle Capture_Handle
*
* @param interval Interval of two triggering edges in
* #Capture_PeriodUnits
*/
typedef void (*Capture_CallBackFxn)(Capture_Handle handle, uint32_t interval);
/*!
* @brief Capture Parameters
*
* Capture parameters are used by the Capture_open() call. Default values for
* these parameters are set using Capture_Params_init().
*
*/
typedef struct Capture_Params_ {
/*!< Mode to be used by the timer driver. */
Capture_Mode mode;
/*!< Callback function called when a trigger event occurs. */
Capture_CallBackFxn callbackFxn;
/*!< Units used to specify the interval. */
Capture_PeriodUnits periodUnit;
} Capture_Params;
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_close().
*/
typedef void (*Capture_CloseFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_control().
*/
typedef int_fast16_t (*Capture_ControlFxn)(Capture_Handle handle,
uint_fast16_t cmd, void *arg);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_init().
*/
typedef void (*Capture_InitFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_open().
*/
typedef Capture_Handle (*Capture_OpenFxn)(Capture_Handle handle,
Capture_Params *params);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_start().
*/
typedef int32_t (*Capture_StartFxn)(Capture_Handle handle);
/*!
* @brief A function pointer to a driver specific implementation of
* Capture_stop().
*/
typedef void (*Capture_StopFxn)(Capture_Handle handle);
/*!
* @brief The definition of a capture function table that contains the
* required set of functions to control a specific capture driver
* implementation.
*/
typedef struct Capture_FxnTable_ {
/*!< Function to close the specified peripheral. */
Capture_CloseFxn closeFxn;
/*!< Function to implementation specific control function. */
Capture_ControlFxn controlFxn;
/*!< Function to initialize the given data object. */
Capture_InitFxn initFxn;
/*!< Function to open the specified peripheral. */
Capture_OpenFxn openFxn;
/*!< Function to start the specified peripheral. */
Capture_StartFxn startFxn;
/*!< Function to stop the specified peripheral. */
Capture_StopFxn stopFxn;
} Capture_FxnTable;
/*!
* @brief Capture Global configuration
*
* The Capture_Config structure contains a set of pointers used to
* characterize the capture driver implementation.
*
* This structure needs to be defined before calling Capture_init() and it
* must not be changed thereafter.
*
* @sa Capture_init()
*/
typedef struct Capture_Config_ {
/*! Pointer to a table of driver-specific implementations of capture
APIs. */
Capture_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object. */
void *object;
/*! Pointer to a driver specific hardware attributes structure. */
void const *hwAttrs;
} Capture_Config;
/*!
* @brief Function to close a capture driver instance. The corresponding
* timer peripheral to Capture_handle becomes an available resource.
*
* @pre Capture_open() has been called.
*
* @param handle A Capture_Handle returned from Capture_open().
*
* @sa Capture_open()
*/
extern void Capture_close(Capture_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* Capture_Handle.
*
* @pre Capture_open() has been called.
*
* @param handle A Capture_Handle returned from Capture_open().
*
* @param cmd A command value defined by the driver specific
* implementation.
*
* @param arg A pointer to an optional R/W (read/write) argument that
* is accompanied with cmd.
*
* @return A Capture_Status describing an error or success state. Negative values
* indicate an error occurred.
*
* @sa Capture_open()
*/
extern int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd,
void *arg);
/*!
* @brief Function to initialize the capture driver. This function will go
* through all available hardware resources and mark them as
* "available".
*
* @pre The Capture_config structure must exist and be persistent before
* this function can be called. This function must also be called
* before any other capture driver APIs.
*
* @sa Capture_open()
*/
extern void Capture_init(void);
/*!
* @brief Function to open a given capture instance specified by the
* index argument. The Capture_Params specifies which mode the capture
* instance will operate. This function takes care of capture resource
* allocation. If the particular timer hardware is available to use,
* the capture driver acquires it and returns a Capture_Handle.
*
* @pre Capture_init() has been called.
*
* @param index Logical instance number for the capture indexed into
* the Capture_config table.
*
* @param params Pointer to a parameter block. Cannot be NULL.
*
* @return A Capture_Handle on success, or NULL if the timer peripheral is
* already in use.
*
* @sa Capture_init()
* @sa Capture_close()
*/
extern Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params);
/*!
* @brief Function to initialize the Capture_Params struct to its defaults.
*
* @param params An pointer to Capture_Params structure for
* initialization.
*
* Defaults values are:
* callbackFxn = NULL
* mode = Capture_RISING_EDGE
* periodUnit = Capture_PERIOD_COUNTS
*/
extern void Capture_Params_init(Capture_Params *params);
/*!
* @brief Function to start the capture instance.
*
* @pre Capture_open() has been called.
*
* @param handle A Capture_Handle returned from Capture_open().
*
* @return Capture_STATUS_SUCCESS or Capture_STATUS_ERROR.
*
* @sa Capture_stop().
*
*/
extern int32_t Capture_start(Capture_Handle handle);
/*!
* @brief Function to stop a capture instance. If the capture instance is
* already stopped, this function has no effect.
*
* @pre Capture_open() has been called.
*
* @param handle A Capture_Handle returned from Capture_open().
*
* @sa Capture_start()
*/
extern void Capture_stop(Capture_Handle handle);
/* The following are included for backwards compatibility. These should not be
* used by the application.
*/
#define CAPTURE_CMD_RESERVED Capture_CMD_RESERVED
#define CAPTURE_STATUS_RESERVED Capture_STATUS_RESERVED
#define CAPTURE_STATUS_SUCCESS Capture_STATUS_SUCCESS
#define CAPTURE_STATUS_ERROR Capture_STATUS_ERROR
#define CAPTURE_STATUS_UNDEFINEDCMD Capture_STATUS_UNDEFINEDCMD
#define CAPTURE_MODE_RISING_RISING Capture_RISING_EDGE
#define CAPTURE_MODE_FALLING_FALLING Capture_FALLING_EDGE
#define CAPTURE_MODE_ANY_EDGE Capture_ANY_EDGE
#define CAPTURE_PERIOD_US Capture_PERIOD_US
#define CAPTURE_PERIOD_HZ Capture_PERIOD_HZ
#define CAPTURE_PERIOD_COUNTS Capture_PERIOD_COUNTS
#define Capture_Period_Unit Capture_PeriodUnits
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_Capture__include */

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/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== ECDH.c ========
*
* This file contains default values for the ECDH_Params struct
*
*/
#include <stdlib.h>
#include <ti/drivers/dpl/SemaphoreP.h>
#include <ti/drivers/ECDH.h>
const ECDH_Params ECDH_defaultParams = {
.returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING,
.callbackFxn = NULL,
.timeout = SemaphoreP_WAIT_FOREVER,
.custom = NULL,
};

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/*
* Copyright (c) 2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!
* @file ECDH.h
*
* @brief TI Driver for Elliptic Curve Diffie-Hellman key agreement scheme.
*
*
* @warning This is a beta API. It may change in future releases.
*
* # Overview #
*
* Elliptic Curve Diffie-Hellman (ECDH) is a key agreement scheme between
* two parties based on the Diffie-Hellman key exchange protocol.
*
* It provides a means of generating a shared secret and derived symmetric key
* between the two parties over an insecure channel.
*
* It does not provide authentication. As such, it does not guarantee that the
* party you are exchanging keys with is truly the party you wish to establish a
* secured channel with.
*
* The two parties each generate a private key and a public key. The private key
* is a random integer in the interval [1, n - 1], where n is the order of a
* previously agreed upon curve. The public key is generated
* by multiplying the private key by the generator point of a previously agreed
* upon elliptic curve such as NISTP256 or Curve 25519. The public key is itself
* a point upon the elliptic curve. Each public key is then transmitted to the
* other party over a potentially insecure channel. The other party's public key
* is then multiplied with the private key, generating a shared secret. This
* shared secret is also a point on the curve. However, the entropy in the secret
* is not spread evenly throughout the shared secret. In order to generate one or more
* shared symmetric keys, the shared secret must be run through a key derivation
* function (KDF) that was previously agreed upon. The key derivation function
* can take many forms, from simply hashing the X coordinate of the shared secret
* with SHA2 and truncating the result to generating multiple symmetric keys with
* HKDF, an HMAC based KDF.
*
* # Usage #
*
* ## Before starting an ECDH operation #
*
* Before starting a CCM operation, the application must do the following:
* - Call ECDH_init() to initialize the driver
* - Call ECDH_Params_init() to initialize the ECDH_Params to default values.
* - Modify the ECDH_Params as desired
* - Call ECDH_open() to open an instance of the driver
*
* ## Generating your public-private key pair #
* To generate a public-private key pair for an agreed upon curve, the application
* must do the following:
* - Generate the keying material for the private key. This keying material must
* be an integer in the interval [1, n - 1], where n is the order of the curve.
* It should be stored in an array with the least significant byte of the integer
* hex representation stored in the lowest address of the array (little-endian).
* The array should be the same length as the curve parameters of the curve used.
* The driver can be configured to validate public and private keys against the
* provided curve.
* - Initialize the private key CryptoKey. CryptoKeys are opaque datastructures and representations
* of keying material and its storage. Depending on how the keying material
* is stored (RAM or flash, key store, key blob), the CryptoKey must be
* initialized differently. The ECDH API can handle all types of CryptoKey.
* However, not all device-specific implementions support all types of CryptoKey.
* Devices without a key store will not support CryptoKeys with keying material
* stored in a key store for example.
* All devices support plaintext CryptoKeys.
* - Initialize a blank CryptoKey for the public key. The CryptoKey will keep track
* of where the keying material for the public key should be copied and how
* long it is. It should have twice the length of the private key.
* - Call ECDH_generatePublicKey(). The generated keying material will be copied
* according the the CryptoKey passed in as the public key parameter. The CryptoKey
* will no longer be considered 'blank' after the operation.
*
* ## Calculating a shared secret #
* After trading public keys with the other party, the application should do the following
* to calculate the shared secret:
* - Initialize a CryptoKey as public key with the keying material received from the other
* party.
* - Initialize a blank CryptoKey with the same size as the previously initialized
* public key.
* - Call ECDH_computeSharedSecret(). The shared secret will be copied to a location
* according to the shared secret CryptoKey passed to the function call.
*
*
* ## Creating one or more symmetric keys from the shared secret #
* After calculating the shared secret between the application and the other party,
* the entropy in the shared secret must be evened out and stretched as needed. The API
* allows for any number of keys to be derived from the shared secret using an application-provided
* key-derivation function. There are uncountable methods and algorithms to stretch an original
* seed entropy (the share secret) to generate symmetric keys.
* - Initialize n blank CryptoKeys in an array. These CryptoKeys is where the generated
* king material will be copied to. The keying material they represent does
* not need to be a contiguous range or even of the same CryptoKey type. The array may
* contain Plaintext, key blob, or key store CryptoKeys. It may contain different types
* of CryptoKeys.
* While the API allows for full flexibility in key material location and length, not all
* key derivation functions support the full scope of flexibility. Check the KDF's documentation
* before using it.
* - Call ECDH_calculateSharedEntropy(). The generated keying material will be copied to a
* location according to the CryptoKeys passed to the function.
*
* ## After a key exchange #
* After the ECDH key exchange completes, the application should either start another operation
* or close the driver by calling ECDH_close()
*
* ## General usage #
* The API expects elliptic curves in short Weierstrass form as defined in
* ti/drivers/types/ECCParams.h. Several commonly used curves are provided.
*
* Public keys and shared secrets are points on an elliptic curve. These points can
* be expressed in several ways. The most common one is in affine coordinates as an
* X,Y pair. The Y value can be omitted when using point compression and doing
* the calculations in the Montgomery domain with X,Z coordinates.
* This API only uses points expressed in affine coordinates. The point is stored as a
* concatenated array of X followed by Y.
*
* ## ECDH Driver Configuration #
*
* In order to use the ECDH APIs, the application is required
* to provide device-specific ECDH configuration in the Board.c file.
* The ECDH driver interface defines a configuration data structure:
*
* @code
* typedef struct ECDH_Config_ {
* void *object;
* void const *hwAttrs;
* } ECDH_Config;
* @endcode
*
* The application must declare an array of ECDH_Config elements, named
* ECDH_config[]. Each element of ECDH_config[] must be populated with
* pointers to a device specific ECDH driver implementation's
* driver object, hardware attributes. The hardware attributes
* define properties such as the ECDH peripheral's base address.
* Each element in ECDH_config[] corresponds to
* an ECDH instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as ECDH0 or ECDH1). For example, it is
* possible to use ECDH_config[0] for ECDH1. Multiple drivers and driver
* instances may all access the same underlying hardware. This is transparent
* to the application. Mutual exclusion is performed automatically by the
* drivers as necessary.
*
* Because the ECDH configuration is very device dependent, you will need to
* check the doxygen for the device specific ECDH implementation. There you
* will find a description of the ECDH hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the ECDH
* configuration.
*
* ## ECDH Parameters #
*
* The #ECDH_Params structure is passed to the ECDH_open() call. If NULL
* is passed for the parameters, ECDH_open() uses default parameters.
* An #ECDH_Params structure is initialized with default values by passing
* it to ECDH_Params_init().
* Some of the ECDH parameters are described below. To see brief descriptions
* of all the parameters, see #ECDH_Params.
*
* ## ECDH Return Behavior
* The ECDH driver supports three return behaviors when processing data: blocking, polling, and
* callback. The ECDH driver defaults to blocking mode, if the application does not set it.
* Once an ECDH driver is opened, the only way to change the return behavior
* is to close and re-open the ECDH instance with the new return behavior.
*
* In blocking mode, a task's code execution is blocked until an ECDH
* operation has completed. This ensures that only one ECDH operation
* operates at a given time. Other tasks requesting ECDH operations while
* a operation is currently taking place are also placed into a blocked
* state. ECDH operations are executed in the order in which they were
* received. In blocking mode, you cannot perform ECDH operations
* in the context of a software or hardware ISR.
*
* In callback mode, an ECDH operation functions asynchronously, which
* means that it does not block code execution. After an ECDH operation
* has been completed, the ECDH driver calls a user-provided hook function.
* Callback mode is supported in the task, SWI, and HWI execution context,
* However, if an ECDH operation is requested while a operation is taking place,
* the call returns an error code.
*
* In polling mode, an ECDH operation behaves the almost the same way as
* in blocking mode. Instead of pending on a semaphore and letting other
* scheduled tasks run, the application task, SWI, or HWI continuously polls
* a flag until the operation completes. If an ECDH operation is
* requested while a operation is taking place, the call returns an error code.
* When starting an ECDH operation in polling mode from HWI or SWI context,
* the ECDH HWI and SWI must be configured to have a higher priority to pre-empt
* the polling context.
*
* # Examples #
*
* ## ECDH exchange with plaintext CryptoKeys #
*
* @code
*
* #include <ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h>
* #include <ti/drivers/ECDH.h>
*
* ...
*
* // Our private key is 0x0000000000000000000000000000000000000000000000000000000000000001
* // In practice, this value should come from a TRNG, PRNG, PUF, or device-specific pre-seeded key
* uint8_t myPrivateKeyingMaterial[32] = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
* 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
* uint8_t myPublicKeyingMaterial[64] = {0};
* uint8_t theirPublicKeyingMaterial[64] = {0};
* uint8_t sharedSecretKeyingMaterial[64] = {0};
* uint8_t symmetricKeyingMaterial[16] = {0};
*
* CryptoKey myPrivateKey;
* CryptoKey myPublicKey;
* CryptoKey theirPublicKey;
* CryptoKey sharedSecret;
* CryptoKey symmetricKey;
*
* ECDH_Handle ecdhHandle;
*
* int_fast16_t operationResult;
*
* // Since we are using default ECDH_Params, we just pass in NULL for that parameter.
* ecdhHandle = ECDH_open(0, NULL);
*
* if (!ecdhHandle) {
* // Handle error
* }
*
* // Initialize myPrivateKey and myPublicKey
* CryptoKeyPlaintext_initKey(&myPrivateKey, myPrivateKeyingMaterial, sizeof(myPrivateKeyingMaterial));
* CryptoKeyPlaintext_initBlankKey(&myPublicKey, myPublicKeyingMaterial, sizeof(myPublicKeyingMaterial));
*
* // Generate the keying material for myPublicKey and store it in myPublicKeyingMaterial
* operationResult = ECDH_generatePublicKey(ecdhHandle, &ECC_NISTP256, &myPrivateKey, &myPublicKey);
*
* if (operationResult != ECDH_STATUS_SUCCESS) {
* // Handle error
* }
*
* // Now send the content of myPublicKeyingMaterial to theother party,
* // receive their public key, and copy their public keying material to theirPublicKeyingMaterial
*
* // Initialise their public CryptoKey and the shared secret CryptoKey
* CryptoKeyPlaintext_initKey(&theirPublicKey, theirPublicKeyingMaterial, sizeof(theirPublicKeyingMaterial));
* CryptoKeyPlaintext_initBlankKey(&sharedSecret, sharedSecretKeyingMaterial, sizeof(sharedSecretKeyingMaterial));
*
* // Compute the shared secret and copy it to sharedSecretKeyingMaterial
* // The ECC_NISTP256 struct is provided in ti/drivers/types/EccPArams.h and the corresponding device-specific implementation
* operationResult = ECDH_computeSharedSecret(ecdhHandle, &ECC_NISTP256, &myPrivateKey, &theirPublicKey, &sharedSecret);
*
* if (operationResult != ECDH_STATUS_SUCCESS) {
* // Handle error
* }
*
* CryptoKeyPlaintext_initBlankKey(&symmetricKey, symmetricKeyingMaterial, sizeof(symmetricKeyingMaterial));
*
* // Set up a KDF such as HKDF and open the requisite cryptographic primitive driver to implement it
* // HKDF and SHA2 were chosen as an example and may not be available directly
* // Since we only have one symmetric CryptoKey we wish to generate, we can pass it directly to the function
* operationResult = ECDH_calculateSharedEntropy(ecdhHandle, &sharedSecret, KDF_HKDF, sha2Handle, &symmetricKey, 1);
*
* if (operationResult != ECDH_STATUS_SUCCESS) {
* // Handle error
* }
*
* // At this point, you and the other party have both created the content within symmetricKeyingMaterial without
* // someone else listening to your communication channel being able to do so
*
* @endcode
*
*
*/
#ifndef ti_drivers_ECDH__include
#define ti_drivers_ECDH__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <ti/drivers/cryptoutils/cryptokey/CryptoKey.h>
#include <ti/drivers/cryptoutils/ecc/ECCParams.h>
/**
* @defgroup ECDH_CONTROL ECDH_control command and status codes
* These ECC macros are reservations for ECC.h
* @{
*/
/*!
* Common ECDH_control command code reservation offset.
* ECC driver implementations should offset command codes with ECDH_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define ECCXYZ_CMD_COMMAND0 ECDH_CMD_RESERVED + 0
* #define ECCXYZ_CMD_COMMAND1 ECDH_CMD_RESERVED + 1
* @endcode
*/
#define ECDH_CMD_RESERVED (32)
/*!
* Common ECDH_control status code reservation offset.
* ECC driver implementations should offset status codes with
* ECDH_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define ECCXYZ_STATUS_ERROR0 ECDH_STATUS_RESERVED - 0
* #define ECCXYZ_STATUS_ERROR1 ECDH_STATUS_RESERVED - 1
* #define ECCXYZ_STATUS_ERROR2 ECDH_STATUS_RESERVED - 2
* @endcode
*/
#define ECDH_STATUS_RESERVED (-32)
/**
* @defgroup ECDH_STATUS Status Codes
* ECDH_STATUS_* macros are general status codes returned by ECC functions
* @{
* @ingroup ECDH_CONTROL
*/
/*!
* @brief Successful status code.
*
* Function return ECDH_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define ECDH_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code.
*
* Functions return ECDH_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define ECDH_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by ECDH_control() for undefined
* command codes.
*
* ECDH_control() returns ECDH_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define ECDH_STATUS_UNDEFINEDCMD (-2)
/*!
* @brief An error status code returned if the hardware or software resource
* is currently unavailable.
*
* ECC driver implementations may have hardware or software limitations on how
* many clients can simultaneously perform operations. This status code is returned
* if the mutual exclusion mechanism signals that an operation cannot currently be performed.
*/
#define ECDH_STATUS_RESOURCE_UNAVAILABLE (-3)
/*!
* @brief The result of the operation is the point at infinity.
*
* The operation yielded the point at infinity on this curve. This point is
* not permitted for further use in ECC operations.
*/
#define ECDH_STATUS_RESULT_POINT_AT_INFINITY (-4)
/*!
* @brief The private key passed in is larger than the order of the curve.
*
* Private keys must be integers in the interval [1, n - 1], where n is the
* order of the curve.
*/
#define ECDH_STATUS_RESULT_PRIVATE_KEY_LARGER_THAN_ORDER (-5)
/*!
* @brief The public key of the other party does not lie upon the curve.
*
* The public key received from the other party does not lie upon the agreed upon
* curve.
*/
#define ECDH_STATUS_RESULT_PUBLIC_KEY_NOT_ON_CURVE (-6)
/** @}*/
/**
* @defgroup ECDH_CMD Command Codes
* ECDH_CMD_* macros are general command codes for ECDH_control(). Not all ECC
* driver implementations support these command codes.
* @{
* @ingroup ECDH_CONTROL
*/
/* Add ECDH_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an ECDH_open() call.
*/
typedef struct ECDH_Config_ *ECDH_Handle;
/*!
* @brief The definition of a callback function used by the ECC driver
* when used in ::ECDH_RETURN_BEHAVIOR_CALLBACK
*
* @param handle Handle of the client that started the ECC operation.
*
* @param operationStatus The result of the ECC operation. May contain an error code
* if the result is the point at infinity for example.
*/
typedef void (*ECDH_CallbackFxn) (ECDH_Handle handle, int_fast16_t operationStatus);
/*!
* @brief The way in which ECC function calls return after performing an
* encryption + authentication or decryption + verification operation.
*
* Not all ECC operations exhibit the specified return behavor. Functions that do not
* require significant computation and cannot offload that computation to a background thread
* behave like regular functions. Which functions exhibit the specfied return behavior is not
* implementation dependent. Specifically, a software-backed implementation run on the same
* CPU as the application will emulate the return behavior while not actually offloading
* the computation to the background thread.
*
* ECC functions exhibiting the specified return behavior have restrictions on the
* context from which they may be called.
*
* | | Task | Hwi | Swi |
* |--------------------------------|-------|-------|-------|
* |ECDH_RETURN_BEHAVIOR_CALLBACK | X | X | X |
* |ECDH_RETURN_BEHAVIOR_BLOCKING | X | | |
* |ECDH_RETURN_BEHAVIOR_POLLING | X | X | X |
*
*/
typedef enum ECDH_ReturnBehavior_ {
ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the
* ECC operation goes on in the background. The registered
* callback function is called after the operation completes.
* The context the callback function is called (task, HWI, SWI)
* is implementation-dependent.
*/
ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes
* on in the background. ECC operation results are available
* after the function returns.
*/
ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC
* operation goes on in the background. ECC operation results
* are available after the function returns.
*/
} ECDH_ReturnBehavior;
/*!
* @brief ECC Parameters
*
* ECC Parameters are used to with the ECDH_open() call. Default values for
* these parameters are set using ECDH_Params_init().
*
* @sa ECDH_Params_init()
*/
typedef struct ECDH_Params_ {
bool doNotValidateKeys; /*!< Whether or not to validate public and private keys in operations. */
ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */
ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */
uint32_t timeout;
void *custom; /*!< Custom argument used by driver
* implementation
*/
} ECDH_Params;
/*!
* @brief ECC Global configuration
*
* The ECDH_Config structure contains a set of pointers used to characterize
* the ECC driver implementation.
*
* This structure needs to be defined before calling ECDH_init() and it must
* not be changed thereafter.
*
* @sa ECDH_init()
*/
typedef struct ECDH_Config_ {
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} ECDH_Config;
/*!
* @brief Function that implements a key derivation function (KDF)
*
* Key derivation functions take a string of random entropy as their input and generate
* a deterministic pseudo-random bit stream of arbitrary length. Specialised KDFs may
* produce outputs of fixed length or with maximum lengths.
*
* @param [in] driverHandle Handle of the of the driver used to execute the crypto
* primitive underlying the KDF. This primitive could be a
* cryptographic hash or a block cipher.
*
* @param [in] seedEntropy The entropy used to seed the KDF. Reusing the same seed
* will yield the same pseudo-random bit stream.
*
* @param [in] seedEntropyLength Length of the seed entropy.
*
* @param [out] derivedKeys The CryptoKeys seeded with deterministic pseudo-random output of the KDF.
*
* @param [in] derivedKeysCount The number of keys to seed.
*/
typedef int_fast16_t (*ECDH_KDFFxn) (void *driverHandle, const uint8_t *seedEntropy, size_t seedEntropyLength, CryptoKey derivedKeys[], uint32_t derivedKeysCount);
/*!
* @brief Default ECDH_Params structure
*
* @sa ECDH_Params_init()
*/
extern const ECDH_Params ECDH_defaultParams;
/*!
* @brief This function initializes the ECC module.
*
* @pre The ECDH_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other ECC driver APIs. This function call does not modify any
* peripheral registers.
*/
void ECDH_init(void);
/*!
* @brief Function to initialize the ECDH_Params struct to its defaults
*
* @param params An pointer to ECDH_Params structure for
* initialization
*
* Defaults values are:
* returnBehavior = ECDH_RETURN_BEHAVIOR_BLOCKING
* callbackFxn = NULL
* timeout = SemaphoreP_WAIT_FOREVER
* custom = NULL
*/
void ECDH_Params_init(ECDH_Params *params);
/*!
* @brief This function opens a given ECC peripheral.
*
* @pre ECC controller has been initialized using ECDH_init()
*
* @param index Logical peripheral number for the ECC indexed into
* the ECDH_config table
*
* @param params Pointer to an parameter block, if NULL it will use
* default values.
*
* @return A ECDH_Handle on success or a NULL on an error or if it has been
* opened already.
*
* @sa ECDH_init()
* @sa ECDH_close()
*/
ECDH_Handle ECDH_open(uint_least8_t index, ECDH_Params *params);
/*!
* @brief Function to close a ECC peripheral specified by the ECC handle
*
* @pre ECDH_open() has to be called first.
*
* @param handle A ECC handle returned from ECDH_open()
*
* @sa ECDH_open()
*/
void ECDH_close(ECDH_Handle handle);
/*!
* @brief Function performs implementation specific features on a given
* ECDH_Handle.
*
* Commands for ECDH_control can originate from ECC.h or from implementation
* specific ECC*.h (_ECCCC26XX.h_, _EECCSP432.h_, etc.. ) files.
* While commands from ECC.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific ECC*.h files add
* unique driver capabilities but are not API portable across all ECC driver
* implementations.
*
* Commands supported by ECC.h follow an ECDH_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by ECC*.h follow an ECC*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref ECDH_CMD "ECDH_control command codes" for command codes.
*
* See @ref ECDH_STATUS "ECDH_control return status codes" for status codes.
*
* @pre ECDH_open() has to be called first.
*
* @param handle A ECC handle returned from ECDH_open()
*
* @param cmd ECC.h or ECC*.h commands.
*
* @param args An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa ECDH_open()
*/
int_fast16_t ECDH_control(ECDH_Handle handle, uint32_t cmd, void *args);
/*!
* @brief Generates a public key for use in key agreement.
*
* ECDH_generateKey() can be used for generating ephemeral keys.
*
* @param handle A ECC handle returned from ECDH_open()
* @param eccParams A pointer to the elliptic curve parameters for myPrivateKey
* @param myPrivateKey A pointer to the private ECC key from which the new public key will be generated. (maybe your static key)
* @param myPublicKey A pointer to a public ECC key which has been initialized blank. Newly generated
* key will be placed in this location.
*
* \post ECDH_computeSharedSecret()
*
*/
int_fast16_t ECDH_generatePublicKey(ECDH_Handle handle, const ECCParams_CurveParams *eccParams, const CryptoKey *myPrivateKey, CryptoKey *myPublicKey);
/*!
* @brief Computes a shared secret
*
* This secret can be used to generate shared keys for encryption and authentication.
*
* @param handle A ECC handle returned from ECDH_open()
* @param eccParams A pointer to the elliptic curve parameters for myPrivateKey (if ECDH_generateKey() was used, this should be the same private key)
* @param myPrivateKey A pointer to the private ECC key which will be used in to compute the shared secret
* @param theirPublicKey A pointer to the public key of the party with whom the shared secret will be generated
* @param sharedSecret A pointer to a CryptoKey which has been initialized blank. The shared secret will be placed here.
*
* \post ECDH_calculateSharedEntropy()
*/
int_fast16_t ECDH_computeSharedSecret(ECDH_Handle handle, const ECCParams_CurveParams *eccParams, const CryptoKey *myPrivateKey, const CryptoKey *theirPublicKey, CryptoKey *sharedSecret);
/*!
* @brief Calculates key material
*
* \pre ECDH_computeSharedSecret()
*
* @param handle A ECC handle returned from ECDH_open()
*
* @param sharedSecret The shared secret produced by ECDH_calculateSharedEntropy()
*
* @param kdf A pointer to the key derivation function to be used
*
* @param kdfPrimitiveDriverHandle A pointer to the handle of a driver of a cryptographic primitive used to implement the KDF
*
* @param derivedKeys A an array of CryptoKeys to seed with calculated entropy
*
* @param derivedKeysCount The number of CryptoKeys to seed with calculated entropy
*
*/
int_fast16_t ECDH_calculateSharedEntropy(ECDH_Handle handle, const CryptoKey *sharedSecret, const ECDH_KDFFxn kdf, void *kdfPrimitiveDriverHandle, CryptoKey derivedKeys[], uint32_t derivedKeysCount);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_ECDH__include */

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/*
* Copyright (c) 2014, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/EMAC.h>
/* Externs */
extern const EMAC_Config EMAC_config[];
/* Used to check status for initialization */
static int EMAC_count = -1;
/*
* ======== EMAC_init ========
*/
void EMAC_init(void)
{
/*
* Allow only the first initialization to do anything.
* The next ones are nops.
*/
if (EMAC_count >= 0) {
return;
}
/* Call each driver's init function */
for (EMAC_count = 0; EMAC_config[EMAC_count].fxnTablePtr != NULL;
EMAC_count++) {
EMAC_config[EMAC_count].fxnTablePtr->emacInit(EMAC_count);
}
return;
}
/*
* ======== EMAC_isLinkUp ========
*/
bool EMAC_isLinkUp(unsigned int index)
{
return (EMAC_config[index].fxnTablePtr->emacIsLinkUp(index));
}

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file EMAC.h
*
* @brief EMAC driver interface
*
* The EMAC header file should be included in an application as follows:
* @code
* #include <ti/drivers/EMAC.h>
* @endcode
*
* # Implementation #
*
* The EMAC driver interface module is joined (at link time) to a
* NULL-terminated array of EMAC_Config data structures named *EMAC_config*.
* *EMAC_config* is implemented in the application with each entry being an
* instance of a EMAC peripheral. Each entry in *EMAC_config* contains a:
* - (EMAC_FxnTable *) to a set of functions that implement a EMAC peripheral
* - (void *) data object that is associated with the EMAC_FxnTable
* - (void *) hardware attributes that are associated to the EMAC_FxnTable
*
* # Instrumentation #
* The EMAC driver interface produces log statements if instrumentation is
* enabled.
*
* Diagnostics Mask | Log details |
* ---------------- | ----------- |
* Diags_USER1 | basic operations |
* Diags_USER2 | detailed operations |
*
* ============================================================================
*/
#ifndef ti_drivers_EMAC__include
#define ti_drivers_EMAC__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stdint.h>
/**
* @defgroup EMAC_CONTROL EMAC_control command and status codes
* These EMAC macros are reservations for EMAC.h
* @{
*/
/*!
* Common EMAC_control command code reservation offset.
* EMAC driver implementations should offset command codes with
* EMAC_CMD_RESERVED growing positively
*
* Example implementation specific command codes:
* @code
* #define EMACXYZ_CMD_COMMAND0 EMAC_CMD_RESERVED + 0
* #define EMACXYZ_CMD_COMMAND1 EMAC_CMD_RESERVED + 1
* @endcode
*/
#define EMAC_CMD_RESERVED 32
/*!
* Common EMAC_control status code reservation offset.
* EMAC driver implementations should offset status codes with
* EMAC_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define EMACXYZ_STATUS_ERROR0 EMAC_STATUS_RESERVED - 0
* #define EMACXYZ_STATUS_ERROR1 EMAC_STATUS_RESERVED - 1
* #define EMACXYZ_STATUS_ERROR2 EMAC_STATUS_RESERVED - 2
* @endcode
*/
#define EMAC_STATUS_RESERVED -32
/**
* @defgroup EMAC_STATUS Status Codes
* EMAC_STATUS_* macros are general status codes returned by EMAC_control()
* @{
* @ingroup EMAC_CONTROL
*/
/*!
* @brief Successful status code returned by EMAC_control().
*
* EMAC_control() returns EMAC_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define EMAC_STATUS_SUCCESS 0
/*!
* @brief Generic error status code returned by EMAC_control().
*
* EMAC_control() returns EMAC_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define EMAC_STATUS_ERROR -1
/*!
* @brief An error status code returned by EMAC_control() for undefined
* command codes.
*
* EMAC_control() returns EMAC_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define EMAC_STATUS_UNDEFINEDCMD -2
/** @}*/
/**
* @defgroup EMAC_CMD Command Codes
* EMAC_CMD_* macros are general command codes for EMAC_control(). Not all EMAC
* driver implementations support these command codes.
* @{
* @ingroup EMAC_CONTROL
*/
/* Add Camera_CMD_<commands> here */
/** @}*/
/** @}*/
/* Prototypes of EMAC interface */
typedef void (*EMAC_InitFxn)(uint32_t);
typedef bool (*EMAC_isLinkUpFxn)(uint32_t);
/*!
* @brief EMAC Function table structure
*/
typedef struct EMAC_FxnTable {
EMAC_InitFxn emacInit;
EMAC_isLinkUpFxn emacIsLinkUp;
} EMAC_FxnTable;
/*!
* @brief EMAC Global configuration
*
* The EMAC_Config structure contains a set of pointers used to characterize
* the EMAC driver implementation.
*
* This structure needs to be defined before calling EMAC_init() and it must
* not be changed thereafter.
*
* @sa EMAC_init()
*/
typedef struct EMAC_Config {
/*! Pointer to a table of driver-specific implementations of EMAC APIs */
EMAC_FxnTable const *fxnTablePtr;
/*! Pointer to a driver specific data object */
void *object;
/*! Pointer to a driver specific hardware attributes structure */
void const *hwAttrs;
} EMAC_Config;
/*!
* @brief This function initializes the EMAC driver
*
* This function must be called by the application before the NDK stack
* thread is started.
*
* @pre The EMAC_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other EMAC driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void EMAC_init(void);
/*!
* @brief This function returns if the link is up
*
* @return true is the link is up. false if it is down.
*/
extern bool EMAC_isLinkUp(unsigned int index);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_EMAC__include */

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** ============================================================================
* @file GPIO.h
*
* @brief GPIO driver
*
* The GPIO header file should be included in an application as follows:
* @code
* #include <ti/drivers/GPIO.h>
* @endcode
*
* # Overview #
* The GPIO module allows you to manage General Purpose I/O pins via simple
* and portable APIs. GPIO pin behavior is usually configured statically,
* but can also be configured or reconfigured at runtime.
*
* Because of its simplicity, the GPIO driver does not follow the model of
* other TI-RTOS drivers in which a driver application interface has
* separate device-specific implementations. This difference is most
* apparent in the GPIOxxx_Config structure, which does not require you to
* specify a particular function table or object.
*
* # Usage #
* The following code example demonstrates how
* to configure a GPIO pin to generate an interrupt and how to toggle an
* an LED on and off within the registered interrupt callback function.
*
* @code
* #include <stdint.h>
* #include <stddef.h>
*
* // Driver Header file
* #include <ti/drivers/GPIO.h>
*
* // Example/Board Header file
* #include "Board.h"
*
* main()
* {
* // Call GPIO driver init function
* GPIO_init();
*
* // Turn on user LED
* GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON);
*
* // install Button callback
* GPIO_setCallback(Board_GPIO_BUTTON0, gpioButtonFxn0);
*
* // Enable interrupts
* GPIO_enableInt(Board_GPIO_BUTTON0);
*
* ...
* }
*
* //
* // ======== gpioButtonFxn0 ========
* // Callback function for the GPIO interrupt on Board_GPIO_BUTTON0.
* //
* void gpioButtonFxn0(uint_least8_t index)
* {
* // Toggle the LED
* GPIO_toggle(Board_GPIO_LED0);
* }
*
* @endcode
*
* Details for the example code above are described in the following
* subsections.
*
* ### GPIO Driver Configuration #
*
* In order to use the GPIO APIs, the application is required
* to provide 3 structures in the Board.c file:
* 1. An array of @ref GPIO_PinConfig elements that defines the
* initial configuration of each pin used by the application. A
* pin is referenced in the application by its corresponding index in this
* array. The pin type (that is, INPUT/OUTPUT), its initial state (that is
* OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and
* device specific pin identification are configured in each element
* of this array (see @ref GPIO_PinConfigSettings).
* Below is an MSP432 device specific example of the GPIO_PinConfig array:
* @code
* //
* // Array of Pin configurations
* // NOTE: The order of the pin configurations must coincide with what was
* // defined in MSP_EXP432P401R.h
* // NOTE: Pins not used for interrupts should be placed at the end of the
* // array. Callback entries can be omitted from callbacks array to
* // reduce memory usage.
* //
* GPIO_PinConfig gpioPinConfigs[] = {
* // Input pins
* // MSP_EXP432P401R_GPIO_S1
* GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING,
* // MSP_EXP432P401R_GPIO_S2
* GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING,
*
* // Output pins
* // MSP_EXP432P401R_GPIO_LED1
* GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
* // MSP_EXP432P401R_GPIO_LED_RED
* GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW,
* };
* @endcode
*
* 2. An array of @ref GPIO_CallbackFxn elements that is used to store
* callback function pointers for GPIO pins configured with interrupts.
* The indexes for these array elements correspond to the pins defined
* in the GPIO_pinConfig array. These function pointers can be defined
* statically by referencing the callback function name in the array
* element, or dynamically, by setting the array element to NULL and using
* GPIO_setCallback() at runtime to plug the callback entry.
* Pins not used for interrupts can be omitted from the callback array to
* reduce memory usage (if they are placed at the end of GPIO_pinConfig
* array). The callback function syntax should match the following:
* @code
* void (*GPIO_CallbackFxn)(uint_least8_t index);
* @endcode
* The index parameter is the same index that was passed to
* GPIO_setCallback(). This allows the same callback function to be used
* for multiple GPIO interrupts, by using the index to identify the GPIO
* that caused the interrupt.
* Keep in mind that the callback functions will be called in the context of
* an interrupt service routine and should be designed accordingly. When an
* interrupt is triggered, the interrupt status of all (interrupt enabled) pins
* on a port will be read, cleared, and the respective callbacks will be
* executed. Callbacks will be called in order from least significant bit to
* most significant bit.
* Below is an MSP432 device specific example of the GPIO_CallbackFxn array:
* @code
* //
* // Array of callback function pointers
* // NOTE: The order of the pin configurations must coincide with what was
* // defined in MSP_EXP432P401R.h
* // NOTE: Pins not used for interrupts can be omitted from callbacks array
* // to reduce memory usage (if placed at end of gpioPinConfigs
* // array).
* //
* GPIO_CallbackFxn gpioCallbackFunctions[] = {
* // MSP_EXP432P401R_GPIO_S1
* NULL,
* // MSP_EXP432P401R_GPIO_S2
* NULL
* };
* @endcode
*
* 3. A device specific GPIOxxx_Config structure that tells the GPIO
* driver where the two aforementioned arrays are and the number of elements
* in each. The interrupt priority of all pins configured to generate
* interrupts is also specified here. Values for the interrupt priority are
* device-specific. You should be well-acquainted with the interrupt
* controller used in your device before setting this parameter to a
* non-default value. The sentinel value of (~0) (the default value) is
* used to indicate that the lowest possible priority should be used.
* Below is an MSP432 device specific example of a GPIOxxx_Config
* structure:
* @code
* //
* // MSP432 specific GPIOxxx_Config structure
* //
* const GPIOMSP432_Config GPIOMSP432_config = {
* .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs,
* .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions,
* .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig),
* .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn),
* .intPriority = (~0)
* };
* @endcode
*
* ### Initializing the GPIO Driver #
*
* GPIO_init() must be called before any other GPIO APIs. This function
* configures each GPIO pin in the user-provided @ref GPIO_PinConfig
* array according to the defined settings. The user can also reconfigure
* a pin dynamically after GPIO_init() is called by using the
* GPIO_setConfig(), and GPIO_setCallback() APIs.
*
* # Implementation #
*
* Unlike most other TI-RTOS drivers, the GPIO driver has no generic function
* table with pointers to device-specific API implementations. All the generic
* GPIO APIs are implemented by the device-specific GPIO driver module.
* Additionally, there is no notion of an instance 'handle' with the GPIO driver.
* GPIO pins are referenced by their numeric index in the GPIO_PinConfig array.
* This design approach was used to enhance runtime and memory efficiency.
*
* ============================================================================
*/
#ifndef ti_drivers_GPIO__include
#define ti_drivers_GPIO__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/**
* @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs.
* @{
*/
/*!
* @brief Common GPIO status code reservation offset.
*
* GPIO driver implementations should offset status codes with
* GPIO_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define GPIOTXYZ_STATUS_ERROR1 GPIO_STATUS_RESERVED - 1
* #define GPIOTXYZ_STATUS_ERROR0 GPIO_STATUS_RESERVED - 0
* #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2
* @endcode
*/
#define GPIO_STATUS_RESERVED (-32)
/*!
* @brief Successful status code returned by GPI_setConfig().
*
* GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed
* successfully.
*/
#define GPIO_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by GPI_setConfig().
*
* GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed
* successfully.
*/
#define GPIO_STATUS_ERROR (-1)
/** @}*/
/*!
* @brief GPIO pin configuration settings
*
* The upper 16 bits of the 32 bit PinConfig is reserved
* for pin configuration settings.
*
* The lower 16 bits are reserved for device-specific
* port/pin identifications
*/
typedef uint32_t GPIO_PinConfig;
/*!
* @cond NODOC
* Internally used configuration bit access macros.
*/
#define GPIO_CFG_IO_MASK 0x00ff0000
#define GPIO_CFG_IO_LSB 16
#define GPIO_CFG_OUT_TYPE_MASK 0x00060000
#define GPIO_CFG_OUT_TYPE_LSB 17
#define GPIO_CFG_IN_TYPE_MASK 0x00060000
#define GPIO_CFG_IN_TYPE_LSB 17
#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000
#define GPIO_CFG_OUT_STRENGTH_LSB 20
#define GPIO_CFG_INT_MASK 0x07000000
#define GPIO_CFG_INT_LSB 24
#define GPIO_CFG_OUT_BIT 19
/*! @endcond */
/*!
* \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins
* @{
*/
/** @name GPIO_PinConfig output pin configuration macros
* @{
*/
#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */
#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */
#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */
#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */
#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */
#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to low */
#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to medium */
#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strengh to high */
#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */
#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */
/** @} */
/** @name GPIO_PinConfig input pin configuration macros
* @{
*/
#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */
#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */
#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */
#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */
/** @} */
/** @name GPIO_PinConfig interrupt configuration macros
* @{
*/
#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */
#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */
#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */
#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */
#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */
#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */
/** @} */
/** @name Special GPIO_PinConfig configuration macros
* @{
*/
/*!
* @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig()
* to only configure the interrupt attributes of a GPIO input pin.
*/
#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */
/*!
* @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init()
* NOT to configure the corresponding pin
*/
#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */
/** @} */
/** @} end of GPIO_PinConfigSettings group */
/*!
* @brief GPIO callback function type
*
* @param index GPIO index. This is the same index that
* was passed to GPIO_setCallback(). This allows
* you to use the same callback function for multiple
* GPIO interrupts, by using the index to identify
* the GPIO that caused the interrupt.
*/
typedef void (*GPIO_CallbackFxn)(uint_least8_t index);
/*!
* @brief Clear a GPIO pin interrupt flag
*
* Clears the GPIO interrupt for the specified index.
*
* Note: It is not necessary to call this API within a
* callback assigned to a pin.
*
* @param index GPIO index
*/
extern void GPIO_clearInt(uint_least8_t index);
/*!
* @brief Disable a GPIO pin interrupt
*
* Disables interrupts for the specified GPIO index.
*
* @param index GPIO index
*/
extern void GPIO_disableInt(uint_least8_t index);
/*!
* @brief Enable a GPIO pin interrupt
*
* Enables GPIO interrupts for the selected index to occur.
*
* Note: Prior to enabling a GPIO pin interrupt, make sure
* that a corresponding callback function has been provided.
* Use the GPIO_setCallback() API for this purpose at runtime.
* Alternatively, the callback function can be statically
* configured in the GPIO_CallbackFxn array provided.
*
* @param index GPIO index
*/
extern void GPIO_enableInt(uint_least8_t index);
/*!
* @brief Get the current configuration for a gpio pin
*
* The pin configuration is provided in the static GPIO_PinConfig array,
* but can be changed with GPIO_setConfig(). GPIO_getConfig() gets the
* current pin configuration.
*
* @param index GPIO index
* @param pinConfig Location to store device specific pin
* configuration settings
*/
extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig);
/*!
* @brief Initializes the GPIO module
*
* The pins defined in the application-provided *GPIOXXX_config* structure
* are initialized accordingly.
*
* @pre The GPIO_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other GPIO driver APIs.
*/
extern void GPIO_init();
/*!
* @brief Reads the value of a GPIO pin
*
* The value returned will either be zero or one depending on the
* state of the pin.
*
* @param index GPIO index
*
* @return 0 or 1, depending on the state of the pin.
*/
extern uint_fast8_t GPIO_read(uint_least8_t index);
/*!
* @brief Bind a callback function to a GPIO pin interrupt
*
* Associate a callback function with a particular GPIO pin interrupt.
*
* Callbacks can be changed at any time, making it easy to switch between
* efficient, state-specific interrupt handlers.
*
* Note: The callback function is called within the context of an interrupt
* handler.
*
* Note: This API does not enable the GPIO pin interrupt.
* Use GPIO_enableInt() and GPIO_disableInt() to enable
* and disable the pin interrupt as necessary.
*
* Note: it is not necessary to call GPIO_clearInt() within a callback.
* That operation is performed internally before the callback is invoked.
*
* @param index GPIO index
* @param callback address of the callback function
*/
extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback);
/*!
* @brief Configure the gpio pin
*
* Dynamically configure a gpio pin to a device specific setting.
* For many applications, the pin configurations provided in the static
* GPIO_PinConfig array is sufficient.
*
* For input pins with interrupt configurations, a corresponding interrupt
* object will be created as needed.
*
* @param index GPIO index
* @param pinConfig device specific pin configuration settings
*/
extern int_fast16_t GPIO_setConfig(uint_least8_t index,
GPIO_PinConfig pinConfig);
/*!
* @brief Toggles the current state of a GPIO
*
* @param index GPIO index
*/
extern void GPIO_toggle(uint_least8_t index);
/*!
* @brief Writes the value to a GPIO pin
*
* @param index GPIO index
* @param value must be either 0 or 1
*/
extern void GPIO_write(uint_least8_t index, unsigned int value);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_GPIO__include */

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== I2C.c ========
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/dpl/HwiP.h>
#include <ti/drivers/I2C.h>
extern const I2C_Config I2C_config[];
extern const uint_least8_t I2C_count;
/* Default I2C parameters structure */
const I2C_Params I2C_defaultParams = {
I2C_MODE_BLOCKING, /* transferMode */
NULL, /* transferCallbackFxn */
I2C_100kHz, /* bitRate */
NULL /* custom */
};
static bool isInitialized = false;
/*
* ======== I2C_cancel ========
*/
void I2C_cancel(I2C_Handle handle)
{
handle->fxnTablePtr->cancelFxn(handle);
}
/*
* ======== I2C_close ========
*/
void I2C_close(I2C_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== I2C_control ========
*/
int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, void *controlArg)
{
return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg));
}
/*
* ======== I2C_init ========
*/
void I2C_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < I2C_count; i++) {
I2C_config[i].fxnTablePtr->initFxn((I2C_Handle)&(I2C_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== I2C_open ========
*/
I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params)
{
I2C_Handle handle = NULL;
if (isInitialized && (index < I2C_count)) {
/* If params are NULL use defaults. */
if (params == NULL) {
params = (I2C_Params *) &I2C_defaultParams;
}
/* Get handle for this driver instance */
handle = (I2C_Handle)&(I2C_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== I2C_Params_init =======
*/
void I2C_Params_init(I2C_Params *params)
{
*params = I2C_defaultParams;
}
/*
* ======== I2C_transfer ========
*/
bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction)
{
return (handle->fxnTablePtr->transferFxn(handle, transaction));
}

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*!*****************************************************************************
* @file I2C.h
*
* @brief I2C driver interface
*
* The I2C driver interface provides device independent APIs, data types,
* and macros. The I2C header file should be included in an application as
* follows:
* @code
* #include <ti/drivers/I2C.h>
* @endcode
*
* # Overview #
* This section assumes that you have background knowledge and understanding
* about how the I2C protocol operates. For the full I2C specifications and
* user manual (UM10204), see the NXP Semiconductors website.
*
* The I2C driver has been designed to operate as a single I2C master by
* performing I2C transactions between the target and I2C slave peripherals.
* The I2C driver does not support I2C slave mode.
* I2C is a communication protocol - the specifications define how data
* transactions are to occur via the I2C bus. The specifications do not
* define how data is to be formatted or handled, allowing for flexible
* implementations across different peripheral vendors. As a result, the
* I2C handles only the exchange of data (or transactions) between master
* and slaves. It is the left to the application to interpret and
* manipulate the contents of each specific I2C peripheral.
*
* The I2C driver has been designed to operate in an RTOS environment. It
* protects its transactions with OS primitives supplied by the underlying
* RTOS.
*
* # Usage #
*
* The I2C driver includes the following APIs:
* - I2C_init(): Initialize the I2C driver.
* - I2C_Params_init(): Initialize an #I2C_Params structure with default
* vaules.
* - I2C_open(): Open an instance of the I2C driver.
* - I2C_control(): Performs implemenation-specific features on a given
* I2C peripheral.
* - I2C_transfer(): Transfer the data.
* - I2C_close(): De-initialize the I2C instance.
*
*
* ### I2C Driver Configuration #
*
* In order to use the I2C APIs, the application is required
* to provide device-specific I2C configuration in the Board.c file.
* The I2C driver interface defines a configuration data structure:
*
* @code
* typedef struct I2C_Config_ {
* I2C_FxnTable const *fxnTablePtr;
* void *object;
* void const *hwAttrs;
* } I2C_Config;
* @endcode
*
* The application must declare an array of I2C_Config elements, named
* I2C_config[]. Each element of I2C_config[] must be populated with
* pointers to a device specific I2C driver implementation's function
* table, driver object, and hardware attributes. The hardware attributes
* define properties such as the I2C peripheral's base address and
* pins. Each element in I2C_config[] corresponds to
* an I2C instance, and none of the elements should have NULL pointers.
* There is no correlation between the index and the
* peripheral designation (such as I2C0 or I2C1). For example, it is
* possible to use I2C_config[0] for I2C1.
*
* Because the I2C configuration is very device dependent, you will need to
* check the doxygen for the device specific I2C implementation. There you
* will find a description of the I2C hardware attributes. Please also
* refer to the Board.c file of any of your examples to see the I2C
* configuration.
*
* ### Initializing the I2C Driver #
*
* I2C_init() must be called before any other I2C APIs. This function
* iterates through the elements of the I2C_config[] array, calling
* the element's device implementation I2C initialization function.
*
* ### I2C Parameters
*
* The #I2C_Params structure is passed to the I2C_open() call. If NULL
* is passed for the parameters, I2C_open() uses default parameters.
* An #I2C_Params structure is initialized with default values by passing
* it to I2C_Params_init().
* Some of the I2C parameters are described below. To see brief descriptions
* of all the parameters, see #I2C_Params.
*
* #### I2C Transfer Mode
* The I2C driver supports two transfer modes of operation: blocking and
* callback:
* - #I2C_MODE_BLOCKING: The call to I2C_transfer() blocks until the
* transfer completes.
* - #I2C_MODE_CALLBACK: The call to I2C_transfer() returns immediately.
* When the transfer completes, the I2C driver will call a user-
* specified callback function.
*
* The transfer mode is determined by the #I2C_Params.transferMode parameter
* passed to I2C_open(). The I2C driver defaults to blocking mode, if the
* application does not set it.
*
* In blocking mode, a task calling I2C_transfer() is blocked until the
* transaction completes. Other tasks requesting I2C transactions while
* a transaction is currently taking place, are also placed into a
* blocked state.
*
* In callback mode, an I2C_transfer() functions asynchronously, which
* means that it does not block a calling task's execution. In this
* mode, the user must set #I2C_Params.transferCallbackFxn to a user-
* provided callback function. After an I2C transaction has completed,
* the I2C driver calls the user- provided callback function.
* If another I2C transaction is requested, the transaction is queued up.
* As each transfer completes, the I2C driver will call the user-specified
* callback function. The user callback will be called from either hardware
* or software interrupt context, depending upon the device implementation.
*
* Once an I2C driver instance is opened, the
* only way to change the transfer mode is to close and re-open the I2C
* instance with the new transfer mode.
*
* #### Specifying an I2C Bus Frequency
* The I2C controller's bus frequency is determined by #I2C_Params.bitRate
* passed to I2C_open(). The standard I2C bus frequencies are 100 kHz and
* 400 kHz, with 100 kHz being the default.
*
* ### Opening the I2C Driver #
* After initializing the I2C driver by calling I2C_init(), the application
* can open an I2C instance by calling I2C_open(). This function
* takes an index into the I2C_config[] array and an I2C parameters data
* structure. The I2C instance is specified by the index of the I2C in
* I2C_config[]. Only one I2C index can be used at a time;
* calling I2C_open() a second time with the same index previosly
* passed to I2C_open() will result in an error. You can,
* though, re-use the index if the instance is closed via I2C_close().
*
* If no I2C_Params structure is passed to I2C_open(), default values are
* used. If the open call is successful, it returns a non-NULL value.
*
* Example opening an I2C driver instance in blocking mode:
* @code
* I2C_Handle i2c;
*
* // NULL params are used, so default to blocking mode, 100 KHz
* i2c = I2C_open(Board_I2C0, NULL);
*
* if (!i2c) {
* // Error opening the I2C
* }
* @endcode
*
* Example opening an I2C driver instance in callback mode and 400KHz bit rate:
*
* @code
* I2C_Handle i2c;
* I2C_Params params;
*
* I2C_Params_init(&params);
* params.transferMode = I2C_MODE_CALLBACK;
* params.transferCallbackFxn = myCallbackFunction;
* params.bitRate = I2C_400kHz;
*
* handle = I2C_open(Board_I2C0, &params);
* if (!i2c) {
* // Error opening I2C
* }
* @endcode
*
* ### Transferring data #
* An I2C transaction with an I2C peripheral is started by calling
* I2C_transfer(). Three types of transactions are supported: Write, Read,
* or Write/Read. Each transfer is completed before another transfer is
* initiated.
*
* For Write/Read transactions, the specified data is first written to the
* peripheral, then a repeated start is sent by the driver, which initiates
* the read operation. This type of transfer is useful if an I2C peripheral
* has a pointer register that needs to be adjusted prior to reading from
* the referenced data register.
*
* The details of each transaction are specified with an #I2C_Transaction data
* structure. This structure defines the slave I2C address, pointers
* to write and read buffers, and their associated byte counts. If
* no data needs to be written or read, the corresponding byte counts should
* be set to zero.
*
* If an I2C transaction is requested while a transaction is currently
* taking place, the new transaction is placed onto a queue to be processed
* in the order in which it was received.
*
* The below example shows sending three bytes of data to a slave peripheral
* at address 0x50, in blocking mode:
*
* @code
* unsigned char writeBuffer[3];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = writeBuffer;
* i2cTransaction.writeCount = 3;
* i2cTransaction.readBuf = NULL;
* i2cTransaction.readCount = 0;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* The next example shows reading of five bytes of data from the I2C
* peripheral, also in blocking mode:
*
* @code
* unsigned char readBuffer[5];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = NULL;
* i2cTransaction.writeCount = 0;
* i2cTransaction.readBuf = readBuffer;
* i2cTransaction.readCount = 5;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* This example shows writing of two bytes and reading of four bytes in a
* single transaction.
*
* @code
* unsigned char readBuffer[4];
* unsigned char writeBuffer[2];
* I2C_Transaction i2cTransaction;
*
* i2cTransaction.slaveAddress = 0x50;
* i2cTransaction.writeBuf = writeBuffer;
* i2cTransaction.writeCount = 2;
* i2cTransaction.readBuf = readBuffer;
* i2cTransaction.readCount = 4;
*
* status = I2C_transfer(i2c, &i2cTransaction);
* if (!status) {
* // Unsuccessful I2C transfer
* }
* @endcode
*
* This final example shows usage of asynchronous callback mode, with queuing
* of multiple transactions. Because multiple transactions are simultaneously
* queued, separate I2C_Transaction structures must be used. (This is a
* general rule, that I2C_Transaction structures cannot be reused until
* it is known that the previous transaction has completed.)
*
* First, for the callback function (that is specified in the I2C_open() call)
* the "arg" in the I2C_Transaction structure is a semaphore handle. When
* this value is non-NULL, sem_post() is called in the callback using
* the specified handle, to signal completion to the task that queued the
* transactions:
*
* @code
* Void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, Bool transfer) {
* if (msg->arg != NULL) {
* sem_post((sem_t *)(msg->arg));
* }
* }
* @endcode
*
* Snippets of the task code that initiates the transactions are shown below.
* Note the use of multiple I2C_Transaction structures, and passing of the
* handle of the semaphore to be posted via i2cTransaction2.arg.
* I2C_transfer() is called three times to initiate each transaction.
* Since callback mode is used, these functions return immediately. After
* the transactions have been queued, other work can be done, and then
* eventually sem_wait() is called to wait for the last I2C
* transaction to complete. Once the callback posts the semaphore the task
* will be moved to the ready state, so the task can resume execution.
*
* @code
* Void taskfxn(arg0, arg1) {
*
* I2C_Transaction i2cTransaction0;
* I2C_Transaction i2cTransaction1;
* I2C_Transaction i2cTransaction2;
*
* ...
* i2cTransaction0.arg = NULL;
* i2cTransaction1.arg = NULL;
* i2cTransaction2.arg = semaphoreHandle;
*
* ...
* I2C_transfer(i2c, &i2cTransaction0);
* I2C_transfer(i2c, &i2cTransaction1);
* I2C_transfer(i2c, &i2cTransaction2);
*
* ...
*
* sem_wait(semaphoreHandle);
*
* ...
* }
* @endcode
*
* # Implementation #
*
* This top-level I2C module serves as the main interface for RTOS
* applications. Its purpose is to redirect the module's APIs to specific
* peripheral implementations which are specified using a pointer to an
* #I2C_FxnTable.
*
* The I2C driver interface module is joined (at link time) to an
* array of I2C_Config data structures named *I2C_config*.
* *I2C_config* is typically defined in the Board.c file used for the
* application. If there are multiple instances of I2C peripherals on the
* device, there will typically be multiple I2C_Config structures defined in
* the board file. Each entry in *I2C_config* contains a:
* - (I2C_FxnTable *) to a set of functions that implement a I2C peripheral
* - (void *) data object that is associated with the I2C_FxnTable
* - (void *) hardware attributes that are associated to the I2C_FxnTable
*
*******************************************************************************
*/
#ifndef ti_drivers_I2C__include
#define ti_drivers_I2C__include
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
/**
* @defgroup I2C_CONTROL I2C_control command and status codes
* These I2C macros are reservations for I2C.h
* @{
*/
/*!
* Common I2C_control command code reservation offset.
* I2C driver implementations should offset command codes with I2C_CMD_RESERVED
* growing positively
*
* Example implementation specific command codes:
* @code
* #define I2CXYZ_CMD_COMMAND0 I2C_CMD_RESERVED + 0
* #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1
* @endcode
*/
#define I2C_CMD_RESERVED (32)
/*!
* Common I2C_control status code reservation offset.
* I2C driver implementations should offset status codes with
* I2C_STATUS_RESERVED growing negatively.
*
* Example implementation specific status codes:
* @code
* #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0
* #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1
* #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2
* @endcode
*/
#define I2C_STATUS_RESERVED (-32)
/**
* @defgroup I2C_STATUS Status Codes
* I2C_STATUS_* macros are general status codes returned by I2C_control()
* @{
* @ingroup I2C_CONTROL
*/
/*!
* @brief Successful status code returned by I2C_control().
*
* I2C_control() returns I2C_STATUS_SUCCESS if the control code was executed
* successfully.
*/
#define I2C_STATUS_SUCCESS (0)
/*!
* @brief Generic error status code returned by I2C_control().
*
* I2C_control() returns I2C_STATUS_ERROR if the control code was not executed
* successfully.
*/
#define I2C_STATUS_ERROR (-1)
/*!
* @brief An error status code returned by I2C_control() for undefined
* command codes.
*
* I2C_control() returns I2C_STATUS_UNDEFINEDCMD if the control code is not
* recognized by the driver implementation.
*/
#define I2C_STATUS_UNDEFINEDCMD (-2)
/** @}*/
/**
* @defgroup I2C_CMD Command Codes
* I2C_CMD_* macros are general command codes for I2C_control(). Not all I2C
* driver implementations support these command codes.
* @{
* @ingroup I2C_CONTROL
*/
/* Add I2C_CMD_<commands> here */
/** @}*/
/** @}*/
/*!
* @brief A handle that is returned from an I2C_open() call.
*/
typedef struct I2C_Config_ *I2C_Handle;
/*!
* @brief I2C transaction
*
* This structure defines an I2C transaction. It specifies the buffer(s) and
* buffer size(s) to be written to and/or read from an I2C slave peripheral.
* arg is an optional user-supplied argument that will be passed
* to the user-supplied callback function when the I2C driver is in
* I2C_MODE_CALLBACK.
* nextPtr is a pointer used internally by the driver for queuing of multiple
* transactions; this value must never be modified by the user application.
*/
typedef struct I2C_Transaction_ {
void *writeBuf; /*!< Buffer containing data to be written */
size_t writeCount; /*!< Number of bytes to be written to the slave */
void *readBuf; /*!< Buffer to which data is to be read into */
size_t readCount; /*!< Number of bytes to be read from the slave */
uint_least8_t slaveAddress; /*!< Address of the I2C slave peripheral */
void *arg; /*!< Argument to be passed to the callback function */
void *nextPtr; /*!< Used for queuing in I2C_MODE_CALLBACK mode */
} I2C_Transaction;
/*!
* @brief I2C transfer mode
*
* I2C_MODE_BLOCKING blocks task execution while an I2C transfer is in
* progress.
* I2C_MODE_CALLBACK does not block task execution, but calls a callback
* function when the I2C transfer has completed.
*/
typedef enum I2C_TransferMode_ {
I2C_MODE_BLOCKING, /*!< I2C_transfer() blocks execution */
I2C_MODE_CALLBACK /*!< I2C_transfer() does not block */
} I2C_TransferMode;
/*!
* @brief I2C callback function
*
* User-definable callback function prototype. The I2C driver will call this
* callback upon transfer completion, specifying the I2C handle for the
* transfer (as returned from I2C_open()), the pointer to the I2C_Transaction
* that just completed, and the return value of I2C_transfer(). Note that
* this return value will be the same as if the transfer were performed in
* blocking mode.
*
* @param I2C_Handle I2C_Handle
* @param I2C_Transaction* Address of the I2C_Transaction
* @param bool Result of the I2C transfer
*/
typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction,
bool transferStatus);
/*!
* @brief I2C bitRate
*
* Specifies one of the standard I2C bus bit rates for I2C communications.
* The default is I2C_100kHz.
*/
typedef enum I2C_BitRate_ {
I2C_100kHz = 0,
I2C_400kHz = 1
} I2C_BitRate;
/*!
* @brief I2C Parameters
*
* I2C parameters are used with the I2C_open() call. Default values for
* these parameters are set using I2C_Params_init().
*
* If I2C_TransferMode is set to I2C_MODE_BLOCKING, I2C_transfer() function
* calls will block thread execution until the transaction has completed. In
* this case, the transferCallbackFxn parameter will be ignored.
*
* If I2C_TransferMode is set to I2C_MODE_CALLBACK, I2C_transfer() will not
* block thread execution, but it will call the function specified by
* transferCallbackFxn upon transfer completion. Sequential calls to
* I2C_transfer() in I2C_MODE_CALLBACK will put the I2C_Transaction structures
* onto an internal queue that automatically starts queued transactions after
* the previous transaction has completed. This queuing occurs regardless of
* any error state from previous transactions.
*
* I2C_BitRate specifies the I2C bus rate used for I2C communications.
*
* @sa I2C_Params_init()
*/
typedef struct I2C_Params_ {
I2C_TransferMode transferMode; /*!< Blocking or Callback mode */
I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */
I2C_BitRate bitRate; /*!< I2C bus bit rate */
void *custom; /*!< Custom argument used by driver
implementation */
} I2C_Params;
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_cancel().
*/
typedef void (*I2C_CancelFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_close().
*/
typedef void (*I2C_CloseFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_control().
*/
typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd,
void *controlArg);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_init().
*/
typedef void (*I2C_InitFxn) (I2C_Handle handle);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_open().
*/
typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params *params);
/*!
* @brief A function pointer to a driver-specific implementation of
* I2C_transfer().
*/
typedef bool (*I2C_TransferFxn) (I2C_Handle handle,
I2C_Transaction *transaction);
/*!
* @brief The definition of an I2C function table that contains the
* required set of functions to control a specific I2C driver
* implementation.
*/
typedef struct I2C_FxnTable_ {
/*! Cancel all I2C data transfers */
I2C_CancelFxn cancelFxn;
/*! Close the specified peripheral */
I2C_CloseFxn closeFxn;
/*! Implementation-specific control function */
I2C_ControlFxn controlFxn;
/*! Initialize the given data object */
I2C_InitFxn initFxn;
/*! Open the specified peripheral */
I2C_OpenFxn openFxn;
/*! Initiate an I2C data transfer */
I2C_TransferFxn transferFxn;
} I2C_FxnTable;
/*!
* @brief I2C global configuration
*
* The I2C_Config structure contains a set of pointers used to characterize
* the I2C driver implementation.
*
* This structure needs to be defined before calling I2C_init() and it must
* not be changed thereafter.
*
* @sa I2C_init()
*/
typedef struct I2C_Config_ {
/*! Pointer to a table of driver-specific implementations of I2C APIs */
I2C_FxnTable const *fxnTablePtr;
/*! Pointer to a driver-specific data object */
void *object;
/*! Pointer to a driver-specific hardware attributes structure */
void const *hwAttrs;
} I2C_Config;
/*!
* @brief Cancel all I2C transfers
*
* This function will cancel asynchronous I2C_transfer() operations, and is
* applicable only for I2C_MODE_CALLBACK. An in progress transfer, as well
* as any queued transfers will be canceled. The individual callback functions
* for each transfer will be called from the context that I2C_cancel() is
* called.
*
* @pre I2C_Transfer() has been called.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @note Different I2C slave devices will behave differently when an
* in-progress transfer fails and needs to be canceled. The slave
* may need to be reset, or there may be other slave-specific
* steps that can be used to successfully resume communication.
*
* @sa I2C_transfer()
*/
extern void I2C_cancel(I2C_Handle handle);
/*!
* @brief Close an I2C peripheral specified by an I2C_Handle
*
* @pre I2C_open() has been called.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @sa I2C_open()
*/
extern void I2C_close(I2C_Handle handle);
/*!
* @brief Perform implementation-specific features on a given
* I2C_Handle.
*
* Commands for I2C_control() can originate from I2C.h or from implementation
* specific I2C*.h (I2CCC26XX.h_, I2CMSP432.h_, etc.) files.
* While commands from I2C.h are API portable across driver implementations,
* not all implementations may support all these commands.
* Conversely, commands from driver implementation specific I2C*.h files add
* unique driver capabilities but are not API portable across all I2C driver
* implementations.
*
* Commands supported by I2C.h follow a I2C_CMD_\<cmd\> naming
* convention.<br>
* Commands supported by I2C*.h follow a I2C*_CMD_\<cmd\> naming
* convention.<br>
* Each control command defines @b arg differently. The types of @b arg are
* documented with each command.
*
* See @ref I2C_CMD "I2C_control command codes" for command codes.
*
* See @ref I2C_STATUS "I2C_control return status codes" for status codes.
*
* @pre I2C_open() has to be called first.
*
* @param handle An I2C_Handle returned from I2C_open()
*
* @param cmd I2C.h or I2C*.h command.
*
* @param controlArg An optional R/W (read/write) command argument
* accompanied with cmd
*
* @return Implementation-specific return codes. Negative values indicate
* unsuccessful operations.
*
* @sa I2C_open()
*/
extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd,
void *controlArg);
/*!
* @brief Initializes the I2C module
*
* @pre The I2C_config structure must exist and be persistent before this
* function can be called. This function must also be called before
* any other I2C driver APIs. This function call does not modify any
* peripheral registers.
*/
extern void I2C_init(void);
/*!
* @brief Initialize a given I2C peripheral as identified by an index value.
* The I2C_Params structure defines the operating mode, and any
* related settings.
*
* @pre The I2C controller has been initialized, via a previous call to
* I2C_init()
*
* @param index Logical peripheral number for the I2C indexed into
* the I2C_config table
*
* @param params Pointer to a parameter block. Default values will be
* used if NULL is specified for params. All the fields
* in this structure are are considered RO (read-only).
*
* @return An I2C_Handle on success, or NULL on an error, or if the peripheral
* is already opened.
*
* @sa I2C_init()
* @sa I2C_close()
*/
extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params);
/*!
* @brief Initialize an I2C_Params struct to its defaults
*
* @param params A pointer to I2C_Params structure for
* initialization
*
* Defaults values are:
* transferMode = I2C_MODE_BLOCKING
* transferCallbackFxn = NULL
* bitRate = I2C_100kHz
*/
extern void I2C_Params_init(I2C_Params *params);
/*!
* @brief Perform an I2C transaction with an I2C slave peripheral.
*
* This function will perform an I2C transfer, as specified by an
* I2C_Transaction structure.
*
* An I2C transaction may write data to a peripheral, or read data from a
* peripheral, or both write and read data, in a single transaction. If there
* is any data to be written, it will always be sent before any data is read
* from the peripheral.
*
* The data written to the peripheral is preceded with the peripheral's 7-bit
* I2C slave address (with the Write bit set).
* After all the data has been transmitted, the driver will evaluate if any
* data needs to be read from the device.
* If yes, another START bit is sent, along with the same 7-bit I2C slave
* address (with the Read bit). After the specified number of bytes have been
* read, the transfer is ended with a NACK and a STOP bit. Otherwise, if
* no data is to be read, the transfer is concluded with a STOP bit.
*
* In I2C_MODE_BLOCKING, I2C_transfer() will block thread execution until the
* transaction completes. Therefore, this function must only be called from an
* appropriate thread context (e.g., Task context for the TI-RTOS kernel).
*
* In I2C_MODE_CALLBACK, the I2C_transfer() call does not block thread
* execution. Instead, a callback function (specified during I2C_open(), via
* the transferCallbackFxn field in the I2C_Params structure) is called when
* the transfer completes. Success or failure of the transaction is reported
* via the callback function's bool argument. If a transfer is already in
* progress, the new transaction is put on an internal queue. The driver
* services the queue in a first come first served basis.
*
* @param handle An I2C_Handle
*
* @param transaction A pointer to an I2C_Transaction. All of the fields
* within the transaction structure should be considered
* write only, unless otherwise noted in the driver
* implementation.
*
* @note The I2C_Transaction structure must persist unmodified until the
* corresponding call to I2C_transfer() has completed.
*
* @return In I2C_MODE_BLOCKING: true for a successful transfer; false for an
* error (for example, an I2C bus fault (NACK)).
*
* In I2C_MODE_CALLBACK: always true. The transferCallbackFxn's bool
* argument will be true to indicate success, and false to indicate
* an error.
*
* @sa I2C_open
*/
extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction);
#ifdef __cplusplus
}
#endif
#endif /* ti_drivers_I2C__include */

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/*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* * Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ======== I2CSlave.c ========
*/
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include <stdlib.h>
#include <ti/drivers/dpl/HwiP.h>
#include <ti/drivers/I2CSlave.h>
extern const I2CSlave_Config I2CSlave_config[];
extern const uint_least8_t I2CSlave_count;
/* Default I2CSlave parameters structure */
const I2CSlave_Params I2CSlave_defaultParams = {
I2CSLAVE_MODE_BLOCKING, /* transferMode */
NULL, /* transferCallbackFxn */
NULL /* custom */
};
static bool isInitialized = false;
/*
* ======== I2CSlave_close ========
*/
void I2CSlave_close(I2CSlave_Handle handle)
{
handle->fxnTablePtr->closeFxn(handle);
}
/*
* ======== I2CSlave_control ========
*/
int_fast16_t I2CSlave_control(I2CSlave_Handle handle, uint_fast16_t cmd, void *arg)
{
return (handle->fxnTablePtr->controlFxn(handle, cmd, arg));
}
/*
* ======== I2CSlave_init ========
*/
void I2CSlave_init(void)
{
uint_least8_t i;
uint_fast32_t key;
key = HwiP_disable();
if (!isInitialized) {
isInitialized = (bool) true;
/* Call each driver's init function */
for (i = 0; i < I2CSlave_count; i++) {
I2CSlave_config[i].fxnTablePtr->initFxn((I2CSlave_Handle)&(I2CSlave_config[i]));
}
}
HwiP_restore(key);
}
/*
* ======== I2CSlave_open ========
*/
I2CSlave_Handle I2CSlave_open(uint_least8_t index, I2CSlave_Params *params)
{
I2CSlave_Handle handle = NULL;
/* Verify driver index and state */
if (isInitialized && (index < I2CSlave_count)) {
/* Use defaults if params are NULL. */
if (params == NULL) {
params = (I2CSlave_Params *) &I2CSlave_defaultParams;
}
/* Get handle for this driver instance */
handle = (I2CSlave_Handle)&(I2CSlave_config[index]);
handle = handle->fxnTablePtr->openFxn(handle, params);
}
return (handle);
}
/*
* ======== I2CSlave_Params_init =======
*/
void I2CSlave_Params_init(I2CSlave_Params *params)
{
*params = I2CSlave_defaultParams;
}
/*
* ======== I2CSlave_read ========
*/
bool I2CSlave_read(I2CSlave_Handle handle, void *buffer, size_t size)
{
return (handle->fxnTablePtr->readFxn(handle, buffer, size));
}
/*
* ======== I2CSlave_write ========
*/
bool I2CSlave_write(I2CSlave_Handle handle, const void *buffer, size_t size)
{
return (handle->fxnTablePtr->writeFxn(handle, buffer, size));
}

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