From d148ea1d7ff79325f4ce738be2093de24b7ad530 Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Fri, 16 Sep 2022 10:41:45 -0400 Subject: [PATCH] intel_adsp: mem_window: support read-only flag Some windows might need to be set as writtable, so add a flag read-only to DTS bindings which is set to true for all windows right now. This can be set to false where needed. Signed-off-by: Anas Nashif --- dts/bindings/memory-window/intel,adsp-mem-window.yaml | 3 +++ dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 2 ++ dts/xtensa/intel/intel_adsp_cavs15.dtsi | 2 ++ dts/xtensa/intel/intel_adsp_cavs18.dtsi | 2 ++ dts/xtensa/intel/intel_adsp_cavs20.dtsi | 2 ++ dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi | 2 ++ dts/xtensa/intel/intel_adsp_cavs25.dtsi | 2 ++ soc/xtensa/intel_adsp/common/include/mem_window.h | 1 + soc/xtensa/intel_adsp/common/mem_window.c | 9 +++++++-- 9 files changed, 23 insertions(+), 2 deletions(-) diff --git a/dts/bindings/memory-window/intel,adsp-mem-window.yaml b/dts/bindings/memory-window/intel,adsp-mem-window.yaml index 7c4d4e8bd9..4be6d182e7 100644 --- a/dts/bindings/memory-window/intel,adsp-mem-window.yaml +++ b/dts/bindings/memory-window/intel,adsp-mem-window.yaml @@ -20,3 +20,6 @@ properties: offset: type: int description: offset from memory base. + + read-only: + type: boolean diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index 9c0ff0411b..aced2617ca 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -163,6 +163,7 @@ offset = <0x4000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@70208 { compatible = "intel,adsp-mem-window"; @@ -180,6 +181,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x70218 0x8>; memory = <&sram0>; + read-only; }; tlb: tlb@17e000 { diff --git a/dts/xtensa/intel/intel_adsp_cavs15.dtsi b/dts/xtensa/intel/intel_adsp_cavs15.dtsi index b5eb3f08f1..23498f78a4 100644 --- a/dts/xtensa/intel/intel_adsp_cavs15.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs15.dtsi @@ -79,6 +79,7 @@ offset = <0x6000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@1588 { compatible = "intel,adsp-mem-window"; @@ -96,6 +97,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x1598 0x8>; memory = <&sram0>; + read-only; }; core_intc: core_intc@0 { diff --git a/dts/xtensa/intel/intel_adsp_cavs18.dtsi b/dts/xtensa/intel/intel_adsp_cavs18.dtsi index 532521fa2d..35b98b9f19 100644 --- a/dts/xtensa/intel/intel_adsp_cavs18.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs18.dtsi @@ -71,6 +71,7 @@ offset = <0x4000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@71a08 { compatible = "intel,adsp-mem-window"; @@ -88,6 +89,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x71a18 0x8>; memory = <&sram0>; + read-only; }; l2lm: l2lm@71d00 { diff --git a/dts/xtensa/intel/intel_adsp_cavs20.dtsi b/dts/xtensa/intel/intel_adsp_cavs20.dtsi index 3eaef70fd5..05fc908a3e 100644 --- a/dts/xtensa/intel/intel_adsp_cavs20.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs20.dtsi @@ -71,6 +71,7 @@ offset = <0x4000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@71a08 { compatible = "intel,adsp-mem-window"; @@ -88,6 +89,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x71a18 0x8>; memory = <&sram0>; + read-only; }; l2lm: l2lm@71d00 { diff --git a/dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi b/dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi index 4dee64ba8f..d6c05d12c3 100644 --- a/dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi @@ -51,6 +51,7 @@ offset = <0x4000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@71a08 { compatible = "intel,adsp-mem-window"; @@ -68,6 +69,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x71a18 0x8>; memory = <&sram0>; + read-only; }; l2lm: l2lm@71d00 { compatible = "intel,cavs-l2lm"; diff --git a/dts/xtensa/intel/intel_adsp_cavs25.dtsi b/dts/xtensa/intel/intel_adsp_cavs25.dtsi index 95ec346846..70b08bf8cb 100644 --- a/dts/xtensa/intel/intel_adsp_cavs25.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs25.dtsi @@ -91,6 +91,7 @@ offset = <0x4000>; memory = <&sram0>; initialize; + read-only; }; mem_window1: mem_window@71a08 { compatible = "intel,adsp-mem-window"; @@ -108,6 +109,7 @@ compatible = "intel,adsp-mem-window"; reg = <0x71a18 0x8>; memory = <&sram0>; + read-only; }; sspbase: ssp_base@71c00 { diff --git a/soc/xtensa/intel_adsp/common/include/mem_window.h b/soc/xtensa/intel_adsp/common/include/mem_window.h index 3a03937152..e51479462f 100644 --- a/soc/xtensa/intel_adsp/common/include/mem_window.h +++ b/soc/xtensa/intel_adsp/common/include/mem_window.h @@ -14,6 +14,7 @@ struct mem_win_config { uint32_t offset; uint32_t mem_base; bool initialize; + bool read_only; }; #endif diff --git a/soc/xtensa/intel_adsp/common/mem_window.c b/soc/xtensa/intel_adsp/common/mem_window.c index 7861edbad4..070628358b 100644 --- a/soc/xtensa/intel_adsp/common/mem_window.c +++ b/soc/xtensa/intel_adsp/common/mem_window.c @@ -36,8 +36,12 @@ __imr int mem_win_init(const struct device *dev) } sys_write32(config->size | 0x7, DMWLO(config->base_addr)); - sys_write32((config->mem_base | ADSP_DMWBA_READONLY | ADSP_DMWBA_ENABLE), - DMWBA(config->base_addr)); + if (config->read_only) { + sys_write32((config->mem_base | ADSP_DMWBA_READONLY | ADSP_DMWBA_ENABLE), + DMWBA(config->base_addr)); + } else { + sys_write32((config->mem_base | ADSP_DMWBA_ENABLE), DMWBA(config->base_addr)); + } return 0; } @@ -47,6 +51,7 @@ __imr int mem_win_init(const struct device *dev) .base_addr = DT_INST_REG_ADDR(inst), \ .size = WIN_SIZE(inst), \ .offset = WIN_OFFSET(inst), \ + .read_only = DT_INST_PROP(inst, read_only), \ .mem_base = DT_REG_ADDR(DT_INST_PHANDLE(inst, memory)) + WIN_OFFSET(inst), \ .initialize = DT_INST_PROP(inst, initialize), \ }; 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