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drivers/timer: Use correct timer for CPU in SMP Risc-V

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With SMP, it shouldn't be assumed that there's only one CPU to set
timers.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This commit is contained in:
Ederson de Souza 2021-12-29 10:47:21 -08:00 committed by Anas Nashif
parent d9ab35577b
commit d27cdd1a1e
1 changed files with 15 additions and 2 deletions
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17
drivers/timer/riscv_machine_timer.c
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@ -21,12 +21,17 @@
static struct k_spinlock lock;
static uint64_t last_count;
static uint64_t get_hart_mtimecmp(void)
{
return RISCV_MTIMECMP_BASE + (_current_cpu->id * 8);
}
static void set_mtimecmp(uint64_t time)
{
#ifdef CONFIG_64BIT
*(volatile uint64_t *)RISCV_MTIMECMP_BASE = time;
*(volatile uint64_t *)get_hart_mtimecmp() = time;
#else
volatile uint32_t *r = (uint32_t *)RISCV_MTIMECMP_BASE;
volatile uint32_t *r = (uint32_t *)(uint32_t)get_hart_mtimecmp();
/* Per spec, the RISC-V MTIME/MTIMECMP registers are 64 bit,
* but are NOT internally latched for multiword transfers. So
@ -155,5 +160,13 @@ static int sys_clock_driver_init(const struct device *dev)
return 0;
}
#ifdef CONFIG_SMP
void smp_timer_init(void)
{
set_mtimecmp(last_count + CYC_PER_TICK);
irq_enable(RISCV_MACHINE_TIMER_IRQ);
}
#endif
SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);