cache: Rework headers and force inlining
The current headers do not allow the full inlining of the cache functions. Rework and cleanup the headers to allow for the full inlining. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Anas Nashif
parent
de90dfccbc
commit
d3ed4a784b
290
include/zephyr/arch/cache.h
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290
include/zephyr/arch/cache.h
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@ -0,0 +1,290 @@
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/*
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* Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* Public APIs for architectural cache controller drivers
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_CACHE_H_
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#define ZEPHYR_INCLUDE_ARCH_CACHE_H_
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/**
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* @brief Cache Controller Interface
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* @defgroup cache_arch_interface Cache Controller Interface
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* @ingroup io_interfaces
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* @{
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*/
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#if defined(CONFIG_DCACHE)
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/**
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* @brief Enable the d-cache
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*
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* Enable the data cache.
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*/
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extern void arch_dcache_enable(void);
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#define cache_data_enable arch_dcache_enable
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/**
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* @brief Disable the d-cache
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*
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* Disable the data cache.
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*/
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extern void arch_dcache_disable(void);
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#define cache_data_disable arch_dcache_disable
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/**
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* @brief Flush the d-cache
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*
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* Flush the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_flush_all(void);
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#define cache_data_flush_all arch_dcache_flush_all
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/**
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* @brief Invalidate the d-cache
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*
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* Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_invd_all(void);
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#define cache_data_invd_all arch_dcache_invd_all
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/**
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* @brief Flush and Invalidate the d-cache
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*
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* Flush and Invalidate the whole data cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_flush_and_invd_all(void);
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#define cache_data_flush_and_invd_all arch_dcache_flush_and_invd_all
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/**
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* @brief Flush an address range in the d-cache
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*
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* Flush the specified address range of the data cache.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_flush_range(void *addr, size_t size);
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#define cache_data_flush_range(addr, size) arch_dcache_flush_range(addr, size)
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/**
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* @brief Invalidate an address range in the d-cache
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*
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* Invalidate the specified address range of the data cache.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_invd_range(void *addr, size_t size);
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#define cache_data_invd_range(addr, size) arch_dcache_invd_range(addr, size)
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/**
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* @brief Flush and Invalidate an address range in the d-cache
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*
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* Flush and Invalidate the specified address range of the data cache.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_dcache_flush_and_invd_range(void *addr, size_t size);
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#define cache_data_flush_and_invd_range(addr, size) \
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arch_dcache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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/**
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*
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* @brief Get the d-cache line size.
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*
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* The API is provided to dynamically detect the data cache line size at run
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* time.
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*
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* The function must be implemented only when CONFIG_DCACHE_LINE_SIZE_DETECT is
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* defined.
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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extern size_t arch_dcache_line_size_get(void);
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#define cache_data_line_size_get arch_dcache_line_size_get
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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/**
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* @brief Enable the i-cache
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*
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* Enable the instruction cache.
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*/
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extern void arch_icache_enable(void);
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#define cache_instr_enable arch_icache_enable
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/**
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* @brief Disable the i-cache
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*
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* Disable the instruction cache.
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*/
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extern void arch_icache_disable(void);
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#define cache_instr_disable arch_icache_disable
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/**
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* @brief Flush the i-cache
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*
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* Flush the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_flush_all(void);
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#define cache_instr_flush_all arch_icache_flush_all
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/**
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* @brief Invalidate the i-cache
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*
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* Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_invd_all(void);
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#define cache_instr_invd_all arch_icache_invd_all
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/**
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* @brief Flush and Invalidate the i-cache
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*
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* Flush and Invalidate the whole instruction cache.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_flush_and_invd_all(void);
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#define cache_instr_flush_and_invd_all arch_icache_flush_and_invd_all
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/**
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* @brief Flush an address range in the i-cache
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*
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* Flush the specified address range of the instruction cache.
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*
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* @param addr Starting address to flush.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_flush_range(void *addr, size_t size);
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#define cache_instr_flush_range(addr, size) arch_icache_flush_range(addr, size)
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/**
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* @brief Invalidate an address range in the i-cache
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*
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* Invalidate the specified address range of the instruction cache.
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*
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* @param addr Starting address to invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_invd_range(void *addr, size_t size);
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#define cache_instr_invd_range(addr, size) arch_icache_invd_range(addr, size)
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/**
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* @brief Flush and Invalidate an address range in the i-cache
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*
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* Flush and Invalidate the specified address range of the instruction cache.
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*
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* @param addr Starting address to flush and invalidate.
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* @param size Range size.
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*
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* @retval 0 If succeeded.
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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extern int arch_icache_flush_and_invd_range(void *addr, size_t size);
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#define cache_instr_flush_and_invd_range(addr, size) \
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arch_icache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
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/**
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*
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* @brief Get the i-cache line size.
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*
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* The API is provided to dynamically detect the instruction cache line size at
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* run time.
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*
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* The function must be implemented only when CONFIG_ICACHE_LINE_SIZE_DETECT is
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* defined.
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*
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* @retval size Size of the d-cache line.
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* @retval 0 If the d-cache is not enabled.
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*/
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extern size_t arch_icache_line_size_get(void);
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#define cache_instr_line_size_get arch_icache_line_size_get
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_ICACHE */
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/**
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* @}
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*/
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#endif /* ZEPHYR_INCLUDE_ARCH_CACHE_H_ */
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@ -21,98 +21,12 @@ extern "C" {
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#endif
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#if defined(CONFIG_EXTERNAL_CACHE)
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#include <zephyr/drivers/cache.h>
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/*
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* External cache API driver interface mirrored in
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* include/zephyr/drivers/cache.h
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*/
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#if defined(CONFIG_DCACHE)
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extern void cache_data_enable(void);
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extern void cache_data_disable(void);
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extern int cache_data_flush_all(void);
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extern int cache_data_invd_all(void);
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extern int cache_data_flush_and_invd_all(void);
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extern int cache_data_flush_range(void *addr, size_t size);
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extern int cache_data_invd_range(void *addr, size_t size);
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extern int cache_data_flush_and_invd_range(void *addr, size_t size);
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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extern size_t cache_data_line_size_get(void);
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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extern void cache_instr_enable(void);
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extern void cache_instr_disable(void);
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extern int cache_instr_flush_all(void);
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extern int cache_instr_invd_all(void);
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extern int cache_instr_flush_and_invd_all(void);
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extern int cache_instr_flush_range(void *addr, size_t size);
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extern int cache_instr_invd_range(void *addr, size_t size);
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extern int cache_instr_flush_and_invd_range(void *addr, size_t size);
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#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
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extern size_t cache_instr_line_size_get(void);
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_ICACHE */
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#else /* CONFIG_ARCH_CACHE */
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/*
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* Arch cache API interface mirrored in
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* include/zephyr/sys/arch_interface.h
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*/
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#if defined(CONFIG_DCACHE)
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#define cache_data_enable arch_dcache_enable
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#define cache_data_disable arch_dcache_disable
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#define cache_data_flush_all arch_dcache_flush_all
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#define cache_data_invd_all arch_dcache_invd_all
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#define cache_data_flush_and_invd_all arch_dcache_flush_and_invd_all
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#define cache_data_flush_range(addr, size) arch_dcache_flush_range(addr, size)
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#define cache_data_invd_range(addr, size) arch_dcache_invd_range(addr, size)
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#define cache_data_flush_and_invd_range(addr, size) \
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arch_dcache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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#define cache_data_line_size_get arch_dcache_line_size_get
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#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_DCACHE */
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#if defined(CONFIG_ICACHE)
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#define cache_instr_enable arch_icache_enable
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#define cache_instr_disable arch_icache_disable
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#define cache_instr_flush_all arch_icache_flush_all
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#define cache_instr_invd_all arch_icache_invd_all
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#define cache_instr_flush_and_invd_all arch_icache_flush_and_invd_all
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#define cache_instr_flush_range(addr, size) arch_icache_flush_range(addr, size)
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#define cache_instr_invd_range(addr, size) arch_icache_invd_range(addr, size)
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#define cache_instr_flush_and_invd_range(addr, size) \
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arch_icache_flush_and_invd_range(addr, size)
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#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
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#define cache_instr_line_size_get arch_icache_line_size_get
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#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
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#endif /* CONFIG_ICACHE */
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#endif /* CONFIG_EXTERNAL_CACHE */
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#elif defined(CONFIG_ARCH_CACHE)
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#include <zephyr/arch/cache.h>
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#endif
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/**
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* @defgroup cache_interface Cache Interface
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@ -134,7 +48,7 @@ extern size_t cache_instr_line_size_get(void);
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* Enable the data cache
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*
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*/
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static inline void sys_cache_data_enable(void)
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static ALWAYS_INLINE void sys_cache_data_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_enable();
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@ -147,7 +61,7 @@ static inline void sys_cache_data_enable(void)
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* Disable the data cache
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*
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*/
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static inline void sys_cache_data_disable(void)
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static ALWAYS_INLINE void sys_cache_data_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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cache_data_disable();
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@ -160,7 +74,7 @@ static inline void sys_cache_data_disable(void)
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* Enable the instruction cache
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*
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*/
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static inline void sys_cache_instr_enable(void)
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static ALWAYS_INLINE void sys_cache_instr_enable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_enable();
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@ -173,7 +87,7 @@ static inline void sys_cache_instr_enable(void)
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* Disable the instruction cache
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*
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*/
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static inline void sys_cache_instr_disable(void)
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static ALWAYS_INLINE void sys_cache_instr_disable(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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cache_instr_disable();
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@ -189,7 +103,7 @@ static inline void sys_cache_instr_disable(void)
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_data_flush_all(void)
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static ALWAYS_INLINE int sys_cache_data_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_flush_all();
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@ -206,7 +120,7 @@ static inline int sys_cache_data_flush_all(void)
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_flush_all(void)
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static ALWAYS_INLINE int sys_cache_instr_flush_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_flush_all();
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@ -223,7 +137,7 @@ static inline int sys_cache_instr_flush_all(void)
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_data_invd_all(void)
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static ALWAYS_INLINE int sys_cache_data_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
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return cache_data_invd_all();
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@ -240,7 +154,7 @@ static inline int sys_cache_data_invd_all(void)
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
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static inline int sys_cache_instr_invd_all(void)
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static ALWAYS_INLINE int sys_cache_instr_invd_all(void)
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{
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#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
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return cache_instr_invd_all();
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@ -257,7 +171,7 @@ static inline int sys_cache_instr_invd_all(void)
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* @retval -ENOTSUP If not supported.
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* @retval -errno Negative errno for other failures.
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*/
|
||||
static inline int sys_cache_data_flush_and_invd_all(void)
|
||||
static ALWAYS_INLINE int sys_cache_data_flush_and_invd_all(void)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
|
||||
return cache_data_flush_and_invd_all();
|
||||
|
|
@ -274,7 +188,7 @@ static inline int sys_cache_data_flush_and_invd_all(void)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
static inline int sys_cache_instr_flush_and_invd_all(void)
|
||||
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_all(void)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
|
||||
return cache_instr_flush_and_invd_all();
|
||||
|
|
@ -294,8 +208,9 @@ static inline int sys_cache_instr_flush_and_invd_all(void)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
__syscall int sys_cache_data_flush_range(void *addr, size_t size);
|
||||
static inline int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
|
||||
__syscall_always_inline int sys_cache_data_flush_range(void *addr, size_t size);
|
||||
|
||||
static ALWAYS_INLINE int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
|
||||
return cache_data_flush_range(addr, size);
|
||||
|
|
@ -318,7 +233,7 @@ static inline int z_impl_sys_cache_data_flush_range(void *addr, size_t size)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
static inline int sys_cache_instr_flush_range(void *addr, size_t size)
|
||||
static ALWAYS_INLINE int sys_cache_instr_flush_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
|
||||
return cache_instr_flush_range(addr, size);
|
||||
|
|
@ -341,8 +256,9 @@ static inline int sys_cache_instr_flush_range(void *addr, size_t size)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
__syscall int sys_cache_data_invd_range(void *addr, size_t size);
|
||||
static inline int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
|
||||
__syscall_always_inline int sys_cache_data_invd_range(void *addr, size_t size);
|
||||
|
||||
static ALWAYS_INLINE int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
|
||||
return cache_data_invd_range(addr, size);
|
||||
|
|
@ -365,7 +281,7 @@ static inline int z_impl_sys_cache_data_invd_range(void *addr, size_t size)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
static inline int sys_cache_instr_invd_range(void *addr, size_t size)
|
||||
static ALWAYS_INLINE int sys_cache_instr_invd_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
|
||||
return cache_instr_invd_range(addr, size);
|
||||
|
|
@ -388,8 +304,9 @@ static inline int sys_cache_instr_invd_range(void *addr, size_t size)
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
__syscall int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
|
||||
static inline int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
|
||||
__syscall_always_inline int sys_cache_data_flush_and_invd_range(void *addr, size_t size);
|
||||
|
||||
static ALWAYS_INLINE int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
|
||||
return cache_data_flush_and_invd_range(addr, size);
|
||||
|
|
@ -412,7 +329,7 @@ static inline int z_impl_sys_cache_data_flush_and_invd_range(void *addr, size_t
|
|||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
static inline int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
|
||||
static ALWAYS_INLINE int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
|
||||
{
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ICACHE)
|
||||
return cache_instr_flush_and_invd_range(addr, size);
|
||||
|
|
@ -439,7 +356,7 @@ static inline int sys_cache_instr_flush_and_invd_range(void *addr, size_t size)
|
|||
* @retval size Size of the d-cache line.
|
||||
* @retval 0 If the d-cache is not enabled.
|
||||
*/
|
||||
static inline size_t sys_cache_data_line_size_get(void)
|
||||
static ALWAYS_INLINE size_t sys_cache_data_line_size_get(void)
|
||||
{
|
||||
#ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
|
||||
return cache_data_line_size_get();
|
||||
|
|
@ -466,7 +383,7 @@ static inline size_t sys_cache_data_line_size_get(void)
|
|||
* @retval size Size of the d-cache line.
|
||||
* @retval 0 If the d-cache is not enabled.
|
||||
*/
|
||||
static inline size_t sys_cache_instr_line_size_get(void)
|
||||
static ALWAYS_INLINE size_t sys_cache_instr_line_size_get(void)
|
||||
{
|
||||
#ifdef CONFIG_ICACHE_LINE_SIZE_DETECT
|
||||
return cache_instr_line_size_get();
|
||||
|
|
@ -478,7 +395,7 @@ static inline size_t sys_cache_instr_line_size_get(void)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_LIBMETAL
|
||||
static inline void sys_cache_flush(void *addr, size_t size)
|
||||
static ALWAYS_INLINE void sys_cache_flush(void *addr, size_t size)
|
||||
{
|
||||
sys_cache_data_flush_range(addr, size);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1030,236 +1030,6 @@ int arch_gdb_remove_breakpoint(struct gdb_ctx *ctx, uint8_t type,
|
|||
#endif
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* @defgroup arch_cache Architecture-specific cache functions
|
||||
* @ingroup arch-interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_ARCH_CACHE)
|
||||
#if defined(CONFIG_DCACHE)
|
||||
|
||||
/**
|
||||
* @brief Enable the d-cache
|
||||
*
|
||||
* Enable the data cache.
|
||||
*/
|
||||
|
||||
void arch_dcache_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the d-cache
|
||||
*
|
||||
* Disable the data cache.
|
||||
*/
|
||||
void arch_dcache_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Flush the d-cache
|
||||
*
|
||||
* Flush the whole data cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_flush_all(void);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the d-cache
|
||||
*
|
||||
* Invalidate the whole data cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_invd_all(void);
|
||||
|
||||
/**
|
||||
* @brief Flush and Invalidate the d-cache
|
||||
*
|
||||
* Flush and Invalidate the whole data cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_flush_and_invd_all(void);
|
||||
|
||||
/**
|
||||
* @brief Flush an address range in the d-cache
|
||||
*
|
||||
* Flush the specified address range of the data cache.
|
||||
*
|
||||
* @param addr Starting address to flush.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_flush_range(void *addr, size_t size);
|
||||
|
||||
/**
|
||||
* @brief Invalidate an address range in the d-cache
|
||||
*
|
||||
* Invalidate the specified address range of the data cache.
|
||||
*
|
||||
* @param addr Starting address to invalidate.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_invd_range(void *addr, size_t size);
|
||||
|
||||
/**
|
||||
* @brief Flush and Invalidate an address range in the d-cache
|
||||
*
|
||||
* Flush and Invalidate the specified address range of the data cache.
|
||||
*
|
||||
* @param addr Starting address to flush and invalidate.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_dcache_flush_and_invd_range(void *addr, size_t size);
|
||||
|
||||
#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
|
||||
/**
|
||||
*
|
||||
* @brief Get the the d-cache line size.
|
||||
*
|
||||
* The API is provided to dynamically detect the data cache line size at run
|
||||
* time.
|
||||
*
|
||||
* The function must be implemented only when CONFIG_DCACHE_LINE_SIZE_DETECT is
|
||||
* defined.
|
||||
*
|
||||
* @retval size Size of the d-cache line.
|
||||
* @retval 0 If the d-cache is not enabled.
|
||||
*/
|
||||
size_t arch_dcache_line_size_get(void);
|
||||
#endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
|
||||
|
||||
#endif /* CONFIG_DCACHE */
|
||||
|
||||
#if defined(CONFIG_ICACHE)
|
||||
/**
|
||||
* @brief Enable the i-cache
|
||||
*
|
||||
* Enable the instruction cache.
|
||||
*/
|
||||
void arch_icache_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable the i-cache
|
||||
*
|
||||
* Disable the instruction cache.
|
||||
*/
|
||||
void arch_icache_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Flush the i-cache
|
||||
*
|
||||
* Flush the whole instruction cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_flush_all(void);
|
||||
|
||||
/**
|
||||
* @brief Invalidate the i-cache
|
||||
*
|
||||
* Invalidate the whole instruction cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_invd_all(void);
|
||||
|
||||
/**
|
||||
* @brief Flush and Invalidate the i-cache
|
||||
*
|
||||
* Flush and Invalidate the whole instruction cache.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_flush_and_invd_all(void);
|
||||
|
||||
/**
|
||||
* @brief Flush an address range in the i-cache
|
||||
*
|
||||
* Flush the specified address range of the instruction cache.
|
||||
*
|
||||
* @param addr Starting address to flush.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_flush_range(void *addr, size_t size);
|
||||
|
||||
/**
|
||||
* @brief Invalidate an address range in the i-cache
|
||||
*
|
||||
* Invalidate the specified address range of the instruction cache.
|
||||
*
|
||||
* @param addr Starting address to invalidate.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_invd_range(void *addr, size_t size);
|
||||
|
||||
/**
|
||||
* @brief Flush and Invalidate an address range in the i-cache
|
||||
*
|
||||
* Flush and Invalidate the specified address range of the instruction cache.
|
||||
*
|
||||
* @param addr Starting address to flush and invalidate.
|
||||
* @param size Range size.
|
||||
*
|
||||
* @retval 0 If succeeded.
|
||||
* @retval -ENOTSUP If not supported.
|
||||
* @retval -errno Negative errno for other failures.
|
||||
*/
|
||||
int arch_icache_flush_and_invd_range(void *addr, size_t size);
|
||||
|
||||
#if defined(CONFIG_ICACHE_LINE_SIZE_DETECT)
|
||||
/**
|
||||
*
|
||||
* @brief Get the the i-cache line size.
|
||||
*
|
||||
* The API is provided to dynamically detect the instruction cache line size at
|
||||
* run time.
|
||||
*
|
||||
* The function must be implemented only when CONFIG_ICACHE_LINE_SIZE_DETECT is
|
||||
* defined.
|
||||
*
|
||||
* @retval size Size of the d-cache line.
|
||||
* @retval 0 If the d-cache is not enabled.
|
||||
*/
|
||||
size_t arch_icache_line_size_get(void);
|
||||
#endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */
|
||||
|
||||
#endif /* CONFIG_ICACHE */
|
||||
#endif /* CONFIG_CACHE_MANAGEMENT && CONFIG_ARCH_CACHE */
|
||||
|
||||
/** @} */
|
||||
|
||||
#ifdef CONFIG_TIMING_FUNCTIONS
|
||||
#include <zephyr/timing/types.h>
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue