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drivers/spi: stm32: Convert to devicetree pinctrl generation

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Convert STM32 SPI driver to device pinctrl configuration.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2020-10-12 11:36:02 +02:00 committed by Kumar Gala
parent 6187c8b8df
commit d4e390ce63
4 changed files with 66 additions and 1 deletions
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39
drivers/spi/spi_ll_stm32.c
View file

@ -20,6 +20,7 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
#include <dt-bindings/dma/stm32_dma.h>
#include <drivers/dma.h>
#endif
#include <pinmux/stm32/pinmux_stm32.h>
#include <drivers/clock_control/stm32_clock_control.h>
#include <drivers/clock_control.h>
@ -51,7 +52,6 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
#endif
#endif /* CONFIG_SOC_SERIES_STM32MP1X */
#ifdef CONFIG_SPI_STM32_DMA
/* dummy value used for transferring NOP when tx buf is null
* and use as dummy sink for when rx buf is null
@ -798,6 +798,38 @@ static int spi_stm32_init(const struct device *dev)
return -EIO;
}
/* Configure dt provided device signals when available */
if (cfg->pinctrl_list_size != 0) {
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl)
int remap;
/* Check that remap configuration is coherent across pins */
remap = stm32_dt_pinctrl_remap_check(cfg->pinctrl_list,
cfg->pinctrl_list_size);
if (remap < 0) {
return remap;
}
/* A valid remapping configuration is provided */
/* Apply remapping before proceeding with pin configuration */
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
switch ((uint32_t)cfg->spi) {
#if DT_NODE_HAS_STATUS(DT_NODELABEL(spi1), okay)
case DT_REG_ADDR(DT_NODELABEL(spi1)):
if (remap == REMAP_1) {
LL_GPIO_AF_EnableRemap_SPI1();
} else {
LL_GPIO_AF_DisableRemap_SPI1();
}
break;
#endif
}
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
stm32_dt_pinctrl_configure(cfg->pinctrl_list,
cfg->pinctrl_list_size);
}
#ifdef CONFIG_SPI_STM32_INTERRUPT
cfg->irq_config(dev);
#endif
@ -897,12 +929,17 @@ static void spi_stm32_irq_config_func_##id(const struct device *dev) \
#define STM32_SPI_INIT(id) \
STM32_SPI_IRQ_HANDLER_DECL(id); \
\
static const struct soc_gpio_pinctrl spi_pins_##id[] = \
ST_STM32_DT_INST_PINCTRL(id, 0); \
\
static const struct spi_stm32_config spi_stm32_cfg_##id = { \
.spi = (SPI_TypeDef *) DT_INST_REG_ADDR(id), \
.pclken = { \
.enr = DT_INST_CLOCKS_CELL(id, bits), \
.bus = DT_INST_CLOCKS_CELL(id, bus) \
}, \
.pinctrl_list = spi_pins_##id, \
.pinctrl_list_size = ARRAY_SIZE(spi_pins_##id), \
STM32_SPI_IRQ_HANDLER_FUNC(id) \
}; \
\

2
drivers/spi/spi_ll_stm32.h
View file

@ -14,6 +14,8 @@ typedef void (*irq_config_func_t)(const struct device *port);
struct spi_stm32_config {
struct stm32_pclken pclken;
SPI_TypeDef *spi;
const struct soc_gpio_pinctrl *pinctrl_list;
size_t pinctrl_list_size;
#ifdef CONFIG_SPI_STM32_INTERRUPT
irq_config_func_t irq_config;
#endif

13
dts/bindings/spi/st,stm32-spi-fifo.yaml
View file

@ -13,3 +13,16 @@ properties:
interrupts:
required: true
pinctrl-0:
type: phandles
required: false
description: |
Pin configuration for SPI signals (MISO, MOSI, SCK and optional NSS).
We expect that the phandles will reference pinctrl nodes.
For example the SPI3 would be
<&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
Example with NSS Pin
<&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12 &spi3_nss_pa15>;

13
dts/bindings/spi/st,stm32-spi.yaml
View file

@ -13,3 +13,16 @@ properties:
interrupts:
required: true
pinctrl-0:
type: phandles
required: false
description: |
Pin configuration for SPI signals (MISO, MOSI, SCK and optional NSS).
We expect that the phandles will reference pinctrl nodes.
For example the SPI3 would be
<&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
Example with NSS Pin
<&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12 &spi3_nss_pa15>;